1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZTargetLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "systemz-lower" 15 16 #include "SystemZISelLowering.h" 17 #include "SystemZ.h" 18 #include "SystemZTargetMachine.h" 19 #include "SystemZSubtarget.h" 20 #include "llvm/DerivedTypes.h" 21 #include "llvm/Function.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/GlobalVariable.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/CodeGen/CallingConvLower.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/PseudoSourceValue.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 34 #include "llvm/CodeGen/ValueTypes.h" 35 #include "llvm/Target/TargetOptions.h" 36 #include "llvm/Support/Debug.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/ADT/VectorExtras.h" 40 using namespace llvm; 41 42 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : 43 TargetLowering(tm, new TargetLoweringObjectFileELF()), 44 Subtarget(*tm.getSubtargetImpl()), TM(tm) { 45 46 RegInfo = TM.getRegisterInfo(); 47 48 // Set up the register classes. 49 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); 50 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); 51 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); 52 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); 53 54 if (!UseSoftFloat) { 55 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); 56 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); 57 } 58 59 // Compute derived properties from the register classes 60 computeRegisterProperties(); 61 62 // Provide all sorts of operation actions 63 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 64 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 65 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 66 67 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); 68 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); 69 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 70 71 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); 72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); 73 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 74 75 setStackPointerRegisterToSaveRestore(SystemZ::R15D); 76 77 // TODO: It may be better to default to latency-oriented scheduling, however 78 // LLVM's current latency-oriented scheduler can't handle physreg definitions 79 // such as SystemZ has with PSW, so set this to the register-pressure 80 // scheduler, because it can. 81 setSchedulingPreference(Sched::RegPressure); 82 83 setBooleanContents(ZeroOrOneBooleanContent); 84 85 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 86 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 87 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 88 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 89 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 90 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool, MVT::i64, Custom); 93 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 94 setOperationAction(ISD::JumpTable, MVT::i64, Custom); 95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); 96 97 setOperationAction(ISD::SDIV, MVT::i32, Expand); 98 setOperationAction(ISD::UDIV, MVT::i32, Expand); 99 setOperationAction(ISD::SDIV, MVT::i64, Expand); 100 setOperationAction(ISD::UDIV, MVT::i64, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 setOperationAction(ISD::UREM, MVT::i32, Expand); 103 setOperationAction(ISD::SREM, MVT::i64, Expand); 104 setOperationAction(ISD::UREM, MVT::i64, Expand); 105 106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 107 108 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 109 setOperationAction(ISD::CTPOP, MVT::i64, Expand); 110 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 111 setOperationAction(ISD::CTTZ, MVT::i64, Expand); 112 setOperationAction(ISD::CTLZ, MVT::i32, Promote); 113 setOperationAction(ISD::CTLZ, MVT::i64, Legal); 114 115 // FIXME: Can we lower these 2 efficiently? 116 setOperationAction(ISD::SETCC, MVT::i32, Expand); 117 setOperationAction(ISD::SETCC, MVT::i64, Expand); 118 setOperationAction(ISD::SETCC, MVT::f32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f64, Expand); 120 setOperationAction(ISD::SELECT, MVT::i32, Expand); 121 setOperationAction(ISD::SELECT, MVT::i64, Expand); 122 setOperationAction(ISD::SELECT, MVT::f32, Expand); 123 setOperationAction(ISD::SELECT, MVT::f64, Expand); 124 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 125 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 128 129 setOperationAction(ISD::MULHS, MVT::i64, Expand); 130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 131 132 // FIXME: Can we support these natively? 133 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 134 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 135 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 136 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 137 138 // Lower some FP stuff 139 setOperationAction(ISD::FSIN, MVT::f32, Expand); 140 setOperationAction(ISD::FSIN, MVT::f64, Expand); 141 setOperationAction(ISD::FCOS, MVT::f32, Expand); 142 setOperationAction(ISD::FCOS, MVT::f64, Expand); 143 setOperationAction(ISD::FREM, MVT::f32, Expand); 144 setOperationAction(ISD::FREM, MVT::f64, Expand); 145 146 // We have only 64-bit bitconverts 147 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 148 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 149 150 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 151 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); 152 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 153 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); 154 155 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 156 157 setMinFunctionAlignment(1); 158 } 159 160 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, 161 SelectionDAG &DAG) const { 162 switch (Op.getOpcode()) { 163 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 164 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 165 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 166 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 167 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 168 default: 169 llvm_unreachable("Should not custom lower this!"); 170 return SDValue(); 171 } 172 } 173 174 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 175 if (UseSoftFloat || (VT != MVT::f32 && VT != MVT::f64)) 176 return false; 177 178 // +0.0 lzer 179 // +0.0f lzdr 180 // -0.0 lzer + lner 181 // -0.0f lzdr + lndr 182 return Imm.isZero() || Imm.isNegZero(); 183 } 184 185 //===----------------------------------------------------------------------===// 186 // SystemZ Inline Assembly Support 187 //===----------------------------------------------------------------------===// 188 189 /// getConstraintType - Given a constraint letter, return the type of 190 /// constraint it is for this target. 191 TargetLowering::ConstraintType 192 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const { 193 if (Constraint.size() == 1) { 194 switch (Constraint[0]) { 195 case 'r': 196 return C_RegisterClass; 197 default: 198 break; 199 } 200 } 201 return TargetLowering::getConstraintType(Constraint); 202 } 203 204 std::pair<unsigned, const TargetRegisterClass*> 205 SystemZTargetLowering:: 206 getRegForInlineAsmConstraint(const std::string &Constraint, 207 EVT VT) const { 208 if (Constraint.size() == 1) { 209 // GCC Constraint Letters 210 switch (Constraint[0]) { 211 default: break; 212 case 'r': // GENERAL_REGS 213 if (VT == MVT::i32) 214 return std::make_pair(0U, SystemZ::GR32RegisterClass); 215 else if (VT == MVT::i128) 216 return std::make_pair(0U, SystemZ::GR128RegisterClass); 217 218 return std::make_pair(0U, SystemZ::GR64RegisterClass); 219 } 220 } 221 222 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 223 } 224 225 //===----------------------------------------------------------------------===// 226 // Calling Convention Implementation 227 //===----------------------------------------------------------------------===// 228 229 #include "SystemZGenCallingConv.inc" 230 231 SDValue 232 SystemZTargetLowering::LowerFormalArguments(SDValue Chain, 233 CallingConv::ID CallConv, 234 bool isVarArg, 235 const SmallVectorImpl<ISD::InputArg> 236 &Ins, 237 DebugLoc dl, 238 SelectionDAG &DAG, 239 SmallVectorImpl<SDValue> &InVals) 240 const { 241 242 switch (CallConv) { 243 default: 244 llvm_unreachable("Unsupported calling convention"); 245 case CallingConv::C: 246 case CallingConv::Fast: 247 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals); 248 } 249 } 250 251 SDValue 252 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 253 CallingConv::ID CallConv, bool isVarArg, 254 bool &isTailCall, 255 const SmallVectorImpl<ISD::OutputArg> &Outs, 256 const SmallVectorImpl<SDValue> &OutVals, 257 const SmallVectorImpl<ISD::InputArg> &Ins, 258 DebugLoc dl, SelectionDAG &DAG, 259 SmallVectorImpl<SDValue> &InVals) const { 260 // SystemZ target does not yet support tail call optimization. 261 isTailCall = false; 262 263 switch (CallConv) { 264 default: 265 llvm_unreachable("Unsupported calling convention"); 266 case CallingConv::Fast: 267 case CallingConv::C: 268 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall, 269 Outs, OutVals, Ins, dl, DAG, InVals); 270 } 271 } 272 273 /// LowerCCCArguments - transform physical registers into virtual registers and 274 /// generate load operations for arguments places on the stack. 275 // FIXME: struct return stuff 276 // FIXME: varargs 277 SDValue 278 SystemZTargetLowering::LowerCCCArguments(SDValue Chain, 279 CallingConv::ID CallConv, 280 bool isVarArg, 281 const SmallVectorImpl<ISD::InputArg> 282 &Ins, 283 DebugLoc dl, 284 SelectionDAG &DAG, 285 SmallVectorImpl<SDValue> &InVals) 286 const { 287 288 MachineFunction &MF = DAG.getMachineFunction(); 289 MachineFrameInfo *MFI = MF.getFrameInfo(); 290 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 291 292 // Assign locations to all of the incoming arguments. 293 SmallVector<CCValAssign, 16> ArgLocs; 294 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 295 ArgLocs, *DAG.getContext()); 296 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ); 297 298 if (isVarArg) 299 report_fatal_error("Varargs not supported yet"); 300 301 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 302 SDValue ArgValue; 303 CCValAssign &VA = ArgLocs[i]; 304 EVT LocVT = VA.getLocVT(); 305 if (VA.isRegLoc()) { 306 // Arguments passed in registers 307 TargetRegisterClass *RC; 308 switch (LocVT.getSimpleVT().SimpleTy) { 309 default: 310 #ifndef NDEBUG 311 errs() << "LowerFormalArguments Unhandled argument type: " 312 << LocVT.getSimpleVT().SimpleTy 313 << "\n"; 314 #endif 315 llvm_unreachable(0); 316 case MVT::i64: 317 RC = SystemZ::GR64RegisterClass; 318 break; 319 case MVT::f32: 320 RC = SystemZ::FP32RegisterClass; 321 break; 322 case MVT::f64: 323 RC = SystemZ::FP64RegisterClass; 324 break; 325 } 326 327 unsigned VReg = RegInfo.createVirtualRegister(RC); 328 RegInfo.addLiveIn(VA.getLocReg(), VReg); 329 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT); 330 } else { 331 // Sanity check 332 assert(VA.isMemLoc()); 333 334 // Create the nodes corresponding to a load from this parameter slot. 335 // Create the frame index object for this incoming parameter... 336 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8, 337 VA.getLocMemOffset(), true); 338 339 // Create the SelectionDAG nodes corresponding to a load 340 // from this parameter 341 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 342 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN, 343 MachinePointerInfo::getFixedStack(FI), 344 false, false, 0); 345 } 346 347 // If this is an 8/16/32-bit value, it is really passed promoted to 64 348 // bits. Insert an assert[sz]ext to capture this, then truncate to the 349 // right size. 350 if (VA.getLocInfo() == CCValAssign::SExt) 351 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue, 352 DAG.getValueType(VA.getValVT())); 353 else if (VA.getLocInfo() == CCValAssign::ZExt) 354 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue, 355 DAG.getValueType(VA.getValVT())); 356 357 if (VA.getLocInfo() != CCValAssign::Full) 358 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 359 360 InVals.push_back(ArgValue); 361 } 362 363 return Chain; 364 } 365 366 /// LowerCCCCallTo - functions arguments are copied from virtual regs to 367 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 368 /// TODO: sret. 369 SDValue 370 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, 371 CallingConv::ID CallConv, bool isVarArg, 372 bool isTailCall, 373 const SmallVectorImpl<ISD::OutputArg> 374 &Outs, 375 const SmallVectorImpl<SDValue> &OutVals, 376 const SmallVectorImpl<ISD::InputArg> &Ins, 377 DebugLoc dl, SelectionDAG &DAG, 378 SmallVectorImpl<SDValue> &InVals) const { 379 MachineFunction &MF = DAG.getMachineFunction(); 380 const TargetFrameLowering *TFI = TM.getFrameLowering(); 381 382 // Offset to first argument stack slot. 383 const unsigned FirstArgOffset = 160; 384 385 // Analyze operands of the call, assigning locations to each operand. 386 SmallVector<CCValAssign, 16> ArgLocs; 387 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 388 ArgLocs, *DAG.getContext()); 389 390 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ); 391 392 // Get a count of how many bytes are to be pushed on the stack. 393 unsigned NumBytes = CCInfo.getNextStackOffset(); 394 395 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes, 396 getPointerTy(), true)); 397 398 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass; 399 SmallVector<SDValue, 12> MemOpChains; 400 SDValue StackPtr; 401 402 // Walk the register/memloc assignments, inserting copies/loads. 403 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 404 CCValAssign &VA = ArgLocs[i]; 405 406 SDValue Arg = OutVals[i]; 407 408 // Promote the value if needed. 409 switch (VA.getLocInfo()) { 410 default: assert(0 && "Unknown loc info!"); 411 case CCValAssign::Full: break; 412 case CCValAssign::SExt: 413 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 414 break; 415 case CCValAssign::ZExt: 416 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 417 break; 418 case CCValAssign::AExt: 419 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 420 break; 421 } 422 423 // Arguments that can be passed on register must be kept at RegsToPass 424 // vector 425 if (VA.isRegLoc()) { 426 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 427 } else { 428 assert(VA.isMemLoc()); 429 430 if (StackPtr.getNode() == 0) 431 StackPtr = 432 DAG.getCopyFromReg(Chain, dl, 433 (TFI->hasFP(MF) ? 434 SystemZ::R11D : SystemZ::R15D), 435 getPointerTy()); 436 437 unsigned Offset = FirstArgOffset + VA.getLocMemOffset(); 438 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), 439 StackPtr, 440 DAG.getIntPtrConstant(Offset)); 441 442 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 443 MachinePointerInfo(), 444 false, false, 0)); 445 } 446 } 447 448 // Transform all store nodes into one single node because all store nodes are 449 // independent of each other. 450 if (!MemOpChains.empty()) 451 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 452 &MemOpChains[0], MemOpChains.size()); 453 454 // Build a sequence of copy-to-reg nodes chained together with token chain and 455 // flag operands which copy the outgoing args into registers. The InFlag in 456 // necessary since all emitted instructions must be stuck together. 457 SDValue InFlag; 458 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 459 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 460 RegsToPass[i].second, InFlag); 461 InFlag = Chain.getValue(1); 462 } 463 464 // If the callee is a GlobalAddress node (quite common, every direct call is) 465 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 466 // Likewise ExternalSymbol -> TargetExternalSymbol. 467 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 468 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy()); 469 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 470 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 471 472 // Returns a chain & a flag for retval copy to use. 473 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 474 SmallVector<SDValue, 8> Ops; 475 Ops.push_back(Chain); 476 Ops.push_back(Callee); 477 478 // Add argument registers to the end of the list so that they are 479 // known live into the call. 480 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 481 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 482 RegsToPass[i].second.getValueType())); 483 484 if (InFlag.getNode()) 485 Ops.push_back(InFlag); 486 487 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 488 InFlag = Chain.getValue(1); 489 490 // Create the CALLSEQ_END node. 491 Chain = DAG.getCALLSEQ_END(Chain, 492 DAG.getConstant(NumBytes, getPointerTy(), true), 493 DAG.getConstant(0, getPointerTy(), true), 494 InFlag); 495 InFlag = Chain.getValue(1); 496 497 // Handle result values, copying them out of physregs into vregs that we 498 // return. 499 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, 500 DAG, InVals); 501 } 502 503 /// LowerCallResult - Lower the result values of a call into the 504 /// appropriate copies out of appropriate physical registers. 505 /// 506 SDValue 507 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 508 CallingConv::ID CallConv, bool isVarArg, 509 const SmallVectorImpl<ISD::InputArg> 510 &Ins, 511 DebugLoc dl, SelectionDAG &DAG, 512 SmallVectorImpl<SDValue> &InVals) const { 513 514 // Assign locations to each value returned by this call. 515 SmallVector<CCValAssign, 16> RVLocs; 516 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs, 517 *DAG.getContext()); 518 519 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ); 520 521 // Copy all of the result registers out of their specified physreg. 522 for (unsigned i = 0; i != RVLocs.size(); ++i) { 523 CCValAssign &VA = RVLocs[i]; 524 525 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 526 VA.getLocVT(), InFlag).getValue(1); 527 SDValue RetValue = Chain.getValue(0); 528 InFlag = Chain.getValue(2); 529 530 // If this is an 8/16/32-bit value, it is really passed promoted to 64 531 // bits. Insert an assert[sz]ext to capture this, then truncate to the 532 // right size. 533 if (VA.getLocInfo() == CCValAssign::SExt) 534 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue, 535 DAG.getValueType(VA.getValVT())); 536 else if (VA.getLocInfo() == CCValAssign::ZExt) 537 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue, 538 DAG.getValueType(VA.getValVT())); 539 540 if (VA.getLocInfo() != CCValAssign::Full) 541 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue); 542 543 InVals.push_back(RetValue); 544 } 545 546 return Chain; 547 } 548 549 550 SDValue 551 SystemZTargetLowering::LowerReturn(SDValue Chain, 552 CallingConv::ID CallConv, bool isVarArg, 553 const SmallVectorImpl<ISD::OutputArg> &Outs, 554 const SmallVectorImpl<SDValue> &OutVals, 555 DebugLoc dl, SelectionDAG &DAG) const { 556 557 // CCValAssign - represent the assignment of the return value to a location 558 SmallVector<CCValAssign, 16> RVLocs; 559 560 // CCState - Info about the registers and stack slot. 561 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 562 RVLocs, *DAG.getContext()); 563 564 // Analize return values. 565 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ); 566 567 // If this is the first return lowered for this function, add the regs to the 568 // liveout set for the function. 569 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 570 for (unsigned i = 0; i != RVLocs.size(); ++i) 571 if (RVLocs[i].isRegLoc()) 572 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 573 } 574 575 SDValue Flag; 576 577 // Copy the result values into the output registers. 578 for (unsigned i = 0; i != RVLocs.size(); ++i) { 579 CCValAssign &VA = RVLocs[i]; 580 SDValue ResValue = OutVals[i]; 581 assert(VA.isRegLoc() && "Can only return in registers!"); 582 583 // If this is an 8/16/32-bit value, it is really should be passed promoted 584 // to 64 bits. 585 if (VA.getLocInfo() == CCValAssign::SExt) 586 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue); 587 else if (VA.getLocInfo() == CCValAssign::ZExt) 588 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue); 589 else if (VA.getLocInfo() == CCValAssign::AExt) 590 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue); 591 592 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag); 593 594 // Guarantee that all emitted copies are stuck together, 595 // avoiding something bad. 596 Flag = Chain.getValue(1); 597 } 598 599 if (Flag.getNode()) 600 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 601 602 // Return Void 603 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); 604 } 605 606 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, 607 ISD::CondCode CC, SDValue &SystemZCC, 608 SelectionDAG &DAG) const { 609 // FIXME: Emit a test if RHS is zero 610 611 bool isUnsigned = false; 612 SystemZCC::CondCodes TCC; 613 switch (CC) { 614 default: 615 llvm_unreachable("Invalid integer condition!"); 616 case ISD::SETEQ: 617 case ISD::SETOEQ: 618 TCC = SystemZCC::E; 619 break; 620 case ISD::SETUEQ: 621 TCC = SystemZCC::NLH; 622 break; 623 case ISD::SETNE: 624 case ISD::SETONE: 625 TCC = SystemZCC::NE; 626 break; 627 case ISD::SETUNE: 628 TCC = SystemZCC::LH; 629 break; 630 case ISD::SETO: 631 TCC = SystemZCC::O; 632 break; 633 case ISD::SETUO: 634 TCC = SystemZCC::NO; 635 break; 636 case ISD::SETULE: 637 if (LHS.getValueType().isFloatingPoint()) { 638 TCC = SystemZCC::NH; 639 break; 640 } 641 isUnsigned = true; // FALLTHROUGH 642 case ISD::SETLE: 643 case ISD::SETOLE: 644 TCC = SystemZCC::LE; 645 break; 646 case ISD::SETUGE: 647 if (LHS.getValueType().isFloatingPoint()) { 648 TCC = SystemZCC::NL; 649 break; 650 } 651 isUnsigned = true; // FALLTHROUGH 652 case ISD::SETGE: 653 case ISD::SETOGE: 654 TCC = SystemZCC::HE; 655 break; 656 case ISD::SETUGT: 657 if (LHS.getValueType().isFloatingPoint()) { 658 TCC = SystemZCC::NLE; 659 break; 660 } 661 isUnsigned = true; // FALLTHROUGH 662 case ISD::SETGT: 663 case ISD::SETOGT: 664 TCC = SystemZCC::H; 665 break; 666 case ISD::SETULT: 667 if (LHS.getValueType().isFloatingPoint()) { 668 TCC = SystemZCC::NHE; 669 break; 670 } 671 isUnsigned = true; // FALLTHROUGH 672 case ISD::SETLT: 673 case ISD::SETOLT: 674 TCC = SystemZCC::L; 675 break; 676 } 677 678 SystemZCC = DAG.getConstant(TCC, MVT::i32); 679 680 DebugLoc dl = LHS.getDebugLoc(); 681 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), 682 dl, MVT::i64, LHS, RHS); 683 } 684 685 686 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 687 SDValue Chain = Op.getOperand(0); 688 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 689 SDValue LHS = Op.getOperand(2); 690 SDValue RHS = Op.getOperand(3); 691 SDValue Dest = Op.getOperand(4); 692 DebugLoc dl = Op.getDebugLoc(); 693 694 SDValue SystemZCC; 695 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 696 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(), 697 Chain, Dest, SystemZCC, Flag); 698 } 699 700 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, 701 SelectionDAG &DAG) const { 702 SDValue LHS = Op.getOperand(0); 703 SDValue RHS = Op.getOperand(1); 704 SDValue TrueV = Op.getOperand(2); 705 SDValue FalseV = Op.getOperand(3); 706 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 707 DebugLoc dl = Op.getDebugLoc(); 708 709 SDValue SystemZCC; 710 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); 711 712 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 713 SmallVector<SDValue, 4> Ops; 714 Ops.push_back(TrueV); 715 Ops.push_back(FalseV); 716 Ops.push_back(SystemZCC); 717 Ops.push_back(Flag); 718 719 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size()); 720 } 721 722 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op, 723 SelectionDAG &DAG) const { 724 DebugLoc dl = Op.getDebugLoc(); 725 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 726 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 727 728 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_; 729 bool ExtraLoadRequired = 730 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false); 731 732 SDValue Result; 733 if (!IsPic && !ExtraLoadRequired) { 734 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 735 Offset = 0; 736 } else { 737 unsigned char OpFlags = 0; 738 if (ExtraLoadRequired) 739 OpFlags = SystemZII::MO_GOTENT; 740 741 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 742 } 743 744 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl, 745 getPointerTy(), Result); 746 747 if (ExtraLoadRequired) 748 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 749 MachinePointerInfo::getGOT(), false, false, 0); 750 751 // If there was a non-zero offset that we didn't fold, create an explicit 752 // addition for it. 753 if (Offset != 0) 754 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 755 DAG.getConstant(Offset, getPointerTy())); 756 757 return Result; 758 } 759 760 // FIXME: PIC here 761 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op, 762 SelectionDAG &DAG) const { 763 DebugLoc dl = Op.getDebugLoc(); 764 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 765 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy()); 766 767 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 768 } 769 770 771 // FIXME: PIC here 772 // FIXME: This is just dirty hack. We need to lower cpool properly 773 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op, 774 SelectionDAG &DAG) const { 775 DebugLoc dl = Op.getDebugLoc(); 776 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 777 778 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 779 CP->getAlignment(), 780 CP->getOffset()); 781 782 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result); 783 } 784 785 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { 786 switch (Opcode) { 787 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG"; 788 case SystemZISD::CALL: return "SystemZISD::CALL"; 789 case SystemZISD::BRCOND: return "SystemZISD::BRCOND"; 790 case SystemZISD::CMP: return "SystemZISD::CMP"; 791 case SystemZISD::UCMP: return "SystemZISD::UCMP"; 792 case SystemZISD::SELECT: return "SystemZISD::SELECT"; 793 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper"; 794 default: return NULL; 795 } 796 } 797 798 //===----------------------------------------------------------------------===// 799 // Other Lowering Code 800 //===----------------------------------------------------------------------===// 801 802 MachineBasicBlock* 803 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 804 MachineBasicBlock *BB) const { 805 const SystemZInstrInfo &TII = *TM.getInstrInfo(); 806 DebugLoc dl = MI->getDebugLoc(); 807 assert((MI->getOpcode() == SystemZ::Select32 || 808 MI->getOpcode() == SystemZ::SelectF32 || 809 MI->getOpcode() == SystemZ::Select64 || 810 MI->getOpcode() == SystemZ::SelectF64) && 811 "Unexpected instr type to insert"); 812 813 // To "insert" a SELECT instruction, we actually have to insert the diamond 814 // control-flow pattern. The incoming instruction knows the destination vreg 815 // to set, the condition code register to branch on, the true/false values to 816 // select between, and a branch opcode to use. 817 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 818 MachineFunction::iterator I = BB; 819 ++I; 820 821 // thisMBB: 822 // ... 823 // TrueVal = ... 824 // cmpTY ccX, r1, r2 825 // jCC copy1MBB 826 // fallthrough --> copy0MBB 827 MachineBasicBlock *thisMBB = BB; 828 MachineFunction *F = BB->getParent(); 829 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 830 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB); 831 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm(); 832 F->insert(I, copy0MBB); 833 F->insert(I, copy1MBB); 834 // Update machine-CFG edges by transferring all successors of the current 835 // block to the new block which will contain the Phi node for the select. 836 copy1MBB->splice(copy1MBB->begin(), BB, 837 llvm::next(MachineBasicBlock::iterator(MI)), 838 BB->end()); 839 copy1MBB->transferSuccessorsAndUpdatePHIs(BB); 840 // Next, add the true and fallthrough blocks as its successors. 841 BB->addSuccessor(copy0MBB); 842 BB->addSuccessor(copy1MBB); 843 844 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB); 845 846 // copy0MBB: 847 // %FalseValue = ... 848 // # fallthrough to copy1MBB 849 BB = copy0MBB; 850 851 // Update machine-CFG edges 852 BB->addSuccessor(copy1MBB); 853 854 // copy1MBB: 855 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 856 // ... 857 BB = copy1MBB; 858 BuildMI(*BB, BB->begin(), dl, TII.get(SystemZ::PHI), 859 MI->getOperand(0).getReg()) 860 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 861 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 862 863 MI->eraseFromParent(); // The pseudo instruction is gone now. 864 return BB; 865 } 866