1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "SystemZMCTargetDesc.h"
10 #include "InstPrinter/SystemZInstPrinter.h"
11 #include "SystemZMCAsmInfo.h"
12 #include "llvm/MC/MCInstrInfo.h"
13 #include "llvm/MC/MCRegisterInfo.h"
14 #include "llvm/MC/MCStreamer.h"
15 #include "llvm/MC/MCSubtargetInfo.h"
16 #include "llvm/Support/TargetRegistry.h"
17 
18 using namespace llvm;
19 
20 #define GET_INSTRINFO_MC_DESC
21 #include "SystemZGenInstrInfo.inc"
22 
23 #define GET_SUBTARGETINFO_MC_DESC
24 #include "SystemZGenSubtargetInfo.inc"
25 
26 #define GET_REGINFO_MC_DESC
27 #include "SystemZGenRegisterInfo.inc"
28 
29 const unsigned SystemZMC::GR32Regs[16] = {
30   SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
31   SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
32   SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
33   SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
34 };
35 
36 const unsigned SystemZMC::GRH32Regs[16] = {
37   SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
38   SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
39   SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
40   SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
41 };
42 
43 const unsigned SystemZMC::GR64Regs[16] = {
44   SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
45   SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
46   SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
47   SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
48 };
49 
50 const unsigned SystemZMC::GR128Regs[16] = {
51   SystemZ::R0Q, 0, SystemZ::R2Q, 0,
52   SystemZ::R4Q, 0, SystemZ::R6Q, 0,
53   SystemZ::R8Q, 0, SystemZ::R10Q, 0,
54   SystemZ::R12Q, 0, SystemZ::R14Q, 0
55 };
56 
57 const unsigned SystemZMC::FP32Regs[16] = {
58   SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
59   SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
60   SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
61   SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
62 };
63 
64 const unsigned SystemZMC::FP64Regs[16] = {
65   SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
66   SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
67   SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
68   SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
69 };
70 
71 const unsigned SystemZMC::FP128Regs[16] = {
72   SystemZ::F0Q, SystemZ::F1Q, 0, 0,
73   SystemZ::F4Q, SystemZ::F5Q, 0, 0,
74   SystemZ::F8Q, SystemZ::F9Q, 0, 0,
75   SystemZ::F12Q, SystemZ::F13Q, 0, 0
76 };
77 
78 const unsigned SystemZMC::VR32Regs[32] = {
79   SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
80   SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
81   SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
82   SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
83   SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
84   SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S,
85   SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S,
86   SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S
87 };
88 
89 const unsigned SystemZMC::VR64Regs[32] = {
90   SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
91   SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
92   SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
93   SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
94   SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
95   SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D,
96   SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D,
97   SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D
98 };
99 
100 const unsigned SystemZMC::VR128Regs[32] = {
101   SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
102   SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
103   SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
104   SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
105   SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
106   SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
107   SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
108   SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
109 };
110 
111 const unsigned SystemZMC::AR32Regs[16] = {
112   SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
113   SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
114   SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
115   SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15
116 };
117 
118 const unsigned SystemZMC::CR64Regs[16] = {
119   SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
120   SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
121   SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
122   SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
123 };
124 
125 unsigned SystemZMC::getFirstReg(unsigned Reg) {
126   static unsigned Map[SystemZ::NUM_TARGET_REGS];
127   static bool Initialized = false;
128   if (!Initialized) {
129     for (unsigned I = 0; I < 16; ++I) {
130       Map[GR32Regs[I]] = I;
131       Map[GRH32Regs[I]] = I;
132       Map[GR64Regs[I]] = I;
133       Map[GR128Regs[I]] = I;
134       Map[FP128Regs[I]] = I;
135       Map[AR32Regs[I]] = I;
136     }
137     for (unsigned I = 0; I < 32; ++I) {
138       Map[VR32Regs[I]] = I;
139       Map[VR64Regs[I]] = I;
140       Map[VR128Regs[I]] = I;
141     }
142   }
143   assert(Reg < SystemZ::NUM_TARGET_REGS);
144   return Map[Reg];
145 }
146 
147 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI,
148                                          const Triple &TT) {
149   MCAsmInfo *MAI = new SystemZMCAsmInfo(TT);
150   MCCFIInstruction Inst =
151       MCCFIInstruction::createDefCfa(nullptr,
152                                      MRI.getDwarfRegNum(SystemZ::R15D, true),
153                                      SystemZMC::CFAOffsetFromInitialSP);
154   MAI->addInitialFrameState(Inst);
155   return MAI;
156 }
157 
158 static MCInstrInfo *createSystemZMCInstrInfo() {
159   MCInstrInfo *X = new MCInstrInfo();
160   InitSystemZMCInstrInfo(X);
161   return X;
162 }
163 
164 static MCRegisterInfo *createSystemZMCRegisterInfo(const Triple &TT) {
165   MCRegisterInfo *X = new MCRegisterInfo();
166   InitSystemZMCRegisterInfo(X, SystemZ::R14D);
167   return X;
168 }
169 
170 static MCSubtargetInfo *
171 createSystemZMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
172   return createSystemZMCSubtargetInfoImpl(TT, CPU, FS);
173 }
174 
175 static MCInstPrinter *createSystemZMCInstPrinter(const Triple &T,
176                                                  unsigned SyntaxVariant,
177                                                  const MCAsmInfo &MAI,
178                                                  const MCInstrInfo &MII,
179                                                  const MCRegisterInfo &MRI) {
180   return new SystemZInstPrinter(MAI, MII, MRI);
181 }
182 
183 extern "C" void LLVMInitializeSystemZTargetMC() {
184   // Register the MCAsmInfo.
185   TargetRegistry::RegisterMCAsmInfo(getTheSystemZTarget(),
186                                     createSystemZMCAsmInfo);
187 
188   // Register the MCCodeEmitter.
189   TargetRegistry::RegisterMCCodeEmitter(getTheSystemZTarget(),
190                                         createSystemZMCCodeEmitter);
191 
192   // Register the MCInstrInfo.
193   TargetRegistry::RegisterMCInstrInfo(getTheSystemZTarget(),
194                                       createSystemZMCInstrInfo);
195 
196   // Register the MCRegisterInfo.
197   TargetRegistry::RegisterMCRegInfo(getTheSystemZTarget(),
198                                     createSystemZMCRegisterInfo);
199 
200   // Register the MCSubtargetInfo.
201   TargetRegistry::RegisterMCSubtargetInfo(getTheSystemZTarget(),
202                                           createSystemZMCSubtargetInfo);
203 
204   // Register the MCAsmBackend.
205   TargetRegistry::RegisterMCAsmBackend(getTheSystemZTarget(),
206                                        createSystemZMCAsmBackend);
207 
208   // Register the MCInstPrinter.
209   TargetRegistry::RegisterMCInstPrinter(getTheSystemZTarget(),
210                                         createSystemZMCInstPrinter);
211 }
212