1 //===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SystemZMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/SystemZMCTargetDesc.h" 15 #include "MCTargetDesc/SystemZMCFixups.h" 16 #include "llvm/MC/MCCodeEmitter.h" 17 #include "llvm/MC/MCContext.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 23 using namespace llvm; 24 25 #define DEBUG_TYPE "mccodeemitter" 26 27 namespace { 28 class SystemZMCCodeEmitter : public MCCodeEmitter { 29 const MCInstrInfo &MCII; 30 MCContext &Ctx; 31 32 public: 33 SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 34 : MCII(mcii), Ctx(ctx) { 35 } 36 37 ~SystemZMCCodeEmitter() override {} 38 39 // OVerride MCCodeEmitter. 40 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 41 SmallVectorImpl<MCFixup> &Fixups, 42 const MCSubtargetInfo &STI) const override; 43 44 private: 45 // Automatically generated by TableGen. 46 uint64_t getBinaryCodeForInstr(const MCInst &MI, 47 SmallVectorImpl<MCFixup> &Fixups, 48 const MCSubtargetInfo &STI) const; 49 50 // Called by the TableGen code to get the binary encoding of operand 51 // MO in MI. Fixups is the list of fixups against MI. 52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 53 SmallVectorImpl<MCFixup> &Fixups, 54 const MCSubtargetInfo &STI) const; 55 56 // Called by the TableGen code to get the binary encoding of an address. 57 // The index or length, if any, is encoded first, followed by the base, 58 // followed by the displacement. In a 20-bit displacement, 59 // the low 12 bits are encoded before the high 8 bits. 60 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 61 SmallVectorImpl<MCFixup> &Fixups, 62 const MCSubtargetInfo &STI) const; 63 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 64 SmallVectorImpl<MCFixup> &Fixups, 65 const MCSubtargetInfo &STI) const; 66 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 67 SmallVectorImpl<MCFixup> &Fixups, 68 const MCSubtargetInfo &STI) const; 69 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 70 SmallVectorImpl<MCFixup> &Fixups, 71 const MCSubtargetInfo &STI) const; 72 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 73 SmallVectorImpl<MCFixup> &Fixups, 74 const MCSubtargetInfo &STI) const; 75 uint64_t getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum, 76 SmallVectorImpl<MCFixup> &Fixups, 77 const MCSubtargetInfo &STI) const; 78 uint64_t getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum, 79 SmallVectorImpl<MCFixup> &Fixups, 80 const MCSubtargetInfo &STI) const; 81 82 // Operand OpNum of MI needs a PC-relative fixup of kind Kind at 83 // Offset bytes from the start of MI. Add the fixup to Fixups 84 // and return the in-place addend, which since we're a RELA target 85 // is always 0. If AllowTLS is true and optional operand OpNum + 1 86 // is present, also emit a TLS call fixup for it. 87 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum, 88 SmallVectorImpl<MCFixup> &Fixups, 89 unsigned Kind, int64_t Offset, 90 bool AllowTLS) const; 91 92 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, 93 SmallVectorImpl<MCFixup> &Fixups, 94 const MCSubtargetInfo &STI) const { 95 return getPCRelEncoding(MI, OpNum, Fixups, 96 SystemZ::FK_390_PC16DBL, 2, false); 97 } 98 uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, 99 SmallVectorImpl<MCFixup> &Fixups, 100 const MCSubtargetInfo &STI) const { 101 return getPCRelEncoding(MI, OpNum, Fixups, 102 SystemZ::FK_390_PC32DBL, 2, false); 103 } 104 uint64_t getPC16DBLTLSEncoding(const MCInst &MI, unsigned OpNum, 105 SmallVectorImpl<MCFixup> &Fixups, 106 const MCSubtargetInfo &STI) const { 107 return getPCRelEncoding(MI, OpNum, Fixups, 108 SystemZ::FK_390_PC16DBL, 2, true); 109 } 110 uint64_t getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum, 111 SmallVectorImpl<MCFixup> &Fixups, 112 const MCSubtargetInfo &STI) const { 113 return getPCRelEncoding(MI, OpNum, Fixups, 114 SystemZ::FK_390_PC32DBL, 2, true); 115 } 116 117 private: 118 uint64_t computeAvailableFeatures(const FeatureBitset &FB) const; 119 void verifyInstructionPredicates(const MCInst &MI, 120 uint64_t AvailableFeatures) const; 121 }; 122 } // end anonymous namespace 123 124 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII, 125 const MCRegisterInfo &MRI, 126 MCContext &Ctx) { 127 return new SystemZMCCodeEmitter(MCII, Ctx); 128 } 129 130 void SystemZMCCodeEmitter:: 131 encodeInstruction(const MCInst &MI, raw_ostream &OS, 132 SmallVectorImpl<MCFixup> &Fixups, 133 const MCSubtargetInfo &STI) const { 134 verifyInstructionPredicates(MI, 135 computeAvailableFeatures(STI.getFeatureBits())); 136 137 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI); 138 unsigned Size = MCII.get(MI.getOpcode()).getSize(); 139 // Big-endian insertion of Size bytes. 140 unsigned ShiftValue = (Size * 8) - 8; 141 for (unsigned I = 0; I != Size; ++I) { 142 OS << uint8_t(Bits >> ShiftValue); 143 ShiftValue -= 8; 144 } 145 } 146 147 uint64_t SystemZMCCodeEmitter:: 148 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 149 SmallVectorImpl<MCFixup> &Fixups, 150 const MCSubtargetInfo &STI) const { 151 if (MO.isReg()) 152 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 153 if (MO.isImm()) 154 return static_cast<uint64_t>(MO.getImm()); 155 llvm_unreachable("Unexpected operand type!"); 156 } 157 158 uint64_t SystemZMCCodeEmitter:: 159 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 160 SmallVectorImpl<MCFixup> &Fixups, 161 const MCSubtargetInfo &STI) const { 162 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 163 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 164 assert(isUInt<4>(Base) && isUInt<12>(Disp)); 165 return (Base << 12) | Disp; 166 } 167 168 uint64_t SystemZMCCodeEmitter:: 169 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 170 SmallVectorImpl<MCFixup> &Fixups, 171 const MCSubtargetInfo &STI) const { 172 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 173 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 174 assert(isUInt<4>(Base) && isInt<20>(Disp)); 175 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12); 176 } 177 178 uint64_t SystemZMCCodeEmitter:: 179 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 180 SmallVectorImpl<MCFixup> &Fixups, 181 const MCSubtargetInfo &STI) const { 182 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 183 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 184 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 185 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index)); 186 return (Index << 16) | (Base << 12) | Disp; 187 } 188 189 uint64_t SystemZMCCodeEmitter:: 190 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 191 SmallVectorImpl<MCFixup> &Fixups, 192 const MCSubtargetInfo &STI) const { 193 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 194 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 195 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 196 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index)); 197 return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8) 198 | ((Disp & 0xff000) >> 12); 199 } 200 201 uint64_t SystemZMCCodeEmitter:: 202 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, 203 SmallVectorImpl<MCFixup> &Fixups, 204 const MCSubtargetInfo &STI) const { 205 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 206 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 207 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI) - 1; 208 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len)); 209 return (Len << 16) | (Base << 12) | Disp; 210 } 211 212 uint64_t SystemZMCCodeEmitter:: 213 getBDRAddr12Encoding(const MCInst &MI, unsigned OpNum, 214 SmallVectorImpl<MCFixup> &Fixups, 215 const MCSubtargetInfo &STI) const { 216 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 217 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 218 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 219 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Len)); 220 return (Len << 16) | (Base << 12) | Disp; 221 } 222 223 uint64_t SystemZMCCodeEmitter:: 224 getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum, 225 SmallVectorImpl<MCFixup> &Fixups, 226 const MCSubtargetInfo &STI) const { 227 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 228 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 229 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 230 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<5>(Index)); 231 return (Index << 16) | (Base << 12) | Disp; 232 } 233 234 uint64_t 235 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum, 236 SmallVectorImpl<MCFixup> &Fixups, 237 unsigned Kind, int64_t Offset, 238 bool AllowTLS) const { 239 const MCOperand &MO = MI.getOperand(OpNum); 240 const MCExpr *Expr; 241 if (MO.isImm()) 242 Expr = MCConstantExpr::create(MO.getImm() + Offset, Ctx); 243 else { 244 Expr = MO.getExpr(); 245 if (Offset) { 246 // The operand value is relative to the start of MI, but the fixup 247 // is relative to the operand field itself, which is Offset bytes 248 // into MI. Add Offset to the relocation value to cancel out 249 // this difference. 250 const MCExpr *OffsetExpr = MCConstantExpr::create(Offset, Ctx); 251 Expr = MCBinaryExpr::createAdd(Expr, OffsetExpr, Ctx); 252 } 253 } 254 Fixups.push_back(MCFixup::create(Offset, Expr, (MCFixupKind)Kind)); 255 256 // Output the fixup for the TLS marker if present. 257 if (AllowTLS && OpNum + 1 < MI.getNumOperands()) { 258 const MCOperand &MOTLS = MI.getOperand(OpNum + 1); 259 Fixups.push_back(MCFixup::create(0, MOTLS.getExpr(), 260 (MCFixupKind)SystemZ::FK_390_TLS_CALL)); 261 } 262 return 0; 263 } 264 265 #define ENABLE_INSTR_PREDICATE_VERIFIER 266 #include "SystemZGenMCCodeEmitter.inc" 267