1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Sparc.h"
14 #include "SparcTargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Support/TargetRegistry.h"
17 using namespace llvm;
18 
19 extern "C" void LLVMInitializeSparcTarget() {
20   // Register the target.
21   RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
22   RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
23 }
24 
25 /// SparcTargetMachine ctor - Create an ILP32 architecture model
26 ///
27 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
28                                        StringRef CPU, StringRef FS,
29                                        const TargetOptions &Options,
30                                        Reloc::Model RM, CodeModel::Model CM,
31                                        CodeGenOpt::Level OL,
32                                        bool is64bit)
33   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
34     Subtarget(TT, CPU, FS, is64bit),
35     DataLayout(Subtarget.getDataLayout()),
36     TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
37     FrameLowering(Subtarget) {
38 }
39 
40 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM) {
41   PM.add(createSparcISelDag(*this));
42   return false;
43 }
44 
45 /// addPreEmitPass - This pass may be implemented by targets that want to run
46 /// passes immediately before machine code is emitted.  This should return
47 /// true if -print-machineinstrs should print out the code after the passes.
48 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM){
49   PM.add(createSparcFPMoverPass(*this));
50   PM.add(createSparcDelaySlotFillerPass(*this));
51   return true;
52 }
53 
54 void SparcV8TargetMachine::anchor() { }
55 
56 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
57                                            StringRef TT, StringRef CPU,
58                                            StringRef FS,
59                                            const TargetOptions &Options,
60                                            Reloc::Model RM,
61                                            CodeModel::Model CM,
62                                            CodeGenOpt::Level OL)
63   : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
64 }
65 
66 void SparcV9TargetMachine::anchor() { }
67 
68 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
69                                            StringRef TT,  StringRef CPU,
70                                            StringRef FS,
71                                            const TargetOptions &Options,
72                                            Reloc::Model RM,
73                                            CodeModel::Model CM,
74                                            CodeGenOpt::Level OL)
75   : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
76 }
77