1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "Sparc.h"
14 #include "SparcTargetMachine.h"
15 #include "llvm/PassManager.h"
16 #include "llvm/Support/TargetRegistry.h"
17 using namespace llvm;
18 
19 extern "C" void LLVMInitializeSparcTarget() {
20   // Register the target.
21   RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
22   RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
23 }
24 
25 /// SparcTargetMachine ctor - Create an ILP32 architecture model
26 ///
27 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
28                                        StringRef CPU, StringRef FS,
29                                        Reloc::Model RM, CodeModel::Model CM,
30                                        CodeGenOpt::Level OL,
31                                        bool is64bit)
32   : LLVMTargetMachine(T, TT, CPU, FS, RM, CM, OL),
33     Subtarget(TT, CPU, FS, is64bit),
34     DataLayout(Subtarget.getDataLayout()),
35     TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget),
36     FrameLowering(Subtarget) {
37 }
38 
39 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM) {
40   PM.add(createSparcISelDag(*this));
41   return false;
42 }
43 
44 /// addPreEmitPass - This pass may be implemented by targets that want to run
45 /// passes immediately before machine code is emitted.  This should return
46 /// true if -print-machineinstrs should print out the code after the passes.
47 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM){
48   PM.add(createSparcFPMoverPass(*this));
49   PM.add(createSparcDelaySlotFillerPass(*this));
50   return true;
51 }
52 
53 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
54                                            StringRef TT, StringRef CPU,
55                                            StringRef FS, Reloc::Model RM,
56                                            CodeModel::Model CM,
57                                            CodeGenOpt::Level OL)
58   : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, false) {
59 }
60 
61 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
62                                            StringRef TT,  StringRef CPU,
63                                            StringRef FS, Reloc::Model RM,
64                                            CodeModel::Model CM,
65                                            CodeGenOpt::Level OL)
66   : SparcTargetMachine(T, TT, CPU, FS, RM, CM, OL, true) {
67 }
68