1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
15 #include "Sparc.h"
16 #include "LeonPasses.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetPassConfig.h"
19 #include "llvm/IR/LegacyPassManager.h"
20 #include "llvm/Support/TargetRegistry.h"
21 using namespace llvm;
22 
23 extern "C" void LLVMInitializeSparcTarget() {
24   // Register the target.
25   RegisterTargetMachine<SparcV8TargetMachine> X(getTheSparcTarget());
26   RegisterTargetMachine<SparcV9TargetMachine> Y(getTheSparcV9Target());
27   RegisterTargetMachine<SparcelTargetMachine> Z(getTheSparcelTarget());
28 }
29 
30 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
31   // Sparc is typically big endian, but some are little.
32   std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
33   Ret += "-m:e";
34 
35   // Some ABIs have 32bit pointers.
36   if (!is64Bit)
37     Ret += "-p:32:32";
38 
39   // Alignments for 64 bit integers.
40   Ret += "-i64:64";
41 
42   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
43   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
44   if (is64Bit)
45     Ret += "-n32:64";
46   else
47     Ret += "-f128:64-n32";
48 
49   if (is64Bit)
50     Ret += "-S128";
51   else
52     Ret += "-S64";
53 
54   return Ret;
55 }
56 
57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
58   if (!RM.hasValue())
59     return Reloc::Static;
60   return *RM;
61 }
62 
63 /// Create an ILP32 architecture model
64 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
65                                        StringRef CPU, StringRef FS,
66                                        const TargetOptions &Options,
67                                        Optional<Reloc::Model> RM,
68                                        CodeModel::Model CM,
69                                        CodeGenOpt::Level OL, bool is64bit)
70     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
71                         getEffectiveRelocModel(RM), CM, OL),
72       TLOF(make_unique<SparcELFTargetObjectFile>()),
73       Subtarget(TT, CPU, FS, *this, is64bit), is64Bit(is64bit) {
74   initAsmInfo();
75 }
76 
77 SparcTargetMachine::~SparcTargetMachine() {}
78 
79 const SparcSubtarget *
80 SparcTargetMachine::getSubtargetImpl(const Function &F) const {
81   Attribute CPUAttr = F.getFnAttribute("target-cpu");
82   Attribute FSAttr = F.getFnAttribute("target-features");
83 
84   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
85                         ? CPUAttr.getValueAsString().str()
86                         : TargetCPU;
87   std::string FS = !FSAttr.hasAttribute(Attribute::None)
88                        ? FSAttr.getValueAsString().str()
89                        : TargetFS;
90 
91   // FIXME: This is related to the code below to reset the target options,
92   // we need to know whether or not the soft float flag is set on the
93   // function, so we can enable it as a subtarget feature.
94   bool softFloat =
95       F.hasFnAttribute("use-soft-float") &&
96       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
97 
98   if (softFloat)
99     FS += FS.empty() ? "+soft-float" : ",+soft-float";
100 
101   auto &I = SubtargetMap[CPU + FS];
102   if (!I) {
103     // This needs to be done before we create a new subtarget since any
104     // creation will depend on the TM and the code generation flags on the
105     // function that reside in TargetOptions.
106     resetTargetOptions(F);
107     I = llvm::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
108                                           this->is64Bit);
109   }
110   return I.get();
111 }
112 
113 namespace {
114 /// Sparc Code Generator Pass Configuration Options.
115 class SparcPassConfig : public TargetPassConfig {
116 public:
117   SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
118     : TargetPassConfig(TM, PM) {}
119 
120   SparcTargetMachine &getSparcTargetMachine() const {
121     return getTM<SparcTargetMachine>();
122   }
123 
124   void addIRPasses() override;
125   bool addInstSelector() override;
126   void addPreEmitPass() override;
127 };
128 } // namespace
129 
130 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
131   return new SparcPassConfig(this, PM);
132 }
133 
134 void SparcPassConfig::addIRPasses() {
135   addPass(createAtomicExpandPass(&getSparcTargetMachine()));
136 
137   TargetPassConfig::addIRPasses();
138 }
139 
140 bool SparcPassConfig::addInstSelector() {
141   addPass(createSparcISelDag(getSparcTargetMachine()));
142   return false;
143 }
144 
145 void SparcPassConfig::addPreEmitPass(){
146   addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
147 
148   if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
149   {
150     addPass(new InsertNOPLoad(getSparcTargetMachine()));
151   }
152   if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD())
153   {
154     addPass(new FixFSMULD(getSparcTargetMachine()));
155   }
156   if (this->getSparcTargetMachine().getSubtargetImpl()->replaceFMULS())
157   {
158     addPass(new ReplaceFMULS(getSparcTargetMachine()));
159   }
160   if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT())
161   {
162     addPass(new FixAllFDIVSQRT(getSparcTargetMachine()));
163   }
164 }
165 
166 void SparcV8TargetMachine::anchor() { }
167 
168 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
169                                            StringRef CPU, StringRef FS,
170                                            const TargetOptions &Options,
171                                            Optional<Reloc::Model> RM,
172                                            CodeModel::Model CM,
173                                            CodeGenOpt::Level OL)
174     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
175 
176 void SparcV9TargetMachine::anchor() { }
177 
178 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
179                                            StringRef CPU, StringRef FS,
180                                            const TargetOptions &Options,
181                                            Optional<Reloc::Model> RM,
182                                            CodeModel::Model CM,
183                                            CodeGenOpt::Level OL)
184     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
185 
186 void SparcelTargetMachine::anchor() {}
187 
188 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
189                                            StringRef CPU, StringRef FS,
190                                            const TargetOptions &Options,
191                                            Optional<Reloc::Model> RM,
192                                            CodeModel::Model CM,
193                                            CodeGenOpt::Level OL)
194     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
195