1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
15 #include "Sparc.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/IR/LegacyPassManager.h"
18 #include "llvm/Support/TargetRegistry.h"
19 using namespace llvm;
20 
21 extern "C" void LLVMInitializeSparcTarget() {
22   // Register the target.
23   RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
24   RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
25   RegisterTargetMachine<SparcelTargetMachine> Z(TheSparcelTarget);
26 }
27 
28 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
29   // Sparc is typically big endian, but some are little.
30   std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
31   Ret += "-m:e";
32 
33   // Some ABIs have 32bit pointers.
34   if (!is64Bit)
35     Ret += "-p:32:32";
36 
37   // Alignments for 64 bit integers.
38   Ret += "-i64:64";
39 
40   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
41   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
42   if (is64Bit)
43     Ret += "-n32:64";
44   else
45     Ret += "-f128:64-n32";
46 
47   if (is64Bit)
48     Ret += "-S128";
49   else
50     Ret += "-S64";
51 
52   return Ret;
53 }
54 
55 /// SparcTargetMachine ctor - Create an ILP32 architecture model
56 ///
57 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
58                                        StringRef CPU, StringRef FS,
59                                        const TargetOptions &Options,
60                                        Reloc::Model RM, CodeModel::Model CM,
61                                        CodeGenOpt::Level OL, bool is64bit)
62     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
63                         RM, CM, OL),
64       TLOF(make_unique<SparcELFTargetObjectFile>()),
65       Subtarget(TT, CPU, FS, *this, is64bit) {
66   initAsmInfo();
67 }
68 
69 SparcTargetMachine::~SparcTargetMachine() {}
70 
71 namespace {
72 /// Sparc Code Generator Pass Configuration Options.
73 class SparcPassConfig : public TargetPassConfig {
74 public:
75   SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
76     : TargetPassConfig(TM, PM) {}
77 
78   SparcTargetMachine &getSparcTargetMachine() const {
79     return getTM<SparcTargetMachine>();
80   }
81 
82   void addIRPasses() override;
83   bool addInstSelector() override;
84   void addPreEmitPass() override;
85 };
86 } // namespace
87 
88 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
89   return new SparcPassConfig(this, PM);
90 }
91 
92 void SparcPassConfig::addIRPasses() {
93   addPass(createAtomicExpandPass(&getSparcTargetMachine()));
94 
95   TargetPassConfig::addIRPasses();
96 }
97 
98 bool SparcPassConfig::addInstSelector() {
99   addPass(createSparcISelDag(getSparcTargetMachine()));
100   return false;
101 }
102 
103 void SparcPassConfig::addPreEmitPass(){
104   addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
105 }
106 
107 void SparcV8TargetMachine::anchor() { }
108 
109 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
110                                            StringRef CPU, StringRef FS,
111                                            const TargetOptions &Options,
112                                            Reloc::Model RM, CodeModel::Model CM,
113                                            CodeGenOpt::Level OL)
114     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
115 
116 void SparcV9TargetMachine::anchor() { }
117 
118 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
119                                            StringRef CPU, StringRef FS,
120                                            const TargetOptions &Options,
121                                            Reloc::Model RM, CodeModel::Model CM,
122                                            CodeGenOpt::Level OL)
123     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
124 
125 void SparcelTargetMachine::anchor() {}
126 
127 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
128                                            StringRef CPU, StringRef FS,
129                                            const TargetOptions &Options,
130                                            Reloc::Model RM, CodeModel::Model CM,
131                                            CodeGenOpt::Level OL)
132     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
133