1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
15 #include "Sparc.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/CodeGen/TargetPassConfig.h"
18 #include "llvm/IR/LegacyPassManager.h"
19 #include "llvm/Support/TargetRegistry.h"
20 using namespace llvm;
21 
22 extern "C" void LLVMInitializeSparcTarget() {
23   // Register the target.
24   RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
25   RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
26   RegisterTargetMachine<SparcelTargetMachine> Z(TheSparcelTarget);
27 }
28 
29 static std::string computeDataLayout(const Triple &T, bool is64Bit) {
30   // Sparc is typically big endian, but some are little.
31   std::string Ret = T.getArch() == Triple::sparcel ? "e" : "E";
32   Ret += "-m:e";
33 
34   // Some ABIs have 32bit pointers.
35   if (!is64Bit)
36     Ret += "-p:32:32";
37 
38   // Alignments for 64 bit integers.
39   Ret += "-i64:64";
40 
41   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
42   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
43   if (is64Bit)
44     Ret += "-n32:64";
45   else
46     Ret += "-f128:64-n32";
47 
48   if (is64Bit)
49     Ret += "-S128";
50   else
51     Ret += "-S64";
52 
53   return Ret;
54 }
55 
56 /// SparcTargetMachine ctor - Create an ILP32 architecture model
57 ///
58 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
59                                        StringRef CPU, StringRef FS,
60                                        const TargetOptions &Options,
61                                        Reloc::Model RM, CodeModel::Model CM,
62                                        CodeGenOpt::Level OL, bool is64bit)
63     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
64                         RM, CM, OL),
65       TLOF(make_unique<SparcELFTargetObjectFile>()),
66       Subtarget(TT, CPU, FS, *this, is64bit) {
67   initAsmInfo();
68 }
69 
70 SparcTargetMachine::~SparcTargetMachine() {}
71 
72 namespace {
73 /// Sparc Code Generator Pass Configuration Options.
74 class SparcPassConfig : public TargetPassConfig {
75 public:
76   SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
77     : TargetPassConfig(TM, PM) {}
78 
79   SparcTargetMachine &getSparcTargetMachine() const {
80     return getTM<SparcTargetMachine>();
81   }
82 
83   void addIRPasses() override;
84   bool addInstSelector() override;
85   void addPreEmitPass() override;
86 };
87 } // namespace
88 
89 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
90   return new SparcPassConfig(this, PM);
91 }
92 
93 void SparcPassConfig::addIRPasses() {
94   addPass(createAtomicExpandPass(&getSparcTargetMachine()));
95 
96   TargetPassConfig::addIRPasses();
97 }
98 
99 bool SparcPassConfig::addInstSelector() {
100   addPass(createSparcISelDag(getSparcTargetMachine()));
101   return false;
102 }
103 
104 void SparcPassConfig::addPreEmitPass(){
105   addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
106 }
107 
108 void SparcV8TargetMachine::anchor() { }
109 
110 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT,
111                                            StringRef CPU, StringRef FS,
112                                            const TargetOptions &Options,
113                                            Reloc::Model RM, CodeModel::Model CM,
114                                            CodeGenOpt::Level OL)
115     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
116 
117 void SparcV9TargetMachine::anchor() { }
118 
119 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT,
120                                            StringRef CPU, StringRef FS,
121                                            const TargetOptions &Options,
122                                            Reloc::Model RM, CodeModel::Model CM,
123                                            CodeGenOpt::Level OL)
124     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
125 
126 void SparcelTargetMachine::anchor() {}
127 
128 SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT,
129                                            StringRef CPU, StringRef FS,
130                                            const TargetOptions &Options,
131                                            Reloc::Model RM, CodeModel::Model CM,
132                                            CodeGenOpt::Level OL)
133     : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
134