1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Sparc implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SparcInstrInfo.h" 15 #include "Sparc.h" 16 #include "SparcMachineFunctionInfo.h" 17 #include "SparcSubtarget.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/MachineFrameInfo.h" 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 22 #include "llvm/CodeGen/MachineMemOperand.h" 23 #include "llvm/CodeGen/MachineRegisterInfo.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 27 using namespace llvm; 28 29 #define GET_INSTRINFO_CTOR_DTOR 30 #include "SparcGenInstrInfo.inc" 31 32 // Pin the vtable to this file. 33 void SparcInstrInfo::anchor() {} 34 35 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 36 : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(), 37 Subtarget(ST) {} 38 39 /// isLoadFromStackSlot - If the specified machine instruction is a direct 40 /// load from a stack slot, return the virtual or physical register number of 41 /// the destination along with the FrameIndex of the loaded stack slot. If 42 /// not, return 0. This predicate must return 0 if the instruction has 43 /// any side effects other than loading from the stack slot. 44 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 45 int &FrameIndex) const { 46 if (MI->getOpcode() == SP::LDri || 47 MI->getOpcode() == SP::LDXri || 48 MI->getOpcode() == SP::LDFri || 49 MI->getOpcode() == SP::LDDFri || 50 MI->getOpcode() == SP::LDQFri) { 51 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 52 MI->getOperand(2).getImm() == 0) { 53 FrameIndex = MI->getOperand(1).getIndex(); 54 return MI->getOperand(0).getReg(); 55 } 56 } 57 return 0; 58 } 59 60 /// isStoreToStackSlot - If the specified machine instruction is a direct 61 /// store to a stack slot, return the virtual or physical register number of 62 /// the source reg along with the FrameIndex of the loaded stack slot. If 63 /// not, return 0. This predicate must return 0 if the instruction has 64 /// any side effects other than storing to the stack slot. 65 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 66 int &FrameIndex) const { 67 if (MI->getOpcode() == SP::STri || 68 MI->getOpcode() == SP::STXri || 69 MI->getOpcode() == SP::STFri || 70 MI->getOpcode() == SP::STDFri || 71 MI->getOpcode() == SP::STQFri) { 72 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 73 MI->getOperand(1).getImm() == 0) { 74 FrameIndex = MI->getOperand(0).getIndex(); 75 return MI->getOperand(2).getReg(); 76 } 77 } 78 return 0; 79 } 80 81 static bool IsIntegerCC(unsigned CC) 82 { 83 return (CC <= SPCC::ICC_VC); 84 } 85 86 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC) 87 { 88 switch(CC) { 89 case SPCC::ICC_A: return SPCC::ICC_N; 90 case SPCC::ICC_N: return SPCC::ICC_A; 91 case SPCC::ICC_NE: return SPCC::ICC_E; 92 case SPCC::ICC_E: return SPCC::ICC_NE; 93 case SPCC::ICC_G: return SPCC::ICC_LE; 94 case SPCC::ICC_LE: return SPCC::ICC_G; 95 case SPCC::ICC_GE: return SPCC::ICC_L; 96 case SPCC::ICC_L: return SPCC::ICC_GE; 97 case SPCC::ICC_GU: return SPCC::ICC_LEU; 98 case SPCC::ICC_LEU: return SPCC::ICC_GU; 99 case SPCC::ICC_CC: return SPCC::ICC_CS; 100 case SPCC::ICC_CS: return SPCC::ICC_CC; 101 case SPCC::ICC_POS: return SPCC::ICC_NEG; 102 case SPCC::ICC_NEG: return SPCC::ICC_POS; 103 case SPCC::ICC_VC: return SPCC::ICC_VS; 104 case SPCC::ICC_VS: return SPCC::ICC_VC; 105 106 case SPCC::FCC_A: return SPCC::FCC_N; 107 case SPCC::FCC_N: return SPCC::FCC_A; 108 case SPCC::FCC_U: return SPCC::FCC_O; 109 case SPCC::FCC_O: return SPCC::FCC_U; 110 case SPCC::FCC_G: return SPCC::FCC_ULE; 111 case SPCC::FCC_LE: return SPCC::FCC_UG; 112 case SPCC::FCC_UG: return SPCC::FCC_LE; 113 case SPCC::FCC_ULE: return SPCC::FCC_G; 114 case SPCC::FCC_L: return SPCC::FCC_UGE; 115 case SPCC::FCC_GE: return SPCC::FCC_UL; 116 case SPCC::FCC_UL: return SPCC::FCC_GE; 117 case SPCC::FCC_UGE: return SPCC::FCC_L; 118 case SPCC::FCC_LG: return SPCC::FCC_UE; 119 case SPCC::FCC_UE: return SPCC::FCC_LG; 120 case SPCC::FCC_NE: return SPCC::FCC_E; 121 case SPCC::FCC_E: return SPCC::FCC_NE; 122 123 case SPCC::CPCC_A: return SPCC::CPCC_N; 124 case SPCC::CPCC_N: return SPCC::CPCC_A; 125 case SPCC::CPCC_3: // Fall through 126 case SPCC::CPCC_2: // Fall through 127 case SPCC::CPCC_23: // Fall through 128 case SPCC::CPCC_1: // Fall through 129 case SPCC::CPCC_13: // Fall through 130 case SPCC::CPCC_12: // Fall through 131 case SPCC::CPCC_123: // Fall through 132 case SPCC::CPCC_0: // Fall through 133 case SPCC::CPCC_03: // Fall through 134 case SPCC::CPCC_02: // Fall through 135 case SPCC::CPCC_023: // Fall through 136 case SPCC::CPCC_01: // Fall through 137 case SPCC::CPCC_013: // Fall through 138 case SPCC::CPCC_012: 139 // "Opposite" code is not meaningful, as we don't know 140 // what the CoProc condition means here. The cond-code will 141 // only be used in inline assembler, so this code should 142 // not be reached in a normal compilation pass. 143 llvm_unreachable("Meaningless inversion of co-processor cond code"); 144 } 145 llvm_unreachable("Invalid cond code"); 146 } 147 148 static bool isUncondBranchOpcode(int Opc) { return Opc == SP::BA; } 149 150 static bool isCondBranchOpcode(int Opc) { 151 return Opc == SP::FBCOND || Opc == SP::BCOND; 152 } 153 154 static bool isIndirectBranchOpcode(int Opc) { 155 return Opc == SP::BINDrr || Opc == SP::BINDri; 156 } 157 158 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, 159 SmallVectorImpl<MachineOperand> &Cond) { 160 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm())); 161 Target = LastInst->getOperand(0).getMBB(); 162 } 163 164 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 165 MachineBasicBlock *&TBB, 166 MachineBasicBlock *&FBB, 167 SmallVectorImpl<MachineOperand> &Cond, 168 bool AllowModify) const { 169 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 170 if (I == MBB.end()) 171 return false; 172 173 if (!isUnpredicatedTerminator(*I)) 174 return false; 175 176 // Get the last instruction in the block. 177 MachineInstr *LastInst = I; 178 unsigned LastOpc = LastInst->getOpcode(); 179 180 // If there is only one terminator instruction, process it. 181 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 182 if (isUncondBranchOpcode(LastOpc)) { 183 TBB = LastInst->getOperand(0).getMBB(); 184 return false; 185 } 186 if (isCondBranchOpcode(LastOpc)) { 187 // Block ends with fall-through condbranch. 188 parseCondBranch(LastInst, TBB, Cond); 189 return false; 190 } 191 return true; // Can't handle indirect branch. 192 } 193 194 // Get the instruction before it if it is a terminator. 195 MachineInstr *SecondLastInst = I; 196 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 197 198 // If AllowModify is true and the block ends with two or more unconditional 199 // branches, delete all but the first unconditional branch. 200 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 201 while (isUncondBranchOpcode(SecondLastOpc)) { 202 LastInst->eraseFromParent(); 203 LastInst = SecondLastInst; 204 LastOpc = LastInst->getOpcode(); 205 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 206 // Return now the only terminator is an unconditional branch. 207 TBB = LastInst->getOperand(0).getMBB(); 208 return false; 209 } else { 210 SecondLastInst = I; 211 SecondLastOpc = SecondLastInst->getOpcode(); 212 } 213 } 214 } 215 216 // If there are three terminators, we don't know what sort of block this is. 217 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) 218 return true; 219 220 // If the block ends with a B and a Bcc, handle it. 221 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 222 parseCondBranch(SecondLastInst, TBB, Cond); 223 FBB = LastInst->getOperand(0).getMBB(); 224 return false; 225 } 226 227 // If the block ends with two unconditional branches, handle it. The second 228 // one is not executed. 229 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 230 TBB = SecondLastInst->getOperand(0).getMBB(); 231 return false; 232 } 233 234 // ...likewise if it ends with an indirect branch followed by an unconditional 235 // branch. 236 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 237 I = LastInst; 238 if (AllowModify) 239 I->eraseFromParent(); 240 return true; 241 } 242 243 // Otherwise, can't handle this. 244 return true; 245 } 246 247 unsigned SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB, 248 MachineBasicBlock *TBB, 249 MachineBasicBlock *FBB, 250 ArrayRef<MachineOperand> Cond, 251 const DebugLoc &DL) const { 252 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 253 assert((Cond.size() == 1 || Cond.size() == 0) && 254 "Sparc branch conditions should have one component!"); 255 256 if (Cond.empty()) { 257 assert(!FBB && "Unconditional branch with multiple successors!"); 258 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB); 259 return 1; 260 } 261 262 // Conditional branch 263 unsigned CC = Cond[0].getImm(); 264 265 if (IsIntegerCC(CC)) 266 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC); 267 else 268 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC); 269 if (!FBB) 270 return 1; 271 272 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB); 273 return 2; 274 } 275 276 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const 277 { 278 MachineBasicBlock::iterator I = MBB.end(); 279 unsigned Count = 0; 280 while (I != MBB.begin()) { 281 --I; 282 283 if (I->isDebugValue()) 284 continue; 285 286 if (I->getOpcode() != SP::BA 287 && I->getOpcode() != SP::BCOND 288 && I->getOpcode() != SP::FBCOND) 289 break; // Not a branch 290 291 I->eraseFromParent(); 292 I = MBB.end(); 293 ++Count; 294 } 295 return Count; 296 } 297 298 bool SparcInstrInfo::ReverseBranchCondition( 299 SmallVectorImpl<MachineOperand> &Cond) const { 300 assert(Cond.size() == 1); 301 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm()); 302 Cond[0].setImm(GetOppositeBranchCondition(CC)); 303 return false; 304 } 305 306 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 307 MachineBasicBlock::iterator I, 308 const DebugLoc &DL, unsigned DestReg, 309 unsigned SrcReg, bool KillSrc) const { 310 unsigned numSubRegs = 0; 311 unsigned movOpc = 0; 312 const unsigned *subRegIdx = nullptr; 313 bool ExtraG0 = false; 314 315 const unsigned DW_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; 316 const unsigned DFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd }; 317 const unsigned QFP_DFP_SubRegsIdx[] = { SP::sub_even64, SP::sub_odd64 }; 318 const unsigned QFP_FP_SubRegsIdx[] = { SP::sub_even, SP::sub_odd, 319 SP::sub_odd64_then_sub_even, 320 SP::sub_odd64_then_sub_odd }; 321 322 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 323 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) 324 .addReg(SrcReg, getKillRegState(KillSrc)); 325 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { 326 subRegIdx = DW_SubRegsIdx; 327 numSubRegs = 2; 328 movOpc = SP::ORrr; 329 ExtraG0 = true; 330 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 331 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) 332 .addReg(SrcReg, getKillRegState(KillSrc)); 333 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { 334 if (Subtarget.isV9()) { 335 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) 336 .addReg(SrcReg, getKillRegState(KillSrc)); 337 } else { 338 // Use two FMOVS instructions. 339 subRegIdx = DFP_FP_SubRegsIdx; 340 numSubRegs = 2; 341 movOpc = SP::FMOVS; 342 } 343 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { 344 if (Subtarget.isV9()) { 345 if (Subtarget.hasHardQuad()) { 346 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) 347 .addReg(SrcReg, getKillRegState(KillSrc)); 348 } else { 349 // Use two FMOVD instructions. 350 subRegIdx = QFP_DFP_SubRegsIdx; 351 numSubRegs = 2; 352 movOpc = SP::FMOVD; 353 } 354 } else { 355 // Use four FMOVS instructions. 356 subRegIdx = QFP_FP_SubRegsIdx; 357 numSubRegs = 4; 358 movOpc = SP::FMOVS; 359 } 360 } else if (SP::ASRRegsRegClass.contains(DestReg) && 361 SP::IntRegsRegClass.contains(SrcReg)) { 362 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) 363 .addReg(SP::G0) 364 .addReg(SrcReg, getKillRegState(KillSrc)); 365 } else if (SP::IntRegsRegClass.contains(DestReg) && 366 SP::ASRRegsRegClass.contains(SrcReg)) { 367 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) 368 .addReg(SrcReg, getKillRegState(KillSrc)); 369 } else 370 llvm_unreachable("Impossible reg-to-reg copy"); 371 372 if (numSubRegs == 0 || subRegIdx == nullptr || movOpc == 0) 373 return; 374 375 const TargetRegisterInfo *TRI = &getRegisterInfo(); 376 MachineInstr *MovMI = nullptr; 377 378 for (unsigned i = 0; i != numSubRegs; ++i) { 379 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); 380 unsigned Src = TRI->getSubReg(SrcReg, subRegIdx[i]); 381 assert(Dst && Src && "Bad sub-register"); 382 383 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst); 384 if (ExtraG0) 385 MIB.addReg(SP::G0); 386 MIB.addReg(Src); 387 MovMI = MIB.getInstr(); 388 } 389 // Add implicit super-register defs and kills to the last MovMI. 390 MovMI->addRegisterDefined(DestReg, TRI); 391 if (KillSrc) 392 MovMI->addRegisterKilled(SrcReg, TRI); 393 } 394 395 void SparcInstrInfo:: 396 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 397 unsigned SrcReg, bool isKill, int FI, 398 const TargetRegisterClass *RC, 399 const TargetRegisterInfo *TRI) const { 400 DebugLoc DL; 401 if (I != MBB.end()) DL = I->getDebugLoc(); 402 403 MachineFunction *MF = MBB.getParent(); 404 const MachineFrameInfo &MFI = *MF->getFrameInfo(); 405 MachineMemOperand *MMO = MF->getMachineMemOperand( 406 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, 407 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); 408 409 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 410 if (RC == &SP::I64RegsRegClass) 411 BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0) 412 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 413 else if (RC == &SP::IntRegsRegClass) 414 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 415 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 416 else if (RC == &SP::IntPairRegClass) 417 BuildMI(MBB, I, DL, get(SP::STDri)).addFrameIndex(FI).addImm(0) 418 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 419 else if (RC == &SP::FPRegsRegClass) 420 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 421 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 422 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 423 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 424 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 425 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 426 // Use STQFri irrespective of its legality. If STQ is not legal, it will be 427 // lowered into two STDs in eliminateFrameIndex. 428 BuildMI(MBB, I, DL, get(SP::STQFri)).addFrameIndex(FI).addImm(0) 429 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 430 else 431 llvm_unreachable("Can't store this register to stack slot"); 432 } 433 434 void SparcInstrInfo:: 435 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 436 unsigned DestReg, int FI, 437 const TargetRegisterClass *RC, 438 const TargetRegisterInfo *TRI) const { 439 DebugLoc DL; 440 if (I != MBB.end()) DL = I->getDebugLoc(); 441 442 MachineFunction *MF = MBB.getParent(); 443 const MachineFrameInfo &MFI = *MF->getFrameInfo(); 444 MachineMemOperand *MMO = MF->getMachineMemOperand( 445 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, 446 MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); 447 448 if (RC == &SP::I64RegsRegClass) 449 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0) 450 .addMemOperand(MMO); 451 else if (RC == &SP::IntRegsRegClass) 452 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0) 453 .addMemOperand(MMO); 454 else if (RC == &SP::IntPairRegClass) 455 BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0) 456 .addMemOperand(MMO); 457 else if (RC == &SP::FPRegsRegClass) 458 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0) 459 .addMemOperand(MMO); 460 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 461 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0) 462 .addMemOperand(MMO); 463 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 464 // Use LDQFri irrespective of its legality. If LDQ is not legal, it will be 465 // lowered into two LDDs in eliminateFrameIndex. 466 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0) 467 .addMemOperand(MMO); 468 else 469 llvm_unreachable("Can't load this register from stack slot"); 470 } 471 472 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const 473 { 474 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); 475 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); 476 if (GlobalBaseReg != 0) 477 return GlobalBaseReg; 478 479 // Insert the set of GlobalBaseReg into the first MBB of the function 480 MachineBasicBlock &FirstMBB = MF->front(); 481 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 482 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 483 484 const TargetRegisterClass *PtrRC = 485 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 486 GlobalBaseReg = RegInfo.createVirtualRegister(PtrRC); 487 488 DebugLoc dl; 489 490 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 491 SparcFI->setGlobalBaseReg(GlobalBaseReg); 492 return GlobalBaseReg; 493 } 494 495 bool SparcInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 496 switch (MI->getOpcode()) { 497 case TargetOpcode::LOAD_STACK_GUARD: { 498 assert(Subtarget.isTargetLinux() && 499 "Only Linux target is expected to contain LOAD_STACK_GUARD"); 500 // offsetof(tcbhead_t, stack_guard) from sysdeps/sparc/nptl/tls.h in glibc. 501 const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14; 502 MI->setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri)); 503 MachineInstrBuilder(*MI->getParent()->getParent(), MI) 504 .addReg(SP::G7).addImm(Offset); 505 return true; 506 } 507 } 508 return false; 509 } 510