1 //===-- SparcInstrInfo.cpp - Sparc Instruction Information ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcInstrInfo.h"
15 #include "Sparc.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 #define GET_INSTRINFO_CTOR
26 #include "SparcGenInstrInfo.inc"
27 
28 using namespace llvm;
29 
30 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
31   : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
32     RI(ST), Subtarget(ST) {
33 }
34 
35 /// isLoadFromStackSlot - If the specified machine instruction is a direct
36 /// load from a stack slot, return the virtual or physical register number of
37 /// the destination along with the FrameIndex of the loaded stack slot.  If
38 /// not, return 0.  This predicate must return 0 if the instruction has
39 /// any side effects other than loading from the stack slot.
40 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
41                                              int &FrameIndex) const {
42   if (MI->getOpcode() == SP::LDri ||
43       MI->getOpcode() == SP::LDXri ||
44       MI->getOpcode() == SP::LDFri ||
45       MI->getOpcode() == SP::LDDFri) {
46     if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
47         MI->getOperand(2).getImm() == 0) {
48       FrameIndex = MI->getOperand(1).getIndex();
49       return MI->getOperand(0).getReg();
50     }
51   }
52   return 0;
53 }
54 
55 /// isStoreToStackSlot - If the specified machine instruction is a direct
56 /// store to a stack slot, return the virtual or physical register number of
57 /// the source reg along with the FrameIndex of the loaded stack slot.  If
58 /// not, return 0.  This predicate must return 0 if the instruction has
59 /// any side effects other than storing to the stack slot.
60 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
61                                             int &FrameIndex) const {
62   if (MI->getOpcode() == SP::STri ||
63       MI->getOpcode() == SP::STXri ||
64       MI->getOpcode() == SP::STFri ||
65       MI->getOpcode() == SP::STDFri) {
66     if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
67         MI->getOperand(1).getImm() == 0) {
68       FrameIndex = MI->getOperand(0).getIndex();
69       return MI->getOperand(2).getReg();
70     }
71   }
72   return 0;
73 }
74 
75 static bool IsIntegerCC(unsigned CC)
76 {
77   return  (CC <= SPCC::ICC_VC);
78 }
79 
80 
81 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
82 {
83   switch(CC) {
84   case SPCC::ICC_NE:   return SPCC::ICC_E;
85   case SPCC::ICC_E:    return SPCC::ICC_NE;
86   case SPCC::ICC_G:    return SPCC::ICC_LE;
87   case SPCC::ICC_LE:   return SPCC::ICC_G;
88   case SPCC::ICC_GE:   return SPCC::ICC_L;
89   case SPCC::ICC_L:    return SPCC::ICC_GE;
90   case SPCC::ICC_GU:   return SPCC::ICC_LEU;
91   case SPCC::ICC_LEU:  return SPCC::ICC_GU;
92   case SPCC::ICC_CC:   return SPCC::ICC_CS;
93   case SPCC::ICC_CS:   return SPCC::ICC_CC;
94   case SPCC::ICC_POS:  return SPCC::ICC_NEG;
95   case SPCC::ICC_NEG:  return SPCC::ICC_POS;
96   case SPCC::ICC_VC:   return SPCC::ICC_VS;
97   case SPCC::ICC_VS:   return SPCC::ICC_VC;
98 
99   case SPCC::FCC_U:    return SPCC::FCC_O;
100   case SPCC::FCC_O:    return SPCC::FCC_U;
101   case SPCC::FCC_G:    return SPCC::FCC_LE;
102   case SPCC::FCC_LE:   return SPCC::FCC_G;
103   case SPCC::FCC_UG:   return SPCC::FCC_ULE;
104   case SPCC::FCC_ULE:  return SPCC::FCC_UG;
105   case SPCC::FCC_L:    return SPCC::FCC_GE;
106   case SPCC::FCC_GE:   return SPCC::FCC_L;
107   case SPCC::FCC_UL:   return SPCC::FCC_UGE;
108   case SPCC::FCC_UGE:  return SPCC::FCC_UL;
109   case SPCC::FCC_LG:   return SPCC::FCC_UE;
110   case SPCC::FCC_UE:   return SPCC::FCC_LG;
111   case SPCC::FCC_NE:   return SPCC::FCC_E;
112   case SPCC::FCC_E:    return SPCC::FCC_NE;
113   }
114   llvm_unreachable("Invalid cond code");
115 }
116 
117 MachineInstr *
118 SparcInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
119                                          int FrameIx,
120                                          uint64_t Offset,
121                                          const MDNode *MDPtr,
122                                          DebugLoc dl) const {
123   MachineInstrBuilder MIB = BuildMI(MF, dl, get(SP::DBG_VALUE))
124     .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
125   return &*MIB;
126 }
127 
128 
129 bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
130                                    MachineBasicBlock *&TBB,
131                                    MachineBasicBlock *&FBB,
132                                    SmallVectorImpl<MachineOperand> &Cond,
133                                    bool AllowModify) const
134 {
135 
136   MachineBasicBlock::iterator I = MBB.end();
137   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
138   while (I != MBB.begin()) {
139     --I;
140 
141     if (I->isDebugValue())
142       continue;
143 
144     // When we see a non-terminator, we are done.
145     if (!isUnpredicatedTerminator(I))
146       break;
147 
148     // Terminator is not a branch.
149     if (!I->isBranch())
150       return true;
151 
152     // Handle Unconditional branches.
153     if (I->getOpcode() == SP::BA) {
154       UnCondBrIter = I;
155 
156       if (!AllowModify) {
157         TBB = I->getOperand(0).getMBB();
158         continue;
159       }
160 
161       while (llvm::next(I) != MBB.end())
162         llvm::next(I)->eraseFromParent();
163 
164       Cond.clear();
165       FBB = 0;
166 
167       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
168         TBB = 0;
169         I->eraseFromParent();
170         I = MBB.end();
171         UnCondBrIter = MBB.end();
172         continue;
173       }
174 
175       TBB = I->getOperand(0).getMBB();
176       continue;
177     }
178 
179     unsigned Opcode = I->getOpcode();
180     if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
181       return true; // Unknown Opcode.
182 
183     SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
184 
185     if (Cond.empty()) {
186       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
187       if (AllowModify && UnCondBrIter != MBB.end() &&
188           MBB.isLayoutSuccessor(TargetBB)) {
189 
190         // Transform the code
191         //
192         //    brCC L1
193         //    ba L2
194         // L1:
195         //    ..
196         // L2:
197         //
198         // into
199         //
200         //   brnCC L2
201         // L1:
202         //   ...
203         // L2:
204         //
205         BranchCode = GetOppositeBranchCondition(BranchCode);
206         MachineBasicBlock::iterator OldInst = I;
207         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
208           .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
209         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(SP::BA))
210           .addMBB(TargetBB);
211 
212         OldInst->eraseFromParent();
213         UnCondBrIter->eraseFromParent();
214 
215         UnCondBrIter = MBB.end();
216         I = MBB.end();
217         continue;
218       }
219       FBB = TBB;
220       TBB = I->getOperand(0).getMBB();
221       Cond.push_back(MachineOperand::CreateImm(BranchCode));
222       continue;
223     }
224     // FIXME: Handle subsequent conditional branches.
225     // For now, we can't handle multiple conditional branches.
226     return true;
227   }
228   return false;
229 }
230 
231 unsigned
232 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
233                              MachineBasicBlock *FBB,
234                              const SmallVectorImpl<MachineOperand> &Cond,
235                              DebugLoc DL) const {
236   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
237   assert((Cond.size() == 1 || Cond.size() == 0) &&
238          "Sparc branch conditions should have one component!");
239 
240   if (Cond.empty()) {
241     assert(!FBB && "Unconditional branch with multiple successors!");
242     BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
243     return 1;
244   }
245 
246   // Conditional branch
247   unsigned CC = Cond[0].getImm();
248 
249   if (IsIntegerCC(CC))
250     BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
251   else
252     BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
253   if (!FBB)
254     return 1;
255 
256   BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
257   return 2;
258 }
259 
260 unsigned SparcInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
261 {
262   MachineBasicBlock::iterator I = MBB.end();
263   unsigned Count = 0;
264   while (I != MBB.begin()) {
265     --I;
266 
267     if (I->isDebugValue())
268       continue;
269 
270     if (I->getOpcode() != SP::BA
271         && I->getOpcode() != SP::BCOND
272         && I->getOpcode() != SP::FBCOND)
273       break; // Not a branch
274 
275     I->eraseFromParent();
276     I = MBB.end();
277     ++Count;
278   }
279   return Count;
280 }
281 
282 void SparcInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
283                                  MachineBasicBlock::iterator I, DebugLoc DL,
284                                  unsigned DestReg, unsigned SrcReg,
285                                  bool KillSrc) const {
286   if (SP::IntRegsRegClass.contains(DestReg, SrcReg))
287     BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
288       .addReg(SrcReg, getKillRegState(KillSrc));
289   else if (SP::FPRegsRegClass.contains(DestReg, SrcReg))
290     BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
291       .addReg(SrcReg, getKillRegState(KillSrc));
292   else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) {
293     if (Subtarget.isV9()) {
294       BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
295         .addReg(SrcReg, getKillRegState(KillSrc));
296     } else {
297       // Use two FMOVS instructions.
298       const TargetRegisterInfo *TRI = &getRegisterInfo();
299       MachineInstr *MovMI = 0;
300       unsigned subRegIdx[] = {SP::sub_even, SP::sub_odd};
301       for (unsigned i = 0; i != 2; ++i) {
302         unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
303         unsigned Src = TRI->getSubReg(SrcReg,  subRegIdx[i]);
304         assert(Dst && Src && "Bad sub-register");
305 
306         MovMI = BuildMI(MBB, I, DL, get(SP::FMOVS), Dst).addReg(Src);
307       }
308       // Add implicit super-register defs and kills to the last MovMI.
309       MovMI->addRegisterDefined(DestReg, TRI);
310       if (KillSrc)
311         MovMI->addRegisterKilled(SrcReg, TRI);
312     }
313   } else
314     llvm_unreachable("Impossible reg-to-reg copy");
315 }
316 
317 void SparcInstrInfo::
318 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
319                     unsigned SrcReg, bool isKill, int FI,
320                     const TargetRegisterClass *RC,
321                     const TargetRegisterInfo *TRI) const {
322   DebugLoc DL;
323   if (I != MBB.end()) DL = I->getDebugLoc();
324 
325   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
326   if (RC == &SP::I64RegsRegClass)
327     BuildMI(MBB, I, DL, get(SP::STXri)).addFrameIndex(FI).addImm(0)
328       .addReg(SrcReg, getKillRegState(isKill));
329   else if (RC == &SP::IntRegsRegClass)
330     BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
331       .addReg(SrcReg, getKillRegState(isKill));
332   else if (RC == &SP::FPRegsRegClass)
333     BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
334       .addReg(SrcReg,  getKillRegState(isKill));
335   else if (RC == &SP::DFPRegsRegClass)
336     BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
337       .addReg(SrcReg,  getKillRegState(isKill));
338   else
339     llvm_unreachable("Can't store this register to stack slot");
340 }
341 
342 void SparcInstrInfo::
343 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
344                      unsigned DestReg, int FI,
345                      const TargetRegisterClass *RC,
346                      const TargetRegisterInfo *TRI) const {
347   DebugLoc DL;
348   if (I != MBB.end()) DL = I->getDebugLoc();
349 
350   if (RC == &SP::I64RegsRegClass)
351     BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0);
352   else if (RC == &SP::IntRegsRegClass)
353     BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
354   else if (RC == &SP::FPRegsRegClass)
355     BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
356   else if (RC == &SP::DFPRegsRegClass)
357     BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
358   else
359     llvm_unreachable("Can't load this register from stack slot");
360 }
361 
362 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
363 {
364   SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
365   unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
366   if (GlobalBaseReg != 0)
367     return GlobalBaseReg;
368 
369   // Insert the set of GlobalBaseReg into the first MBB of the function
370   MachineBasicBlock &FirstMBB = MF->front();
371   MachineBasicBlock::iterator MBBI = FirstMBB.begin();
372   MachineRegisterInfo &RegInfo = MF->getRegInfo();
373 
374   GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
375 
376 
377   DebugLoc dl;
378 
379   BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
380   SparcFI->setGlobalBaseReg(GlobalBaseReg);
381   return GlobalBaseReg;
382 }
383