1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Sparc implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcFrameLowering.h"
15 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Target/TargetOptions.h"
26 
27 using namespace llvm;
28 
29 static cl::opt<bool>
30 DisableLeafProc("disable-sparc-leaf-proc",
31                 cl::init(false),
32                 cl::desc("Disable Sparc leaf procedure optimization."),
33                 cl::Hidden);
34 
35 
36 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
37                                           MachineBasicBlock &MBB,
38                                           MachineBasicBlock::iterator MBBI,
39                                           int NumBytes,
40                                           unsigned ADDrr,
41                                           unsigned ADDri) const {
42 
43   DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc();
44   const SparcInstrInfo &TII =
45     *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
46 
47   if (NumBytes >= -4096 && NumBytes < 4096) {
48     BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
49       .addReg(SP::O6).addImm(NumBytes);
50     return;
51   }
52 
53   // Emit this the hard way.  This clobbers G1 which we always know is
54   // available here.
55   if (NumBytes >= 0) {
56     // Emit nonnegative numbers with sethi + or.
57     // sethi %hi(NumBytes), %g1
58     // or %g1, %lo(NumBytes), %g1
59     // add %sp, %g1, %sp
60     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
61       .addImm(HI22(NumBytes));
62     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
63       .addReg(SP::G1).addImm(LO10(NumBytes));
64     BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
65       .addReg(SP::O6).addReg(SP::G1);
66     return ;
67   }
68 
69   // Emit negative numbers with sethi + xor.
70   // sethi %hix(NumBytes), %g1
71   // xor %g1, %lox(NumBytes), %g1
72   // add %sp, %g1, %sp
73   BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
74     .addImm(HIX22(NumBytes));
75   BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
76     .addReg(SP::G1).addImm(LOX10(NumBytes));
77   BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
78     .addReg(SP::O6).addReg(SP::G1);
79 }
80 
81 void SparcFrameLowering::emitPrologue(MachineFunction &MF) const {
82   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
83 
84   MachineBasicBlock &MBB = MF.front();
85   MachineFrameInfo *MFI = MF.getFrameInfo();
86   const SparcInstrInfo &TII =
87     *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
88   MachineBasicBlock::iterator MBBI = MBB.begin();
89   DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
90 
91   // Get the number of bytes to allocate from the FrameInfo
92   int NumBytes = (int) MFI->getStackSize();
93 
94   unsigned SAVEri = SP::SAVEri;
95   unsigned SAVErr = SP::SAVErr;
96   if (FuncInfo->isLeafProc()) {
97     if (NumBytes == 0)
98       return;
99     SAVEri = SP::ADDri;
100     SAVErr = SP::ADDrr;
101   }
102   NumBytes = - SubTarget.getAdjustedFrameSize(NumBytes);
103   emitSPAdjustment(MF, MBB, MBBI, NumBytes, SAVErr, SAVEri);
104 
105   MachineModuleInfo &MMI = MF.getMMI();
106   const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
107   unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
108 
109   // Emit ".cfi_def_cfa_register 30".
110   unsigned CFIIndex =
111       MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
112   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
113       .addCFIIndex(CFIIndex);
114 
115   // Emit ".cfi_window_save".
116   CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
117   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
118       .addCFIIndex(CFIIndex);
119 
120   unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
121   unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
122   // Emit ".cfi_register 15, 31".
123   CFIIndex = MMI.addFrameInst(
124       MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
125   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
126       .addCFIIndex(CFIIndex);
127 }
128 
129 void SparcFrameLowering::
130 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
131                               MachineBasicBlock::iterator I) const {
132   if (!hasReservedCallFrame(MF)) {
133     MachineInstr &MI = *I;
134     int Size = MI.getOperand(0).getImm();
135     if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
136       Size = -Size;
137 
138     if (Size)
139       emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
140   }
141   MBB.erase(I);
142 }
143 
144 
145 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
146                                   MachineBasicBlock &MBB) const {
147   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
148   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
149   const SparcInstrInfo &TII =
150     *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo());
151   DebugLoc dl = MBBI->getDebugLoc();
152   assert(MBBI->getOpcode() == SP::RETL &&
153          "Can only put epilog before 'retl' instruction!");
154   if (!FuncInfo->isLeafProc()) {
155     BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
156       .addReg(SP::G0);
157     return;
158   }
159   MachineFrameInfo *MFI = MF.getFrameInfo();
160 
161   int NumBytes = (int) MFI->getStackSize();
162   if (NumBytes == 0)
163     return;
164 
165   NumBytes = SubTarget.getAdjustedFrameSize(NumBytes);
166   emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
167 }
168 
169 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
170   // Reserve call frame if there are no variable sized objects on the stack.
171   return !MF.getFrameInfo()->hasVarSizedObjects();
172 }
173 
174 // hasFP - Return true if the specified function should have a dedicated frame
175 // pointer register.  This is true if the function has variable sized allocas or
176 // if frame pointer elimination is disabled.
177 bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
178   const MachineFrameInfo *MFI = MF.getFrameInfo();
179   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
180     MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
181 }
182 
183 
184 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
185 {
186 
187   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
188     if (MRI->isPhysRegUsed(reg))
189       return false;
190 
191   for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
192     if (MRI->isPhysRegUsed(reg))
193       return false;
194 
195   return true;
196 }
197 
198 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
199 {
200 
201   MachineRegisterInfo &MRI = MF.getRegInfo();
202   MachineFrameInfo    *MFI = MF.getFrameInfo();
203 
204   return !(MFI->hasCalls()              // has calls
205            || MRI.isPhysRegUsed(SP::L0) // Too many registers needed
206            || MRI.isPhysRegUsed(SP::O6) // %SP is used
207            || hasFP(MF));               // need %FP
208 }
209 
210 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
211 
212   MachineRegisterInfo &MRI = MF.getRegInfo();
213 
214   // Remap %i[0-7] to %o[0-7].
215   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
216     if (!MRI.isPhysRegUsed(reg))
217       continue;
218     unsigned mapped_reg = (reg - SP::I0 + SP::O0);
219     assert(!MRI.isPhysRegUsed(mapped_reg));
220 
221     // Replace I register with O register.
222     MRI.replaceRegWith(reg, mapped_reg);
223 
224     // Mark the reg unused.
225     MRI.setPhysRegUnused(reg);
226   }
227 
228   // Rewrite MBB's Live-ins.
229   for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
230        MBB != E; ++MBB) {
231     for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
232       if (!MBB->isLiveIn(reg))
233         continue;
234       MBB->removeLiveIn(reg);
235       MBB->addLiveIn(reg - SP::I0 + SP::O0);
236     }
237   }
238 
239   assert(verifyLeafProcRegUse(&MRI));
240 #ifdef XDEBUG
241   MF.verify(0, "After LeafProc Remapping");
242 #endif
243 }
244 
245 void SparcFrameLowering::processFunctionBeforeCalleeSavedScan
246                   (MachineFunction &MF, RegScavenger *RS) const {
247 
248   if (!DisableLeafProc && isLeafProc(MF)) {
249     SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
250     MFI->setLeafProc(true);
251 
252     remapRegsForLeafProc(MF);
253   }
254 
255 }
256