1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Sparc implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "SparcFrameLowering.h" 15 #include "SparcInstrInfo.h" 16 #include "SparcMachineFunctionInfo.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineModuleInfo.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/IR/DataLayout.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Target/TargetOptions.h" 26 27 using namespace llvm; 28 29 void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { 30 MachineBasicBlock &MBB = MF.front(); 31 MachineFrameInfo *MFI = MF.getFrameInfo(); 32 const SparcInstrInfo &TII = 33 *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo()); 34 MachineBasicBlock::iterator MBBI = MBB.begin(); 35 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 36 37 // Get the number of bytes to allocate from the FrameInfo 38 int NumBytes = (int) MFI->getStackSize(); 39 40 if (SubTarget.is64Bit()) { 41 // All 64-bit stack frames must be 16-byte aligned, and must reserve space 42 // for spilling the 16 window registers at %sp+BIAS..%sp+BIAS+128. 43 NumBytes += 128; 44 // Frames with calls must also reserve space for 6 outgoing arguments 45 // whether they are used or not. LowerCall_64 takes care of that. 46 assert(NumBytes % 16 == 0 && "Stack size not 16-byte aligned"); 47 } else { 48 // Emit the correct save instruction based on the number of bytes in 49 // the frame. Minimum stack frame size according to V8 ABI is: 50 // 16 words for register window spill 51 // 1 word for address of returned aggregate-value 52 // + 6 words for passing parameters on the stack 53 // ---------- 54 // 23 words * 4 bytes per word = 92 bytes 55 NumBytes += 92; 56 57 // Round up to next doubleword boundary -- a double-word boundary 58 // is required by the ABI. 59 NumBytes = RoundUpToAlignment(NumBytes, 8); 60 } 61 NumBytes = -NumBytes; 62 63 if (NumBytes >= -4096) { 64 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) 65 .addReg(SP::O6).addImm(NumBytes); 66 } else { 67 // Emit this the hard way. This clobbers G1 which we always know is 68 // available here. 69 unsigned OffHi = (unsigned)NumBytes >> 10U; 70 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); 71 // Emit G1 = G1 + I6 72 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) 73 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); 74 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) 75 .addReg(SP::O6).addReg(SP::G1); 76 } 77 } 78 79 void SparcFrameLowering:: 80 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator I) const { 82 if (!hasReservedCallFrame(MF)) { 83 MachineInstr &MI = *I; 84 DebugLoc DL = MI.getDebugLoc(); 85 int Size = MI.getOperand(0).getImm(); 86 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN) 87 Size = -Size; 88 const SparcInstrInfo &TII = 89 *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo()); 90 if (Size) 91 BuildMI(MBB, I, DL, TII.get(SP::ADDri), SP::O6).addReg(SP::O6) 92 .addImm(Size); 93 } 94 MBB.erase(I); 95 } 96 97 98 void SparcFrameLowering::emitEpilogue(MachineFunction &MF, 99 MachineBasicBlock &MBB) const { 100 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 101 const SparcInstrInfo &TII = 102 *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo()); 103 DebugLoc dl = MBBI->getDebugLoc(); 104 assert(MBBI->getOpcode() == SP::RETL && 105 "Can only put epilog before 'retl' instruction!"); 106 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) 107 .addReg(SP::G0); 108 } 109