1 //===-- SparcFrameLowering.cpp - Sparc Frame Information ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Sparc implementation of TargetFrameLowering class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcFrameLowering.h"
15 #include "SparcInstrInfo.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcSubtarget.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Target/TargetOptions.h"
27 
28 using namespace llvm;
29 
30 static cl::opt<bool>
31 DisableLeafProc("disable-sparc-leaf-proc",
32                 cl::init(false),
33                 cl::desc("Disable Sparc leaf procedure optimization."),
34                 cl::Hidden);
35 
36 SparcFrameLowering::SparcFrameLowering(const SparcSubtarget &ST)
37     : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
38                           ST.is64Bit() ? 16 : 8, 0, ST.is64Bit() ? 16 : 8) {}
39 
40 void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF,
41                                           MachineBasicBlock &MBB,
42                                           MachineBasicBlock::iterator MBBI,
43                                           int NumBytes,
44                                           unsigned ADDrr,
45                                           unsigned ADDri) const {
46 
47   DebugLoc dl;
48   const SparcInstrInfo &TII =
49       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
50 
51   if (NumBytes >= -4096 && NumBytes < 4096) {
52     BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53       .addReg(SP::O6).addImm(NumBytes);
54     return;
55   }
56 
57   // Emit this the hard way.  This clobbers G1 which we always know is
58   // available here.
59   if (NumBytes >= 0) {
60     // Emit nonnegative numbers with sethi + or.
61     // sethi %hi(NumBytes), %g1
62     // or %g1, %lo(NumBytes), %g1
63     // add %sp, %g1, %sp
64     BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
65       .addImm(HI22(NumBytes));
66     BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
67       .addReg(SP::G1).addImm(LO10(NumBytes));
68     BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69       .addReg(SP::O6).addReg(SP::G1);
70     return ;
71   }
72 
73   // Emit negative numbers with sethi + xor.
74   // sethi %hix(NumBytes), %g1
75   // xor %g1, %lox(NumBytes), %g1
76   // add %sp, %g1, %sp
77   BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
78     .addImm(HIX22(NumBytes));
79   BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
80     .addReg(SP::G1).addImm(LOX10(NumBytes));
81   BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82     .addReg(SP::O6).addReg(SP::G1);
83 }
84 
85 void SparcFrameLowering::emitPrologue(MachineFunction &MF,
86                                       MachineBasicBlock &MBB) const {
87   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
88 
89   assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
90   MachineFrameInfo &MFI = MF.getFrameInfo();
91   const SparcInstrInfo &TII =
92       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
93   const SparcRegisterInfo &RegInfo =
94       *static_cast<const SparcRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
95   MachineBasicBlock::iterator MBBI = MBB.begin();
96   // Debug location must be unknown since the first debug location is used
97   // to determine the end of the prologue.
98   DebugLoc dl;
99   bool NeedsStackRealignment = RegInfo.needsStackRealignment(MF);
100 
101   // FIXME: unfortunately, returning false from canRealignStack
102   // actually just causes needsStackRealignment to return false,
103   // rather than reporting an error, as would be sensible. This is
104   // poor, but fixing that bogosity is going to be a large project.
105   // For now, just see if it's lied, and report an error here.
106   if (!NeedsStackRealignment && MFI.getMaxAlignment() > getStackAlignment())
107     report_fatal_error("Function \"" + Twine(MF.getName()) + "\" required "
108                        "stack re-alignment, but LLVM couldn't handle it "
109                        "(probably because it has a dynamic alloca).");
110 
111   // Get the number of bytes to allocate from the FrameInfo
112   int NumBytes = (int) MFI.getStackSize();
113 
114   unsigned SAVEri = SP::SAVEri;
115   unsigned SAVErr = SP::SAVErr;
116   if (FuncInfo->isLeafProc()) {
117     if (NumBytes == 0)
118       return;
119     SAVEri = SP::ADDri;
120     SAVErr = SP::ADDrr;
121   }
122 
123   // The SPARC ABI is a bit odd in that it requires a reserved 92-byte
124   // (128 in v9) area in the user's stack, starting at %sp. Thus, the
125   // first part of the stack that can actually be used is located at
126   // %sp + 92.
127   //
128   // We therefore need to add that offset to the total stack size
129   // after all the stack objects are placed by
130   // PrologEpilogInserter calculateFrameObjectOffsets. However, since the stack needs to be
131   // aligned *after* the extra size is added, we need to disable
132   // calculateFrameObjectOffsets's built-in stack alignment, by having
133   // targetHandlesStackFrameRounding return true.
134 
135 
136   // Add the extra call frame stack size, if needed. (This is the same
137   // code as in PrologEpilogInserter, but also gets disabled by
138   // targetHandlesStackFrameRounding)
139   if (MFI.adjustsStack() && hasReservedCallFrame(MF))
140     NumBytes += MFI.getMaxCallFrameSize();
141 
142   // Adds the SPARC subtarget-specific spill area to the stack
143   // size. Also ensures target-required alignment.
144   NumBytes = MF.getSubtarget<SparcSubtarget>().getAdjustedFrameSize(NumBytes);
145 
146   // Finally, ensure that the size is sufficiently aligned for the
147   // data on the stack.
148   if (MFI.getMaxAlignment() > 0) {
149     NumBytes = alignTo(NumBytes, MFI.getMaxAlignment());
150   }
151 
152   // Update stack size with corrected value.
153   MFI.setStackSize(NumBytes);
154 
155   emitSPAdjustment(MF, MBB, MBBI, -NumBytes, SAVErr, SAVEri);
156 
157   unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true);
158 
159   // Emit ".cfi_def_cfa_register 30".
160   unsigned CFIIndex =
161       MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
162   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
163       .addCFIIndex(CFIIndex);
164 
165   // Emit ".cfi_window_save".
166   CFIIndex = MF.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
167   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
168       .addCFIIndex(CFIIndex);
169 
170   unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true);
171   unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true);
172   // Emit ".cfi_register 15, 31".
173   CFIIndex = MF.addFrameInst(
174       MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
175   BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
176       .addCFIIndex(CFIIndex);
177 
178   if (NeedsStackRealignment) {
179     // andn %o6, MaxAlign-1, %o6
180     int MaxAlign = MFI.getMaxAlignment();
181     BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1);
182   }
183 }
184 
185 MachineBasicBlock::iterator SparcFrameLowering::
186 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
187                               MachineBasicBlock::iterator I) const {
188   if (!hasReservedCallFrame(MF)) {
189     MachineInstr &MI = *I;
190     int Size = MI.getOperand(0).getImm();
191     if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
192       Size = -Size;
193 
194     if (Size)
195       emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri);
196   }
197   return MBB.erase(I);
198 }
199 
200 
201 void SparcFrameLowering::emitEpilogue(MachineFunction &MF,
202                                   MachineBasicBlock &MBB) const {
203   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
204   MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
205   const SparcInstrInfo &TII =
206       *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo());
207   DebugLoc dl = MBBI->getDebugLoc();
208   assert(MBBI->getOpcode() == SP::RETL &&
209          "Can only put epilog before 'retl' instruction!");
210   if (!FuncInfo->isLeafProc()) {
211     BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
212       .addReg(SP::G0);
213     return;
214   }
215   MachineFrameInfo &MFI = MF.getFrameInfo();
216 
217   int NumBytes = (int) MFI.getStackSize();
218   if (NumBytes == 0)
219     return;
220 
221   emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri);
222 }
223 
224 bool SparcFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
225   // Reserve call frame if there are no variable sized objects on the stack.
226   return !MF.getFrameInfo().hasVarSizedObjects();
227 }
228 
229 // hasFP - Return true if the specified function should have a dedicated frame
230 // pointer register.  This is true if the function has variable sized allocas or
231 // if frame pointer elimination is disabled.
232 bool SparcFrameLowering::hasFP(const MachineFunction &MF) const {
233   const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
234 
235   const MachineFrameInfo &MFI = MF.getFrameInfo();
236   return MF.getTarget().Options.DisableFramePointerElim(MF) ||
237       RegInfo->needsStackRealignment(MF) ||
238       MFI.hasVarSizedObjects() ||
239       MFI.isFrameAddressTaken();
240 }
241 
242 
243 int SparcFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
244                                                unsigned &FrameReg) const {
245   const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
246   const MachineFrameInfo &MFI = MF.getFrameInfo();
247   const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
248   const SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
249   bool isFixed = MFI.isFixedObjectIndex(FI);
250 
251   // Addressable stack objects are accessed using neg. offsets from
252   // %fp, or positive offsets from %sp.
253   bool UseFP;
254 
255   // Sparc uses FP-based references in general, even when "hasFP" is
256   // false. That function is rather a misnomer, because %fp is
257   // actually always available, unless isLeafProc.
258   if (FuncInfo->isLeafProc()) {
259     // If there's a leaf proc, all offsets need to be %sp-based,
260     // because we haven't caused %fp to actually point to our frame.
261     UseFP = false;
262   } else if (isFixed) {
263     // Otherwise, argument access should always use %fp.
264     UseFP = true;
265   } else if (RegInfo->needsStackRealignment(MF)) {
266     // If there is dynamic stack realignment, all local object
267     // references need to be via %sp, to take account of the
268     // re-alignment.
269     UseFP = false;
270   } else {
271     // Finally, default to using %fp.
272     UseFP = true;
273   }
274 
275   int64_t FrameOffset = MF.getFrameInfo().getObjectOffset(FI) +
276       Subtarget.getStackPointerBias();
277 
278   if (UseFP) {
279     FrameReg = RegInfo->getFrameRegister(MF);
280     return FrameOffset;
281   } else {
282     FrameReg = SP::O6; // %sp
283     return FrameOffset + MF.getFrameInfo().getStackSize();
284   }
285 }
286 
287 static bool LLVM_ATTRIBUTE_UNUSED verifyLeafProcRegUse(MachineRegisterInfo *MRI)
288 {
289 
290   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
291     if (MRI->isPhysRegUsed(reg))
292       return false;
293 
294   for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
295     if (MRI->isPhysRegUsed(reg))
296       return false;
297 
298   return true;
299 }
300 
301 bool SparcFrameLowering::isLeafProc(MachineFunction &MF) const
302 {
303 
304   MachineRegisterInfo &MRI = MF.getRegInfo();
305   MachineFrameInfo    &MFI = MF.getFrameInfo();
306 
307   return !(MFI.hasCalls()                  // has calls
308            || MRI.isPhysRegUsed(SP::L0)    // Too many registers needed
309            || MRI.isPhysRegUsed(SP::O6)    // %SP is used
310            || hasFP(MF));                  // need %FP
311 }
312 
313 void SparcFrameLowering::remapRegsForLeafProc(MachineFunction &MF) const {
314   MachineRegisterInfo &MRI = MF.getRegInfo();
315   // Remap %i[0-7] to %o[0-7].
316   for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
317     if (!MRI.isPhysRegUsed(reg))
318       continue;
319 
320     unsigned mapped_reg = reg - SP::I0 + SP::O0;
321 
322     // Replace I register with O register.
323     MRI.replaceRegWith(reg, mapped_reg);
324 
325     // Also replace register pair super-registers.
326     if ((reg - SP::I0) % 2 == 0) {
327       unsigned preg = (reg - SP::I0) / 2 + SP::I0_I1;
328       unsigned mapped_preg = preg - SP::I0_I1 + SP::O0_O1;
329       MRI.replaceRegWith(preg, mapped_preg);
330     }
331   }
332 
333   // Rewrite MBB's Live-ins.
334   for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
335        MBB != E; ++MBB) {
336     for (unsigned reg = SP::I0_I1; reg <= SP::I6_I7; ++reg) {
337       if (!MBB->isLiveIn(reg))
338         continue;
339       MBB->removeLiveIn(reg);
340       MBB->addLiveIn(reg - SP::I0_I1 + SP::O0_O1);
341     }
342     for (unsigned reg = SP::I0; reg <= SP::I7; ++reg) {
343       if (!MBB->isLiveIn(reg))
344         continue;
345       MBB->removeLiveIn(reg);
346       MBB->addLiveIn(reg - SP::I0 + SP::O0);
347     }
348   }
349 
350   assert(verifyLeafProcRegUse(&MRI));
351 #ifdef EXPENSIVE_CHECKS
352   MF.verify(0, "After LeafProc Remapping");
353 #endif
354 }
355 
356 void SparcFrameLowering::determineCalleeSaves(MachineFunction &MF,
357                                               BitVector &SavedRegs,
358                                               RegScavenger *RS) const {
359   TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
360   if (!DisableLeafProc && isLeafProc(MF)) {
361     SparcMachineFunctionInfo *MFI = MF.getInfo<SparcMachineFunctionInfo>();
362     MFI->setLeafProc(true);
363 
364     remapRegsForLeafProc(MF);
365   }
366 
367 }
368