1 //===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file provides Sparc specific target descriptions.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "SparcMCTargetDesc.h"
15 #include "InstPrinter/SparcInstPrinter.h"
16 #include "SparcMCAsmInfo.h"
17 #include "SparcTargetStreamer.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCRegisterInfo.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 using namespace llvm;
26 
27 #define GET_INSTRINFO_MC_DESC
28 #include "SparcGenInstrInfo.inc"
29 
30 #define GET_SUBTARGETINFO_MC_DESC
31 #include "SparcGenSubtargetInfo.inc"
32 
33 #define GET_REGINFO_MC_DESC
34 #include "SparcGenRegisterInfo.inc"
35 
36 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI,
37                                        const Triple &TT) {
38   MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
39   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
40   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0);
41   MAI->addInitialFrameState(Inst);
42   return MAI;
43 }
44 
45 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI,
46                                          const Triple &TT) {
47   MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT);
48   unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
49   MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047);
50   MAI->addInitialFrameState(Inst);
51   return MAI;
52 }
53 
54 static MCInstrInfo *createSparcMCInstrInfo() {
55   MCInstrInfo *X = new MCInstrInfo();
56   InitSparcMCInstrInfo(X);
57   return X;
58 }
59 
60 static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
61   MCRegisterInfo *X = new MCRegisterInfo();
62   InitSparcMCRegisterInfo(X, SP::O7);
63   return X;
64 }
65 
66 static MCSubtargetInfo *
67 createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
68   MCSubtargetInfo *X = new MCSubtargetInfo();
69   if (CPU.empty())
70     CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
71   InitSparcMCSubtargetInfo(X, TT, CPU, FS);
72   return X;
73 }
74 
75 // Code models. Some only make sense for 64-bit code.
76 //
77 // SunCC  Reloc   CodeModel  Constraints
78 // abs32  Static  Small      text+data+bss linked below 2^32 bytes
79 // abs44  Static  Medium     text+data+bss linked below 2^44 bytes
80 // abs64  Static  Large      text smaller than 2^31 bytes
81 // pic13  PIC_    Small      GOT < 2^13 bytes
82 // pic32  PIC_    Medium     GOT < 2^32 bytes
83 //
84 // All code models require that the text segment is smaller than 2GB.
85 
86 static MCCodeGenInfo *createSparcMCCodeGenInfo(const Triple &TT,
87                                                Reloc::Model RM,
88                                                CodeModel::Model CM,
89                                                CodeGenOpt::Level OL) {
90   MCCodeGenInfo *X = new MCCodeGenInfo();
91 
92   // The default 32-bit code model is abs32/pic32 and the default 32-bit
93   // code model for JIT is abs32.
94   switch (CM) {
95   default: break;
96   case CodeModel::Default:
97   case CodeModel::JITDefault: CM = CodeModel::Small; break;
98   }
99 
100   X->initMCCodeGenInfo(RM, CM, OL);
101   return X;
102 }
103 
104 static MCCodeGenInfo *createSparcV9MCCodeGenInfo(const Triple &TT,
105                                                  Reloc::Model RM,
106                                                  CodeModel::Model CM,
107                                                  CodeGenOpt::Level OL) {
108   MCCodeGenInfo *X = new MCCodeGenInfo();
109 
110   // The default 64-bit code model is abs44/pic32 and the default 64-bit
111   // code model for JIT is abs64.
112   switch (CM) {
113   default:  break;
114   case CodeModel::Default:
115     CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium;
116     break;
117   case CodeModel::JITDefault:
118     CM = CodeModel::Large;
119     break;
120   }
121 
122   X->initMCCodeGenInfo(RM, CM, OL);
123   return X;
124 }
125 
126 static MCTargetStreamer *
127 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
128   return new SparcTargetELFStreamer(S);
129 }
130 
131 static MCTargetStreamer *createTargetAsmStreamer(MCStreamer &S,
132                                                  formatted_raw_ostream &OS,
133                                                  MCInstPrinter *InstPrint,
134                                                  bool isVerboseAsm) {
135   return new SparcTargetAsmStreamer(S, OS);
136 }
137 
138 static MCInstPrinter *createSparcMCInstPrinter(const Triple &T,
139                                                unsigned SyntaxVariant,
140                                                const MCAsmInfo &MAI,
141                                                const MCInstrInfo &MII,
142                                                const MCRegisterInfo &MRI) {
143   return new SparcInstPrinter(MAI, MII, MRI);
144 }
145 
146 extern "C" void LLVMInitializeSparcTargetMC() {
147   // Register the MC asm info.
148   RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo);
149   RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo);
150   RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo);
151 
152   for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) {
153     // Register the MC instruction info.
154     TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo);
155 
156     // Register the MC register info.
157     TargetRegistry::RegisterMCRegInfo(*T, createSparcMCRegisterInfo);
158 
159     // Register the MC subtarget info.
160     TargetRegistry::RegisterMCSubtargetInfo(*T, createSparcMCSubtargetInfo);
161 
162     // Register the MC Code Emitter.
163     TargetRegistry::RegisterMCCodeEmitter(*T, createSparcMCCodeEmitter);
164 
165     // Register the asm backend.
166     TargetRegistry::RegisterMCAsmBackend(*T, createSparcAsmBackend);
167 
168     // Register the object target streamer.
169     TargetRegistry::RegisterObjectTargetStreamer(*T,
170                                                  createObjectTargetStreamer);
171 
172     // Register the asm streamer.
173     TargetRegistry::RegisterAsmTargetStreamer(*T, createTargetAsmStreamer);
174 
175     // Register the MCInstPrinter
176     TargetRegistry::RegisterMCInstPrinter(*T, createSparcMCInstPrinter);
177   }
178 
179   // Register the MC codegen info.
180   TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget,
181                                         createSparcMCCodeGenInfo);
182   TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target,
183                                         createSparcV9MCCodeGenInfo);
184   TargetRegistry::RegisterMCCodeGenInfo(TheSparcelTarget,
185                                         createSparcMCCodeGenInfo);
186 }
187