1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SparcMCCodeEmitter class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/SparcFixupKinds.h"
14 #include "SparcMCExpr.h"
15 #include "SparcMCTargetDesc.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCFixup.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrInfo.h"
25 #include "llvm/MC/MCObjectFileInfo.h"
26 #include "llvm/MC/MCRegisterInfo.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCSymbol.h"
29 #include "llvm/MC/SubtargetFeature.h"
30 #include "llvm/Support/Casting.h"
31 #include "llvm/Support/Endian.h"
32 #include "llvm/Support/EndianStream.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include <cassert>
36 #include <cstdint>
37 
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "mccodeemitter"
41 
42 STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
43 
44 namespace {
45 
46 class SparcMCCodeEmitter : public MCCodeEmitter {
47   const MCInstrInfo &MCII;
48   MCContext &Ctx;
49 
50 public:
51   SparcMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
52       : MCII(mcii), Ctx(ctx) {}
53   SparcMCCodeEmitter(const SparcMCCodeEmitter &) = delete;
54   SparcMCCodeEmitter &operator=(const SparcMCCodeEmitter &) = delete;
55   ~SparcMCCodeEmitter() override = default;
56 
57   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
58                          SmallVectorImpl<MCFixup> &Fixups,
59                          const MCSubtargetInfo &STI) const override;
60 
61   // getBinaryCodeForInstr - TableGen'erated function for getting the
62   // binary encoding for an instruction.
63   uint64_t getBinaryCodeForInstr(const MCInst &MI,
64                                  SmallVectorImpl<MCFixup> &Fixups,
65                                  const MCSubtargetInfo &STI) const;
66 
67   /// getMachineOpValue - Return binary encoding of operand. If the machine
68   /// operand requires relocation, record the relocation and return zero.
69   unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
70                              SmallVectorImpl<MCFixup> &Fixups,
71                              const MCSubtargetInfo &STI) const;
72   unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
73                              SmallVectorImpl<MCFixup> &Fixups,
74                              const MCSubtargetInfo &STI) const;
75   unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
76                              SmallVectorImpl<MCFixup> &Fixups,
77                              const MCSubtargetInfo &STI) const;
78   unsigned getSImm13OpValue(const MCInst &MI, unsigned OpNo,
79                             SmallVectorImpl<MCFixup> &Fixups,
80                             const MCSubtargetInfo &STI) const;
81   unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
82                                       SmallVectorImpl<MCFixup> &Fixups,
83                                       const MCSubtargetInfo &STI) const;
84   unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
85                                        SmallVectorImpl<MCFixup> &Fixups,
86                                        const MCSubtargetInfo &STI) const;
87 
88 private:
89   FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const;
90   void
91   verifyInstructionPredicates(const MCInst &MI,
92                               const FeatureBitset &AvailableFeatures) const;
93 };
94 
95 } // end anonymous namespace
96 
97 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
98                                            SmallVectorImpl<MCFixup> &Fixups,
99                                            const MCSubtargetInfo &STI) const {
100   verifyInstructionPredicates(MI,
101                               computeAvailableFeatures(STI.getFeatureBits()));
102 
103   unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
104   support::endian::write(OS, Bits,
105                          Ctx.getAsmInfo()->isLittleEndian() ? support::little
106                                                             : support::big);
107 
108   // Some instructions have phantom operands that only contribute a fixup entry.
109   unsigned SymOpNo = 0;
110   switch (MI.getOpcode()) {
111   default: break;
112   case SP::TLS_CALL:   SymOpNo = 1; break;
113   case SP::GDOP_LDrr:
114   case SP::GDOP_LDXrr:
115   case SP::TLS_ADDrr:
116   case SP::TLS_ADDXrr:
117   case SP::TLS_LDrr:
118   case SP::TLS_LDXrr:  SymOpNo = 3; break;
119   }
120   if (SymOpNo != 0) {
121     const MCOperand &MO = MI.getOperand(SymOpNo);
122     uint64_t op = getMachineOpValue(MI, MO, Fixups, STI);
123     assert(op == 0 && "Unexpected operand value!");
124     (void)op; // suppress warning.
125   }
126 
127   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
128 }
129 
130 unsigned SparcMCCodeEmitter::
131 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
132                   SmallVectorImpl<MCFixup> &Fixups,
133                   const MCSubtargetInfo &STI) const {
134   if (MO.isReg())
135     return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
136 
137   if (MO.isImm())
138     return MO.getImm();
139 
140   assert(MO.isExpr());
141   const MCExpr *Expr = MO.getExpr();
142   if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
143     MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind();
144     Fixups.push_back(MCFixup::create(0, Expr, Kind));
145     return 0;
146   }
147 
148   int64_t Res;
149   if (Expr->evaluateAsAbsolute(Res))
150     return Res;
151 
152   llvm_unreachable("Unhandled expression!");
153   return 0;
154 }
155 
156 unsigned
157 SparcMCCodeEmitter::getSImm13OpValue(const MCInst &MI, unsigned OpNo,
158                                      SmallVectorImpl<MCFixup> &Fixups,
159                                      const MCSubtargetInfo &STI) const {
160   const MCOperand &MO = MI.getOperand(OpNo);
161 
162   if (MO.isImm())
163     return MO.getImm();
164 
165   assert(MO.isExpr() &&
166          "getSImm13OpValue expects only expressions or an immediate");
167 
168   const MCExpr *Expr = MO.getExpr();
169 
170   // Constant value, no fixup is needed
171   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
172     return CE->getValue();
173 
174   MCFixupKind Kind;
175   if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
176     Kind = MCFixupKind(SExpr->getFixupKind());
177   } else {
178     bool IsPic = Ctx.getObjectFileInfo()->isPositionIndependent();
179     Kind = IsPic ? MCFixupKind(Sparc::fixup_sparc_got13)
180                  : MCFixupKind(Sparc::fixup_sparc_13);
181   }
182 
183   Fixups.push_back(MCFixup::create(0, Expr, Kind));
184   return 0;
185 }
186 
187 unsigned SparcMCCodeEmitter::
188 getCallTargetOpValue(const MCInst &MI, unsigned OpNo,
189                      SmallVectorImpl<MCFixup> &Fixups,
190                      const MCSubtargetInfo &STI) const {
191   const MCOperand &MO = MI.getOperand(OpNo);
192   const MCExpr *Expr = MO.getExpr();
193   const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr);
194 
195   if (MI.getOpcode() == SP::TLS_CALL) {
196     // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in
197     // encodeInstruction.
198 #ifndef NDEBUG
199     // Verify that the callee is actually __tls_get_addr.
200     assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef &&
201            "Unexpected expression in TLS_CALL");
202     const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr());
203     assert(SymExpr->getSymbol().getName() == "__tls_get_addr" &&
204            "Unexpected function for TLS_CALL");
205 #endif
206     return 0;
207   }
208 
209   MCFixupKind Kind = MCFixupKind(SExpr->getFixupKind());
210   Fixups.push_back(MCFixup::create(0, Expr, Kind));
211   return 0;
212 }
213 
214 unsigned SparcMCCodeEmitter::
215 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
216                   SmallVectorImpl<MCFixup> &Fixups,
217                   const MCSubtargetInfo &STI) const {
218   const MCOperand &MO = MI.getOperand(OpNo);
219   if (MO.isReg() || MO.isImm())
220     return getMachineOpValue(MI, MO, Fixups, STI);
221 
222   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
223                                    (MCFixupKind)Sparc::fixup_sparc_br22));
224   return 0;
225 }
226 
227 unsigned SparcMCCodeEmitter::
228 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
229                            SmallVectorImpl<MCFixup> &Fixups,
230                            const MCSubtargetInfo &STI) const {
231   const MCOperand &MO = MI.getOperand(OpNo);
232   if (MO.isReg() || MO.isImm())
233     return getMachineOpValue(MI, MO, Fixups, STI);
234 
235   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
236                                    (MCFixupKind)Sparc::fixup_sparc_br19));
237   return 0;
238 }
239 
240 unsigned SparcMCCodeEmitter::
241 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
242                            SmallVectorImpl<MCFixup> &Fixups,
243                            const MCSubtargetInfo &STI) const {
244   const MCOperand &MO = MI.getOperand(OpNo);
245   if (MO.isReg() || MO.isImm())
246     return getMachineOpValue(MI, MO, Fixups, STI);
247 
248   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
249                                    (MCFixupKind)Sparc::fixup_sparc_br16_2));
250   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
251                                    (MCFixupKind)Sparc::fixup_sparc_br16_14));
252 
253   return 0;
254 }
255 
256 #define ENABLE_INSTR_PREDICATE_VERIFIER
257 #include "SparcGenMCCodeEmitter.inc"
258 
259 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
260                                               MCContext &Ctx) {
261   return new SparcMCCodeEmitter(MCII, Ctx);
262 }
263