1 //===-- SparcMCCodeEmitter.cpp - Convert Sparc code to machine code -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SparcMCCodeEmitter class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "mccodeemitter" 15 #include "SparcMCExpr.h" 16 #include "MCTargetDesc/SparcFixupKinds.h" 17 #include "SparcMCTargetDesc.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/MC/MCCodeEmitter.h" 20 #include "llvm/MC/MCContext.h" 21 #include "llvm/MC/MCExpr.h" 22 #include "llvm/MC/MCInst.h" 23 #include "llvm/MC/MCRegisterInfo.h" 24 #include "llvm/MC/MCSymbol.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 using namespace llvm; 28 29 STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); 30 31 namespace { 32 class SparcMCCodeEmitter : public MCCodeEmitter { 33 SparcMCCodeEmitter(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; 34 void operator=(const SparcMCCodeEmitter &) LLVM_DELETED_FUNCTION; 35 MCContext &Ctx; 36 37 public: 38 SparcMCCodeEmitter(MCContext &ctx): Ctx(ctx) {} 39 40 ~SparcMCCodeEmitter() {} 41 42 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 43 SmallVectorImpl<MCFixup> &Fixups, 44 const MCSubtargetInfo &STI) const; 45 46 // getBinaryCodeForInstr - TableGen'erated function for getting the 47 // binary encoding for an instruction. 48 uint64_t getBinaryCodeForInstr(const MCInst &MI, 49 SmallVectorImpl<MCFixup> &Fixups, 50 const MCSubtargetInfo &STI) const; 51 52 /// getMachineOpValue - Return binary encoding of operand. If the machine 53 /// operand requires relocation, record the relocation and return zero. 54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 55 SmallVectorImpl<MCFixup> &Fixups, 56 const MCSubtargetInfo &STI) const; 57 58 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 59 SmallVectorImpl<MCFixup> &Fixups, 60 const MCSubtargetInfo &STI) const; 61 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 62 SmallVectorImpl<MCFixup> &Fixups, 63 const MCSubtargetInfo &STI) const; 64 65 }; 66 } // end anonymous namespace 67 68 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII, 69 const MCRegisterInfo &MRI, 70 const MCSubtargetInfo &STI, 71 MCContext &Ctx) { 72 return new SparcMCCodeEmitter(Ctx); 73 } 74 75 void SparcMCCodeEmitter:: 76 EncodeInstruction(const MCInst &MI, raw_ostream &OS, 77 SmallVectorImpl<MCFixup> &Fixups, 78 const MCSubtargetInfo &STI) const { 79 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); 80 81 // Output the constant in big endian byte order. 82 for (unsigned i = 0; i != 4; ++i) { 83 OS << (char)(Bits >> 24); 84 Bits <<= 8; 85 } 86 unsigned tlsOpNo = 0; 87 switch (MI.getOpcode()) { 88 default: break; 89 case SP::TLS_CALL: tlsOpNo = 1; break; 90 case SP::TLS_ADDrr: 91 case SP::TLS_ADDXrr: 92 case SP::TLS_LDrr: 93 case SP::TLS_LDXrr: tlsOpNo = 3; break; 94 } 95 if (tlsOpNo != 0) { 96 const MCOperand &MO = MI.getOperand(tlsOpNo); 97 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); 98 assert(op == 0 && "Unexpected operand value!"); 99 (void)op; // suppress warning. 100 } 101 102 ++MCNumEmitted; // Keep track of the # of mi's emitted. 103 } 104 105 106 unsigned SparcMCCodeEmitter:: 107 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 108 SmallVectorImpl<MCFixup> &Fixups, 109 const MCSubtargetInfo &STI) const { 110 111 if (MO.isReg()) 112 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); 113 114 if (MO.isImm()) 115 return MO.getImm(); 116 117 assert(MO.isExpr()); 118 const MCExpr *Expr = MO.getExpr(); 119 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) { 120 MCFixupKind Kind = (MCFixupKind)SExpr->getFixupKind(); 121 Fixups.push_back(MCFixup::Create(0, Expr, Kind)); 122 return 0; 123 } 124 125 int64_t Res; 126 if (Expr->EvaluateAsAbsolute(Res)) 127 return Res; 128 129 assert(0 && "Unhandled expression!"); 130 return 0; 131 } 132 133 unsigned SparcMCCodeEmitter:: 134 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 135 SmallVectorImpl<MCFixup> &Fixups, 136 const MCSubtargetInfo &STI) const { 137 const MCOperand &MO = MI.getOperand(OpNo); 138 if (MO.isReg() || MO.isImm()) 139 return getMachineOpValue(MI, MO, Fixups, STI); 140 141 if (MI.getOpcode() == SP::TLS_CALL) { 142 // No fixups for __tls_get_addr. Will emit for fixups for tls_symbol in 143 // EncodeInstruction. 144 #ifndef NDEBUG 145 // Verify that the callee is actually __tls_get_addr. 146 const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr()); 147 assert(SExpr && SExpr->getSubExpr()->getKind() == MCExpr::SymbolRef && 148 "Unexpected expression in TLS_CALL"); 149 const MCSymbolRefExpr *SymExpr = cast<MCSymbolRefExpr>(SExpr->getSubExpr()); 150 assert(SymExpr->getSymbol().getName() == "__tls_get_addr" && 151 "Unexpected function for TLS_CALL"); 152 #endif 153 return 0; 154 } 155 156 MCFixupKind fixupKind = (MCFixupKind)Sparc::fixup_sparc_call30; 157 158 if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(MO.getExpr())) { 159 if (SExpr->getKind() == SparcMCExpr::VK_Sparc_WPLT30) 160 fixupKind = (MCFixupKind)Sparc::fixup_sparc_wplt30; 161 } 162 163 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), fixupKind)); 164 165 return 0; 166 } 167 168 unsigned SparcMCCodeEmitter:: 169 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 170 SmallVectorImpl<MCFixup> &Fixups, 171 const MCSubtargetInfo &STI) const { 172 const MCOperand &MO = MI.getOperand(OpNo); 173 if (MO.isReg() || MO.isImm()) 174 return getMachineOpValue(MI, MO, Fixups, STI); 175 176 Sparc::Fixups fixup = Sparc::fixup_sparc_br22; 177 if (MI.getOpcode() == SP::BPXCC) 178 fixup = Sparc::fixup_sparc_br19; 179 180 Fixups.push_back(MCFixup::Create(0, MO.getExpr(), 181 (MCFixupKind)fixup)); 182 return 0; 183 } 184 185 #include "SparcGenMCCodeEmitter.inc" 186