1 //===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/SparcFixupKinds.h" 11 #include "MCTargetDesc/SparcMCTargetDesc.h" 12 #include "llvm/MC/MCAsmBackend.h" 13 #include "llvm/MC/MCELFObjectWriter.h" 14 #include "llvm/MC/MCExpr.h" 15 #include "llvm/MC/MCFixupKindInfo.h" 16 #include "llvm/MC/MCObjectWriter.h" 17 #include "llvm/MC/MCValue.h" 18 #include "llvm/Support/TargetRegistry.h" 19 20 using namespace llvm; 21 22 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 23 switch (Kind) { 24 default: 25 llvm_unreachable("Unknown fixup kind!"); 26 case FK_Data_1: 27 case FK_Data_2: 28 case FK_Data_4: 29 case FK_Data_8: 30 return Value; 31 32 case Sparc::fixup_sparc_wplt30: 33 case Sparc::fixup_sparc_call30: 34 return (Value >> 2) & 0x3fffffff; 35 36 case Sparc::fixup_sparc_br22: 37 return (Value >> 2) & 0x3fffff; 38 39 case Sparc::fixup_sparc_br19: 40 return (Value >> 2) & 0x7ffff; 41 42 case Sparc::fixup_sparc_br16_2: 43 return (Value >> 2) & 0xc000; 44 45 case Sparc::fixup_sparc_br16_14: 46 return (Value >> 2) & 0x3fff; 47 48 case Sparc::fixup_sparc_pc22: 49 case Sparc::fixup_sparc_got22: 50 case Sparc::fixup_sparc_tls_gd_hi22: 51 case Sparc::fixup_sparc_tls_ldm_hi22: 52 case Sparc::fixup_sparc_tls_ie_hi22: 53 case Sparc::fixup_sparc_hi22: 54 return (Value >> 10) & 0x3fffff; 55 56 case Sparc::fixup_sparc_pc10: 57 case Sparc::fixup_sparc_got10: 58 case Sparc::fixup_sparc_tls_gd_lo10: 59 case Sparc::fixup_sparc_tls_ldm_lo10: 60 case Sparc::fixup_sparc_tls_ie_lo10: 61 case Sparc::fixup_sparc_lo10: 62 return Value & 0x3ff; 63 64 case Sparc::fixup_sparc_h44: 65 return (Value >> 22) & 0x3fffff; 66 67 case Sparc::fixup_sparc_m44: 68 return (Value >> 12) & 0x3ff; 69 70 case Sparc::fixup_sparc_l44: 71 return Value & 0xfff; 72 73 case Sparc::fixup_sparc_hh: 74 return (Value >> 42) & 0x3fffff; 75 76 case Sparc::fixup_sparc_hm: 77 return (Value >> 32) & 0x3ff; 78 79 case Sparc::fixup_sparc_tls_ldo_hix22: 80 case Sparc::fixup_sparc_tls_le_hix22: 81 case Sparc::fixup_sparc_tls_ldo_lox10: 82 case Sparc::fixup_sparc_tls_le_lox10: 83 assert(Value == 0 && "Sparc TLS relocs expect zero Value"); 84 return 0; 85 86 case Sparc::fixup_sparc_tls_gd_add: 87 case Sparc::fixup_sparc_tls_gd_call: 88 case Sparc::fixup_sparc_tls_ldm_add: 89 case Sparc::fixup_sparc_tls_ldm_call: 90 case Sparc::fixup_sparc_tls_ldo_add: 91 case Sparc::fixup_sparc_tls_ie_ld: 92 case Sparc::fixup_sparc_tls_ie_ldx: 93 case Sparc::fixup_sparc_tls_ie_add: 94 return 0; 95 } 96 } 97 98 namespace { 99 class SparcAsmBackend : public MCAsmBackend { 100 protected: 101 const Target &TheTarget; 102 bool IsLittleEndian; 103 bool Is64Bit; 104 105 public: 106 SparcAsmBackend(const Target &T) 107 : MCAsmBackend(), TheTarget(T), 108 IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"), 109 Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {} 110 111 unsigned getNumFixupKinds() const override { 112 return Sparc::NumTargetFixupKinds; 113 } 114 115 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 116 const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = { 117 // name offset bits flags 118 { "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 119 { "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 120 { "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel }, 121 { "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel }, 122 { "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel }, 123 { "fixup_sparc_hi22", 10, 22, 0 }, 124 { "fixup_sparc_lo10", 22, 10, 0 }, 125 { "fixup_sparc_h44", 10, 22, 0 }, 126 { "fixup_sparc_m44", 22, 10, 0 }, 127 { "fixup_sparc_l44", 20, 12, 0 }, 128 { "fixup_sparc_hh", 10, 22, 0 }, 129 { "fixup_sparc_hm", 22, 10, 0 }, 130 { "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel }, 131 { "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel }, 132 { "fixup_sparc_got22", 10, 22, 0 }, 133 { "fixup_sparc_got10", 22, 10, 0 }, 134 { "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel }, 135 { "fixup_sparc_tls_gd_hi22", 10, 22, 0 }, 136 { "fixup_sparc_tls_gd_lo10", 22, 10, 0 }, 137 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 138 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 139 { "fixup_sparc_tls_ldm_hi22", 10, 22, 0 }, 140 { "fixup_sparc_tls_ldm_lo10", 22, 10, 0 }, 141 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 142 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 143 { "fixup_sparc_tls_ldo_hix22", 10, 22, 0 }, 144 { "fixup_sparc_tls_ldo_lox10", 22, 10, 0 }, 145 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 146 { "fixup_sparc_tls_ie_hi22", 10, 22, 0 }, 147 { "fixup_sparc_tls_ie_lo10", 22, 10, 0 }, 148 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 149 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 150 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 151 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 152 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 153 }; 154 155 const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = { 156 // name offset bits flags 157 { "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 158 { "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 159 { "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel }, 160 { "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel }, 161 { "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel }, 162 { "fixup_sparc_hi22", 0, 22, 0 }, 163 { "fixup_sparc_lo10", 0, 10, 0 }, 164 { "fixup_sparc_h44", 0, 22, 0 }, 165 { "fixup_sparc_m44", 0, 10, 0 }, 166 { "fixup_sparc_l44", 0, 12, 0 }, 167 { "fixup_sparc_hh", 0, 22, 0 }, 168 { "fixup_sparc_hm", 0, 10, 0 }, 169 { "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel }, 170 { "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel }, 171 { "fixup_sparc_got22", 0, 22, 0 }, 172 { "fixup_sparc_got10", 0, 10, 0 }, 173 { "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel }, 174 { "fixup_sparc_tls_gd_hi22", 0, 22, 0 }, 175 { "fixup_sparc_tls_gd_lo10", 0, 10, 0 }, 176 { "fixup_sparc_tls_gd_add", 0, 0, 0 }, 177 { "fixup_sparc_tls_gd_call", 0, 0, 0 }, 178 { "fixup_sparc_tls_ldm_hi22", 0, 22, 0 }, 179 { "fixup_sparc_tls_ldm_lo10", 0, 10, 0 }, 180 { "fixup_sparc_tls_ldm_add", 0, 0, 0 }, 181 { "fixup_sparc_tls_ldm_call", 0, 0, 0 }, 182 { "fixup_sparc_tls_ldo_hix22", 0, 22, 0 }, 183 { "fixup_sparc_tls_ldo_lox10", 0, 10, 0 }, 184 { "fixup_sparc_tls_ldo_add", 0, 0, 0 }, 185 { "fixup_sparc_tls_ie_hi22", 0, 22, 0 }, 186 { "fixup_sparc_tls_ie_lo10", 0, 10, 0 }, 187 { "fixup_sparc_tls_ie_ld", 0, 0, 0 }, 188 { "fixup_sparc_tls_ie_ldx", 0, 0, 0 }, 189 { "fixup_sparc_tls_ie_add", 0, 0, 0 }, 190 { "fixup_sparc_tls_le_hix22", 0, 0, 0 }, 191 { "fixup_sparc_tls_le_lox10", 0, 0, 0 } 192 }; 193 194 if (Kind < FirstTargetFixupKind) 195 return MCAsmBackend::getFixupKindInfo(Kind); 196 197 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 198 "Invalid kind!"); 199 if (IsLittleEndian) 200 return InfosLE[Kind - FirstTargetFixupKind]; 201 202 return InfosBE[Kind - FirstTargetFixupKind]; 203 } 204 205 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 206 const MCValue &Target) override { 207 switch ((Sparc::Fixups)Fixup.getKind()) { 208 default: 209 return false; 210 case Sparc::fixup_sparc_wplt30: 211 if (Target.getSymA()->getSymbol().isTemporary()) 212 return false; 213 LLVM_FALLTHROUGH; 214 case Sparc::fixup_sparc_tls_gd_hi22: 215 case Sparc::fixup_sparc_tls_gd_lo10: 216 case Sparc::fixup_sparc_tls_gd_add: 217 case Sparc::fixup_sparc_tls_gd_call: 218 case Sparc::fixup_sparc_tls_ldm_hi22: 219 case Sparc::fixup_sparc_tls_ldm_lo10: 220 case Sparc::fixup_sparc_tls_ldm_add: 221 case Sparc::fixup_sparc_tls_ldm_call: 222 case Sparc::fixup_sparc_tls_ldo_hix22: 223 case Sparc::fixup_sparc_tls_ldo_lox10: 224 case Sparc::fixup_sparc_tls_ldo_add: 225 case Sparc::fixup_sparc_tls_ie_hi22: 226 case Sparc::fixup_sparc_tls_ie_lo10: 227 case Sparc::fixup_sparc_tls_ie_ld: 228 case Sparc::fixup_sparc_tls_ie_ldx: 229 case Sparc::fixup_sparc_tls_ie_add: 230 case Sparc::fixup_sparc_tls_le_hix22: 231 case Sparc::fixup_sparc_tls_le_lox10: 232 return true; 233 } 234 } 235 236 bool mayNeedRelaxation(const MCInst &Inst) const override { 237 // FIXME. 238 return false; 239 } 240 241 /// fixupNeedsRelaxation - Target specific predicate for whether a given 242 /// fixup requires the associated instruction to be relaxed. 243 bool fixupNeedsRelaxation(const MCFixup &Fixup, 244 uint64_t Value, 245 const MCRelaxableFragment *DF, 246 const MCAsmLayout &Layout) const override { 247 // FIXME. 248 llvm_unreachable("fixupNeedsRelaxation() unimplemented"); 249 return false; 250 } 251 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 252 MCInst &Res) const override { 253 // FIXME. 254 llvm_unreachable("relaxInstruction() unimplemented"); 255 } 256 257 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override { 258 // Cannot emit NOP with size not multiple of 32 bits. 259 if (Count % 4 != 0) 260 return false; 261 262 uint64_t NumNops = Count / 4; 263 for (uint64_t i = 0; i != NumNops; ++i) 264 OW->write32(0x01000000); 265 266 return true; 267 } 268 }; 269 270 class ELFSparcAsmBackend : public SparcAsmBackend { 271 Triple::OSType OSType; 272 public: 273 ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) : 274 SparcAsmBackend(T), OSType(OSType) { } 275 276 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 277 const MCValue &Target, MutableArrayRef<char> Data, 278 uint64_t Value, bool IsResolved) const override { 279 280 Value = adjustFixupValue(Fixup.getKind(), Value); 281 if (!Value) return; // Doesn't change encoding. 282 283 unsigned Offset = Fixup.getOffset(); 284 285 // For each byte of the fragment that the fixup touches, mask in the bits 286 // from the fixup value. The Value has been "split up" into the 287 // appropriate bitfields above. 288 for (unsigned i = 0; i != 4; ++i) { 289 unsigned Idx = IsLittleEndian ? i : 3 - i; 290 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 291 } 292 } 293 294 std::unique_ptr<MCObjectWriter> 295 createObjectWriter(raw_pwrite_stream &OS) const override { 296 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType); 297 return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI); 298 } 299 }; 300 301 } // end anonymous namespace 302 303 MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, 304 const MCRegisterInfo &MRI, 305 const Triple &TT, StringRef CPU, 306 const MCTargetOptions &Options) { 307 return new ELFSparcAsmBackend(T, TT.getOS()); 308 } 309