1 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This is a simple local pass that attempts to fill delay slots with useful
10 // instructions. If no instructions can be moved into the delay slot, then a
11 // NOP is placed.
12 //===----------------------------------------------------------------------===//
13 
14 #include "Sparc.h"
15 #include "SparcSubtarget.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Target/TargetMachine.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "delay-slot-filler"
29 
30 STATISTIC(FilledSlots, "Number of delay slots filled");
31 
32 static cl::opt<bool> DisableDelaySlotFiller(
33   "disable-sparc-delay-filler",
34   cl::init(false),
35   cl::desc("Disable the Sparc delay slot filler."),
36   cl::Hidden);
37 
38 namespace {
39   struct Filler : public MachineFunctionPass {
40     const SparcSubtarget *Subtarget = nullptr;
41 
42     static char ID;
43     Filler() : MachineFunctionPass(ID) {}
44 
45     StringRef getPassName() const override { return "SPARC Delay Slot Filler"; }
46 
47     bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
48     bool runOnMachineFunction(MachineFunction &F) override {
49       bool Changed = false;
50       Subtarget = &F.getSubtarget<SparcSubtarget>();
51 
52       // This pass invalidates liveness information when it reorders
53       // instructions to fill delay slot.
54       F.getRegInfo().invalidateLiveness();
55 
56       for (MachineBasicBlock &MBB : F)
57         Changed |= runOnMachineBasicBlock(MBB);
58       return Changed;
59     }
60 
61     MachineFunctionProperties getRequiredProperties() const override {
62       return MachineFunctionProperties().set(
63           MachineFunctionProperties::Property::NoVRegs);
64     }
65 
66     void insertCallDefsUses(MachineBasicBlock::iterator MI,
67                             SmallSet<unsigned, 32>& RegDefs,
68                             SmallSet<unsigned, 32>& RegUses);
69 
70     void insertDefsUses(MachineBasicBlock::iterator MI,
71                         SmallSet<unsigned, 32>& RegDefs,
72                         SmallSet<unsigned, 32>& RegUses);
73 
74     bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
75                     unsigned Reg);
76 
77     bool delayHasHazard(MachineBasicBlock::iterator candidate,
78                         bool &sawLoad, bool &sawStore,
79                         SmallSet<unsigned, 32> &RegDefs,
80                         SmallSet<unsigned, 32> &RegUses);
81 
82     MachineBasicBlock::iterator
83     findDelayInstr(MachineBasicBlock &MBB, MachineBasicBlock::iterator slot);
84 
85     bool needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize);
86 
87     bool tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
88                                        MachineBasicBlock::iterator MBBI);
89 
90   };
91   char Filler::ID = 0;
92 } // end of anonymous namespace
93 
94 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
95 /// slots in Sparc MachineFunctions
96 ///
97 FunctionPass *llvm::createSparcDelaySlotFillerPass() {
98   return new Filler;
99 }
100 
101 
102 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
103 /// We assume there is only one delay slot per delayed instruction.
104 ///
105 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
106   bool Changed = false;
107   Subtarget = &MBB.getParent()->getSubtarget<SparcSubtarget>();
108   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
109 
110   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
111     MachineBasicBlock::iterator MI = I;
112     ++I;
113 
114     // If MI is restore, try combining it with previous inst.
115     if (!DisableDelaySlotFiller &&
116         (MI->getOpcode() == SP::RESTORErr
117          || MI->getOpcode() == SP::RESTOREri)) {
118       Changed |= tryCombineRestoreWithPrevInst(MBB, MI);
119       continue;
120     }
121 
122     // TODO: If we ever want to support v7, this needs to be extended
123     // to cover all floating point operations.
124     if (!Subtarget->isV9() &&
125         (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD
126          || MI->getOpcode() == SP::FCMPQ)) {
127       BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
128       Changed = true;
129       continue;
130     }
131 
132     // If MI has no delay slot, skip.
133     if (!MI->hasDelaySlot())
134       continue;
135 
136     MachineBasicBlock::iterator D = MBB.end();
137 
138     if (!DisableDelaySlotFiller)
139       D = findDelayInstr(MBB, MI);
140 
141     ++FilledSlots;
142     Changed = true;
143 
144     if (D == MBB.end())
145       BuildMI(MBB, I, MI->getDebugLoc(), TII->get(SP::NOP));
146     else
147       MBB.splice(I, &MBB, D);
148 
149     unsigned structSize = 0;
150     if (needsUnimp(MI, structSize)) {
151       MachineBasicBlock::iterator J = MI;
152       ++J; // skip the delay filler.
153       assert (J != MBB.end() && "MI needs a delay instruction.");
154       BuildMI(MBB, ++J, MI->getDebugLoc(),
155               TII->get(SP::UNIMP)).addImm(structSize);
156       // Bundle the delay filler and unimp with the instruction.
157       MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), J);
158     } else {
159       MIBundleBuilder(MBB, MachineBasicBlock::iterator(MI), I);
160     }
161   }
162   return Changed;
163 }
164 
165 MachineBasicBlock::iterator
166 Filler::findDelayInstr(MachineBasicBlock &MBB,
167                        MachineBasicBlock::iterator slot)
168 {
169   SmallSet<unsigned, 32> RegDefs;
170   SmallSet<unsigned, 32> RegUses;
171   bool sawLoad = false;
172   bool sawStore = false;
173 
174   if (slot == MBB.begin())
175     return MBB.end();
176 
177   if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL)
178     return MBB.end();
179 
180   if (slot->getOpcode() == SP::RETL) {
181     MachineBasicBlock::iterator J = slot;
182     --J;
183 
184     if (J->getOpcode() == SP::RESTORErr
185         || J->getOpcode() == SP::RESTOREri) {
186       // change retl to ret.
187       slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET));
188       return J;
189     }
190   }
191 
192   // Call's delay filler can def some of call's uses.
193   if (slot->isCall())
194     insertCallDefsUses(slot, RegDefs, RegUses);
195   else
196     insertDefsUses(slot, RegDefs, RegUses);
197 
198   bool done = false;
199 
200   MachineBasicBlock::iterator I = slot;
201 
202   while (!done) {
203     done = (I == MBB.begin());
204 
205     if (!done)
206       --I;
207 
208     // skip debug instruction
209     if (I->isDebugInstr())
210       continue;
211 
212     if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
213         I->hasDelaySlot() || I->isBundledWithSucc())
214       break;
215 
216     if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
217       insertDefsUses(I, RegDefs, RegUses);
218       continue;
219     }
220 
221     return I;
222   }
223   return MBB.end();
224 }
225 
226 bool Filler::delayHasHazard(MachineBasicBlock::iterator candidate,
227                             bool &sawLoad,
228                             bool &sawStore,
229                             SmallSet<unsigned, 32> &RegDefs,
230                             SmallSet<unsigned, 32> &RegUses)
231 {
232 
233   if (candidate->isImplicitDef() || candidate->isKill())
234     return true;
235 
236   if (candidate->mayLoad()) {
237     sawLoad = true;
238     if (sawStore)
239       return true;
240   }
241 
242   if (candidate->mayStore()) {
243     if (sawStore)
244       return true;
245     sawStore = true;
246     if (sawLoad)
247       return true;
248   }
249 
250   for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
251     const MachineOperand &MO = candidate->getOperand(i);
252     if (!MO.isReg())
253       continue; // skip
254 
255     Register Reg = MO.getReg();
256 
257     if (MO.isDef()) {
258       // check whether Reg is defined or used before delay slot.
259       if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
260         return true;
261     }
262     if (MO.isUse()) {
263       // check whether Reg is defined before delay slot.
264       if (IsRegInSet(RegDefs, Reg))
265         return true;
266     }
267   }
268 
269   unsigned Opcode = candidate->getOpcode();
270   // LD and LDD may have NOPs inserted afterwards in the case of some LEON
271   // processors, so we can't use the delay slot if this feature is switched-on.
272   if (Subtarget->insertNOPLoad()
273       &&
274       Opcode >=  SP::LDDArr && Opcode <= SP::LDrr)
275     return true;
276 
277   // Same as above for FDIV and FSQRT on some LEON processors.
278   if (Subtarget->fixAllFDIVSQRT()
279       &&
280       Opcode >=  SP::FDIVD && Opcode <= SP::FSQRTD)
281     return true;
282 
283 
284   return false;
285 }
286 
287 
288 void Filler::insertCallDefsUses(MachineBasicBlock::iterator MI,
289                                 SmallSet<unsigned, 32>& RegDefs,
290                                 SmallSet<unsigned, 32>& RegUses)
291 {
292   // Call defines o7, which is visible to the instruction in delay slot.
293   RegDefs.insert(SP::O7);
294 
295   switch(MI->getOpcode()) {
296   default: llvm_unreachable("Unknown opcode.");
297   case SP::CALL: break;
298   case SP::CALLrr:
299   case SP::CALLri:
300     assert(MI->getNumOperands() >= 2);
301     const MachineOperand &Reg = MI->getOperand(0);
302     assert(Reg.isReg() && "CALL first operand is not a register.");
303     assert(Reg.isUse() && "CALL first operand is not a use.");
304     RegUses.insert(Reg.getReg());
305 
306     const MachineOperand &Operand1 = MI->getOperand(1);
307     if (Operand1.isImm() || Operand1.isGlobal())
308         break;
309     assert(Operand1.isReg() && "CALLrr second operand is not a register.");
310     assert(Operand1.isUse() && "CALLrr second operand is not a use.");
311     RegUses.insert(Operand1.getReg());
312     break;
313   }
314 }
315 
316 // Insert Defs and Uses of MI into the sets RegDefs and RegUses.
317 void Filler::insertDefsUses(MachineBasicBlock::iterator MI,
318                             SmallSet<unsigned, 32>& RegDefs,
319                             SmallSet<unsigned, 32>& RegUses)
320 {
321   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
322     const MachineOperand &MO = MI->getOperand(i);
323     if (!MO.isReg())
324       continue;
325 
326     Register Reg = MO.getReg();
327     if (Reg == 0)
328       continue;
329     if (MO.isDef())
330       RegDefs.insert(Reg);
331     if (MO.isUse()) {
332       // Implicit register uses of retl are return values and
333       // retl does not use them.
334       if (MO.isImplicit() && MI->getOpcode() == SP::RETL)
335         continue;
336       RegUses.insert(Reg);
337     }
338   }
339 }
340 
341 // returns true if the Reg or its alias is in the RegSet.
342 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg)
343 {
344   // Check Reg and all aliased Registers.
345   for (MCRegAliasIterator AI(Reg, Subtarget->getRegisterInfo(), true);
346        AI.isValid(); ++AI)
347     if (RegSet.count(*AI))
348       return true;
349   return false;
350 }
351 
352 bool Filler::needsUnimp(MachineBasicBlock::iterator I, unsigned &StructSize)
353 {
354   if (!I->isCall())
355     return false;
356 
357   unsigned structSizeOpNum = 0;
358   switch (I->getOpcode()) {
359   default: llvm_unreachable("Unknown call opcode.");
360   case SP::CALL: structSizeOpNum = 1; break;
361   case SP::CALLrr:
362   case SP::CALLri: structSizeOpNum = 2; break;
363   case SP::TLS_CALL: return false;
364   }
365 
366   const MachineOperand &MO = I->getOperand(structSizeOpNum);
367   if (!MO.isImm())
368     return false;
369   StructSize = MO.getImm();
370   return true;
371 }
372 
373 static bool combineRestoreADD(MachineBasicBlock::iterator RestoreMI,
374                               MachineBasicBlock::iterator AddMI,
375                               const TargetInstrInfo *TII)
376 {
377   // Before:  add  <op0>, <op1>, %i[0-7]
378   //          restore %g0, %g0, %i[0-7]
379   //
380   // After :  restore <op0>, <op1>, %o[0-7]
381 
382   Register reg = AddMI->getOperand(0).getReg();
383   if (reg < SP::I0 || reg > SP::I7)
384     return false;
385 
386   // Erase RESTORE.
387   RestoreMI->eraseFromParent();
388 
389   // Change ADD to RESTORE.
390   AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr)
391                           ? SP::RESTORErr
392                           : SP::RESTOREri));
393 
394   // Map the destination register.
395   AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
396 
397   return true;
398 }
399 
400 static bool combineRestoreOR(MachineBasicBlock::iterator RestoreMI,
401                              MachineBasicBlock::iterator OrMI,
402                              const TargetInstrInfo *TII)
403 {
404   // Before:  or  <op0>, <op1>, %i[0-7]
405   //          restore %g0, %g0, %i[0-7]
406   //    and <op0> or <op1> is zero,
407   //
408   // After :  restore <op0>, <op1>, %o[0-7]
409 
410   Register reg = OrMI->getOperand(0).getReg();
411   if (reg < SP::I0 || reg > SP::I7)
412     return false;
413 
414   // check whether it is a copy.
415   if (OrMI->getOpcode() == SP::ORrr
416       && OrMI->getOperand(1).getReg() != SP::G0
417       && OrMI->getOperand(2).getReg() != SP::G0)
418     return false;
419 
420   if (OrMI->getOpcode() == SP::ORri
421       && OrMI->getOperand(1).getReg() != SP::G0
422       && (!OrMI->getOperand(2).isImm() || OrMI->getOperand(2).getImm() != 0))
423     return false;
424 
425   // Erase RESTORE.
426   RestoreMI->eraseFromParent();
427 
428   // Change OR to RESTORE.
429   OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr)
430                          ? SP::RESTORErr
431                          : SP::RESTOREri));
432 
433   // Map the destination register.
434   OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
435 
436   return true;
437 }
438 
439 static bool combineRestoreSETHIi(MachineBasicBlock::iterator RestoreMI,
440                                  MachineBasicBlock::iterator SetHiMI,
441                                  const TargetInstrInfo *TII)
442 {
443   // Before:  sethi imm3, %i[0-7]
444   //          restore %g0, %g0, %g0
445   //
446   // After :  restore %g0, (imm3<<10), %o[0-7]
447 
448   Register reg = SetHiMI->getOperand(0).getReg();
449   if (reg < SP::I0 || reg > SP::I7)
450     return false;
451 
452   if (!SetHiMI->getOperand(1).isImm())
453     return false;
454 
455   int64_t imm = SetHiMI->getOperand(1).getImm();
456 
457   // Is it a 3 bit immediate?
458   if (!isInt<3>(imm))
459     return false;
460 
461   // Make it a 13 bit immediate.
462   imm = (imm << 10) & 0x1FFF;
463 
464   assert(RestoreMI->getOpcode() == SP::RESTORErr);
465 
466   RestoreMI->setDesc(TII->get(SP::RESTOREri));
467 
468   RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0);
469   RestoreMI->getOperand(1).setReg(SP::G0);
470   RestoreMI->getOperand(2).ChangeToImmediate(imm);
471 
472 
473   // Erase the original SETHI.
474   SetHiMI->eraseFromParent();
475 
476   return true;
477 }
478 
479 bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB,
480                                         MachineBasicBlock::iterator MBBI)
481 {
482   // No previous instruction.
483   if (MBBI == MBB.begin())
484     return false;
485 
486   // assert that MBBI is a "restore %g0, %g0, %g0".
487   assert(MBBI->getOpcode() == SP::RESTORErr
488          && MBBI->getOperand(0).getReg() == SP::G0
489          && MBBI->getOperand(1).getReg() == SP::G0
490          && MBBI->getOperand(2).getReg() == SP::G0);
491 
492   MachineBasicBlock::iterator PrevInst = std::prev(MBBI);
493 
494   // It cannot be combined with a bundled instruction.
495   if (PrevInst->isBundledWithSucc())
496     return false;
497 
498   const TargetInstrInfo *TII = Subtarget->getInstrInfo();
499 
500   switch (PrevInst->getOpcode()) {
501   default: break;
502   case SP::ADDrr:
503   case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break;
504   case SP::ORrr:
505   case SP::ORri:  return combineRestoreOR(MBBI, PrevInst, TII); break;
506   case SP::SETHIi: return combineRestoreSETHIi(MBBI, PrevInst, TII); break;
507   }
508   // It cannot combine with the previous instruction.
509   return false;
510 }
511