1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SparcMCExpr.h"
11 #include "MCTargetDesc/SparcMCTargetDesc.h"
12 #include "llvm/ADT/STLExtras.h"
13 #include "llvm/MC/MCContext.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCObjectFileInfo.h"
16 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
17 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/TargetRegistry.h"
23 
24 using namespace llvm;
25 
26 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
27 // namespace. But SPARC backend uses "SP" as its namespace.
28 namespace llvm {
29   namespace Sparc {
30     using namespace SP;
31   }
32 }
33 
34 namespace {
35 class SparcOperand;
36 class SparcAsmParser : public MCTargetAsmParser {
37 
38   MCAsmParser &Parser;
39 
40   /// @name Auto-generated Match Functions
41   /// {
42 
43 #define GET_ASSEMBLER_HEADER
44 #include "SparcGenAsmMatcher.inc"
45 
46   /// }
47 
48   // public interface of the MCTargetAsmParser.
49   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
50                                OperandVector &Operands, MCStreamer &Out,
51                                uint64_t &ErrorInfo,
52                                bool MatchingInlineAsm) override;
53   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
54   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
55                         SMLoc NameLoc, OperandVector &Operands) override;
56   bool ParseDirective(AsmToken DirectiveID) override;
57 
58   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
59                                       unsigned Kind) override;
60 
61   // Custom parse functions for Sparc specific operands.
62   OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
63 
64   OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
65 
66   OperandMatchResultTy
67   parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
68                        bool isCall = false);
69 
70   OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
71 
72   // Helper function for dealing with %lo / %hi in PIC mode.
73   const SparcMCExpr *adjustPICRelocation(SparcMCExpr::VariantKind VK,
74                                          const MCExpr *subExpr);
75 
76   // returns true if Tok is matched to a register and returns register in RegNo.
77   bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
78                          unsigned &RegKind);
79 
80   bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
81   bool parseDirectiveWord(unsigned Size, SMLoc L);
82 
83   bool is64Bit() const {
84     return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
85   }
86 
87   void expandSET(MCInst &Inst, SMLoc IDLoc,
88                  SmallVectorImpl<MCInst> &Instructions);
89 
90 public:
91   SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
92                 const MCInstrInfo &MII,
93                 const MCTargetOptions &Options)
94       : MCTargetAsmParser(Options, sti), Parser(parser) {
95     // Initialize the set of available features.
96     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
97   }
98 
99 };
100 
101   static const MCPhysReg IntRegs[32] = {
102     Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
103     Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
104     Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
105     Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
106     Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
107     Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
108     Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
109     Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
110 
111   static const MCPhysReg FloatRegs[32] = {
112     Sparc::F0,  Sparc::F1,  Sparc::F2,  Sparc::F3,
113     Sparc::F4,  Sparc::F5,  Sparc::F6,  Sparc::F7,
114     Sparc::F8,  Sparc::F9,  Sparc::F10, Sparc::F11,
115     Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
116     Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
117     Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
118     Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
119     Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
120 
121   static const MCPhysReg DoubleRegs[32] = {
122     Sparc::D0,  Sparc::D1,  Sparc::D2,  Sparc::D3,
123     Sparc::D4,  Sparc::D5,  Sparc::D6,  Sparc::D7,
124     Sparc::D8,  Sparc::D7,  Sparc::D8,  Sparc::D9,
125     Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
126     Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
127     Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
128     Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
129     Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
130 
131   static const MCPhysReg QuadFPRegs[32] = {
132     Sparc::Q0,  Sparc::Q1,  Sparc::Q2,  Sparc::Q3,
133     Sparc::Q4,  Sparc::Q5,  Sparc::Q6,  Sparc::Q7,
134     Sparc::Q8,  Sparc::Q9,  Sparc::Q10, Sparc::Q11,
135     Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
136 
137   static const MCPhysReg ASRRegs[32] = {
138     SP::Y,     SP::ASR1,  SP::ASR2,  SP::ASR3,
139     SP::ASR4,  SP::ASR5,  SP::ASR6, SP::ASR7,
140     SP::ASR8,  SP::ASR9,  SP::ASR10, SP::ASR11,
141     SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
142     SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
143     SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
144     SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
145     SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
146 
147   static const MCPhysReg IntPairRegs[] = {
148     Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
149     Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
150     Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
151     Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
152 
153   static const MCPhysReg CoprocRegs[32] = {
154     Sparc::C0,  Sparc::C1,  Sparc::C2,  Sparc::C3,
155     Sparc::C4,  Sparc::C5,  Sparc::C6,  Sparc::C7,
156     Sparc::C8,  Sparc::C9,  Sparc::C10, Sparc::C11,
157     Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
158     Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
159     Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
160     Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
161     Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
162 
163   static const MCPhysReg CoprocPairRegs[] = {
164     Sparc::C0_C1,   Sparc::C2_C3,   Sparc::C4_C5,   Sparc::C6_C7,
165     Sparc::C8_C9,   Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
166     Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
167     Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
168 
169 /// SparcOperand - Instances of this class represent a parsed Sparc machine
170 /// instruction.
171 class SparcOperand : public MCParsedAsmOperand {
172 public:
173   enum RegisterKind {
174     rk_None,
175     rk_IntReg,
176     rk_IntPairReg,
177     rk_FloatReg,
178     rk_DoubleReg,
179     rk_QuadReg,
180     rk_CoprocReg,
181     rk_CoprocPairReg,
182     rk_Special,
183   };
184 
185 private:
186   enum KindTy {
187     k_Token,
188     k_Register,
189     k_Immediate,
190     k_MemoryReg,
191     k_MemoryImm
192   } Kind;
193 
194   SMLoc StartLoc, EndLoc;
195 
196   struct Token {
197     const char *Data;
198     unsigned Length;
199   };
200 
201   struct RegOp {
202     unsigned RegNum;
203     RegisterKind Kind;
204   };
205 
206   struct ImmOp {
207     const MCExpr *Val;
208   };
209 
210   struct MemOp {
211     unsigned Base;
212     unsigned OffsetReg;
213     const MCExpr *Off;
214   };
215 
216   union {
217     struct Token Tok;
218     struct RegOp Reg;
219     struct ImmOp Imm;
220     struct MemOp Mem;
221   };
222 public:
223   SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
224 
225   bool isToken() const override { return Kind == k_Token; }
226   bool isReg() const override { return Kind == k_Register; }
227   bool isImm() const override { return Kind == k_Immediate; }
228   bool isMem() const override { return isMEMrr() || isMEMri(); }
229   bool isMEMrr() const { return Kind == k_MemoryReg; }
230   bool isMEMri() const { return Kind == k_MemoryImm; }
231 
232   bool isIntReg() const {
233     return (Kind == k_Register && Reg.Kind == rk_IntReg);
234   }
235 
236   bool isFloatReg() const {
237     return (Kind == k_Register && Reg.Kind == rk_FloatReg);
238   }
239 
240   bool isFloatOrDoubleReg() const {
241     return (Kind == k_Register && (Reg.Kind == rk_FloatReg
242                                    || Reg.Kind == rk_DoubleReg));
243   }
244 
245   bool isCoprocReg() const {
246     return (Kind == k_Register && Reg.Kind == rk_CoprocReg);
247   }
248 
249   StringRef getToken() const {
250     assert(Kind == k_Token && "Invalid access!");
251     return StringRef(Tok.Data, Tok.Length);
252   }
253 
254   unsigned getReg() const override {
255     assert((Kind == k_Register) && "Invalid access!");
256     return Reg.RegNum;
257   }
258 
259   const MCExpr *getImm() const {
260     assert((Kind == k_Immediate) && "Invalid access!");
261     return Imm.Val;
262   }
263 
264   unsigned getMemBase() const {
265     assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
266     return Mem.Base;
267   }
268 
269   unsigned getMemOffsetReg() const {
270     assert((Kind == k_MemoryReg) && "Invalid access!");
271     return Mem.OffsetReg;
272   }
273 
274   const MCExpr *getMemOff() const {
275     assert((Kind == k_MemoryImm) && "Invalid access!");
276     return Mem.Off;
277   }
278 
279   /// getStartLoc - Get the location of the first token of this operand.
280   SMLoc getStartLoc() const override {
281     return StartLoc;
282   }
283   /// getEndLoc - Get the location of the last token of this operand.
284   SMLoc getEndLoc() const override {
285     return EndLoc;
286   }
287 
288   void print(raw_ostream &OS) const override {
289     switch (Kind) {
290     case k_Token:     OS << "Token: " << getToken() << "\n"; break;
291     case k_Register:  OS << "Reg: #" << getReg() << "\n"; break;
292     case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
293     case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
294                          << getMemOffsetReg() << "\n"; break;
295     case k_MemoryImm: assert(getMemOff() != nullptr);
296       OS << "Mem: " << getMemBase()
297          << "+" << *getMemOff()
298          << "\n"; break;
299     }
300   }
301 
302   void addRegOperands(MCInst &Inst, unsigned N) const {
303     assert(N == 1 && "Invalid number of operands!");
304     Inst.addOperand(MCOperand::createReg(getReg()));
305   }
306 
307   void addImmOperands(MCInst &Inst, unsigned N) const {
308     assert(N == 1 && "Invalid number of operands!");
309     const MCExpr *Expr = getImm();
310     addExpr(Inst, Expr);
311   }
312 
313   void addExpr(MCInst &Inst, const MCExpr *Expr) const{
314     // Add as immediate when possible.  Null MCExpr = 0.
315     if (!Expr)
316       Inst.addOperand(MCOperand::createImm(0));
317     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
318       Inst.addOperand(MCOperand::createImm(CE->getValue()));
319     else
320       Inst.addOperand(MCOperand::createExpr(Expr));
321   }
322 
323   void addMEMrrOperands(MCInst &Inst, unsigned N) const {
324     assert(N == 2 && "Invalid number of operands!");
325 
326     Inst.addOperand(MCOperand::createReg(getMemBase()));
327 
328     assert(getMemOffsetReg() != 0 && "Invalid offset");
329     Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
330   }
331 
332   void addMEMriOperands(MCInst &Inst, unsigned N) const {
333     assert(N == 2 && "Invalid number of operands!");
334 
335     Inst.addOperand(MCOperand::createReg(getMemBase()));
336 
337     const MCExpr *Expr = getMemOff();
338     addExpr(Inst, Expr);
339   }
340 
341   static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
342     auto Op = make_unique<SparcOperand>(k_Token);
343     Op->Tok.Data = Str.data();
344     Op->Tok.Length = Str.size();
345     Op->StartLoc = S;
346     Op->EndLoc = S;
347     return Op;
348   }
349 
350   static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
351                                                  SMLoc S, SMLoc E) {
352     auto Op = make_unique<SparcOperand>(k_Register);
353     Op->Reg.RegNum = RegNum;
354     Op->Reg.Kind   = (SparcOperand::RegisterKind)Kind;
355     Op->StartLoc = S;
356     Op->EndLoc = E;
357     return Op;
358   }
359 
360   static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
361                                                  SMLoc E) {
362     auto Op = make_unique<SparcOperand>(k_Immediate);
363     Op->Imm.Val = Val;
364     Op->StartLoc = S;
365     Op->EndLoc = E;
366     return Op;
367   }
368 
369   static bool MorphToIntPairReg(SparcOperand &Op) {
370     unsigned Reg = Op.getReg();
371     assert(Op.Reg.Kind == rk_IntReg);
372     unsigned regIdx = 32;
373     if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
374       regIdx = Reg - Sparc::G0;
375     else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
376       regIdx = Reg - Sparc::O0 + 8;
377     else if (Reg >= Sparc::L0 && Reg <= Sparc::L7)
378       regIdx = Reg - Sparc::L0 + 16;
379     else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
380       regIdx = Reg - Sparc::I0 + 24;
381     if (regIdx % 2 || regIdx > 31)
382       return false;
383     Op.Reg.RegNum = IntPairRegs[regIdx / 2];
384     Op.Reg.Kind = rk_IntPairReg;
385     return true;
386   }
387 
388   static bool MorphToDoubleReg(SparcOperand &Op) {
389     unsigned Reg = Op.getReg();
390     assert(Op.Reg.Kind == rk_FloatReg);
391     unsigned regIdx = Reg - Sparc::F0;
392     if (regIdx % 2 || regIdx > 31)
393       return false;
394     Op.Reg.RegNum = DoubleRegs[regIdx / 2];
395     Op.Reg.Kind = rk_DoubleReg;
396     return true;
397   }
398 
399   static bool MorphToQuadReg(SparcOperand &Op) {
400     unsigned Reg = Op.getReg();
401     unsigned regIdx = 0;
402     switch (Op.Reg.Kind) {
403     default: llvm_unreachable("Unexpected register kind!");
404     case rk_FloatReg:
405       regIdx = Reg - Sparc::F0;
406       if (regIdx % 4 || regIdx > 31)
407         return false;
408       Reg = QuadFPRegs[regIdx / 4];
409       break;
410     case rk_DoubleReg:
411       regIdx =  Reg - Sparc::D0;
412       if (regIdx % 2 || regIdx > 31)
413         return false;
414       Reg = QuadFPRegs[regIdx / 2];
415       break;
416     }
417     Op.Reg.RegNum = Reg;
418     Op.Reg.Kind = rk_QuadReg;
419     return true;
420   }
421 
422   static bool MorphToCoprocPairReg(SparcOperand &Op) {
423     unsigned Reg = Op.getReg();
424     assert(Op.Reg.Kind == rk_CoprocReg);
425     unsigned regIdx = 32;
426     if (Reg >= Sparc::C0 && Reg <= Sparc::C31)
427       regIdx = Reg - Sparc::C0;
428     if (regIdx % 2 || regIdx > 31)
429       return false;
430     Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
431     Op.Reg.Kind = rk_CoprocPairReg;
432     return true;
433   }
434 
435   static std::unique_ptr<SparcOperand>
436   MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
437     unsigned offsetReg = Op->getReg();
438     Op->Kind = k_MemoryReg;
439     Op->Mem.Base = Base;
440     Op->Mem.OffsetReg = offsetReg;
441     Op->Mem.Off = nullptr;
442     return Op;
443   }
444 
445   static std::unique_ptr<SparcOperand>
446   CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
447     auto Op = make_unique<SparcOperand>(k_MemoryReg);
448     Op->Mem.Base = Base;
449     Op->Mem.OffsetReg = Sparc::G0;  // always 0
450     Op->Mem.Off = nullptr;
451     Op->StartLoc = S;
452     Op->EndLoc = E;
453     return Op;
454   }
455 
456   static std::unique_ptr<SparcOperand>
457   MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
458     const MCExpr *Imm  = Op->getImm();
459     Op->Kind = k_MemoryImm;
460     Op->Mem.Base = Base;
461     Op->Mem.OffsetReg = 0;
462     Op->Mem.Off = Imm;
463     return Op;
464   }
465 };
466 
467 } // end namespace
468 
469 void SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
470                                SmallVectorImpl<MCInst> &Instructions) {
471   MCOperand MCRegOp = Inst.getOperand(0);
472   MCOperand MCValOp = Inst.getOperand(1);
473   assert(MCRegOp.isReg());
474   assert(MCValOp.isImm() || MCValOp.isExpr());
475 
476   // the imm operand can be either an expression or an immediate.
477   bool IsImm = Inst.getOperand(1).isImm();
478   int64_t RawImmValue = IsImm ? MCValOp.getImm() : 0;
479 
480   // Allow either a signed or unsigned 32-bit immediate.
481   if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
482     Error(IDLoc, "set: argument must be between -2147483648 and 4294967295");
483     return;
484   }
485 
486   // If the value was expressed as a large unsigned number, that's ok.
487   // We want to see if it "looks like" a small signed number.
488   int32_t ImmValue = RawImmValue;
489   // For 'set' you can't use 'or' with a negative operand on V9 because
490   // that would splat the sign bit across the upper half of the destination
491   // register, whereas 'set' is defined to zero the high 32 bits.
492   bool IsEffectivelyImm13 =
493       IsImm && ((is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
494   const MCExpr *ValExpr;
495   if (IsImm)
496     ValExpr = MCConstantExpr::create(ImmValue, getContext());
497   else
498     ValExpr = MCValOp.getExpr();
499 
500   MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
501 
502   // If not just a signed imm13 value, then either we use a 'sethi' with a
503   // following 'or', or a 'sethi' by itself if there are no more 1 bits.
504   // In either case, start with the 'sethi'.
505   if (!IsEffectivelyImm13) {
506     MCInst TmpInst;
507     const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr);
508     TmpInst.setLoc(IDLoc);
509     TmpInst.setOpcode(SP::SETHIi);
510     TmpInst.addOperand(MCRegOp);
511     TmpInst.addOperand(MCOperand::createExpr(Expr));
512     Instructions.push_back(TmpInst);
513     PrevReg = MCRegOp;
514   }
515 
516   // The low bits require touching in 3 cases:
517   // * A non-immediate value will always require both instructions.
518   // * An effectively imm13 value needs only an 'or' instruction.
519   // * Otherwise, an immediate that is not effectively imm13 requires the
520   //   'or' only if bits remain after clearing the 22 bits that 'sethi' set.
521   // If the low bits are known zeros, there's nothing to do.
522   // In the second case, and only in that case, must we NOT clear
523   // bits of the immediate value via the %lo() assembler function.
524   // Note also, the 'or' instruction doesn't mind a large value in the case
525   // where the operand to 'set' was 0xFFFFFzzz - it does exactly what you mean.
526   if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
527     MCInst TmpInst;
528     const MCExpr *Expr;
529     if (IsEffectivelyImm13)
530       Expr = ValExpr;
531     else
532       Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
533     TmpInst.setLoc(IDLoc);
534     TmpInst.setOpcode(SP::ORri);
535     TmpInst.addOperand(MCRegOp);
536     TmpInst.addOperand(PrevReg);
537     TmpInst.addOperand(MCOperand::createExpr(Expr));
538     Instructions.push_back(TmpInst);
539   }
540 }
541 
542 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
543                                              OperandVector &Operands,
544                                              MCStreamer &Out,
545                                              uint64_t &ErrorInfo,
546                                              bool MatchingInlineAsm) {
547   MCInst Inst;
548   SmallVector<MCInst, 8> Instructions;
549   unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
550                                               MatchingInlineAsm);
551   switch (MatchResult) {
552   case Match_Success: {
553     switch (Inst.getOpcode()) {
554     default:
555       Inst.setLoc(IDLoc);
556       Instructions.push_back(Inst);
557       break;
558     case SP::SET:
559       expandSET(Inst, IDLoc, Instructions);
560       break;
561     }
562 
563     for (const MCInst &I : Instructions) {
564       Out.EmitInstruction(I, getSTI());
565     }
566     return false;
567   }
568 
569   case Match_MissingFeature:
570     return Error(IDLoc,
571                  "instruction requires a CPU feature not currently enabled");
572 
573   case Match_InvalidOperand: {
574     SMLoc ErrorLoc = IDLoc;
575     if (ErrorInfo != ~0ULL) {
576       if (ErrorInfo >= Operands.size())
577         return Error(IDLoc, "too few operands for instruction");
578 
579       ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
580       if (ErrorLoc == SMLoc())
581         ErrorLoc = IDLoc;
582     }
583 
584     return Error(ErrorLoc, "invalid operand for instruction");
585   }
586   case Match_MnemonicFail:
587     return Error(IDLoc, "invalid instruction mnemonic");
588   }
589   llvm_unreachable("Implement any new match types added!");
590 }
591 
592 bool SparcAsmParser::
593 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc)
594 {
595   const AsmToken &Tok = Parser.getTok();
596   StartLoc = Tok.getLoc();
597   EndLoc = Tok.getEndLoc();
598   RegNo = 0;
599   if (getLexer().getKind() != AsmToken::Percent)
600     return false;
601   Parser.Lex();
602   unsigned regKind = SparcOperand::rk_None;
603   if (matchRegisterName(Tok, RegNo, regKind)) {
604     Parser.Lex();
605     return false;
606   }
607 
608   return Error(StartLoc, "invalid register name");
609 }
610 
611 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
612                                  unsigned VariantID);
613 
614 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
615                                       StringRef Name, SMLoc NameLoc,
616                                       OperandVector &Operands) {
617 
618   // First operand in MCInst is instruction mnemonic.
619   Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
620 
621   // apply mnemonic aliases, if any, so that we can parse operands correctly.
622   applyMnemonicAliases(Name, getAvailableFeatures(), 0);
623 
624   if (getLexer().isNot(AsmToken::EndOfStatement)) {
625     // Read the first operand.
626     if (getLexer().is(AsmToken::Comma)) {
627       if (parseBranchModifiers(Operands) != MatchOperand_Success) {
628         SMLoc Loc = getLexer().getLoc();
629         Parser.eatToEndOfStatement();
630         return Error(Loc, "unexpected token");
631       }
632     }
633     if (parseOperand(Operands, Name) != MatchOperand_Success) {
634       SMLoc Loc = getLexer().getLoc();
635       Parser.eatToEndOfStatement();
636       return Error(Loc, "unexpected token");
637     }
638 
639     while (getLexer().is(AsmToken::Comma)) {
640       Parser.Lex(); // Eat the comma.
641       // Parse and remember the operand.
642       if (parseOperand(Operands, Name) != MatchOperand_Success) {
643         SMLoc Loc = getLexer().getLoc();
644         Parser.eatToEndOfStatement();
645         return Error(Loc, "unexpected token");
646       }
647     }
648   }
649   if (getLexer().isNot(AsmToken::EndOfStatement)) {
650     SMLoc Loc = getLexer().getLoc();
651     Parser.eatToEndOfStatement();
652     return Error(Loc, "unexpected token");
653   }
654   Parser.Lex(); // Consume the EndOfStatement.
655   return false;
656 }
657 
658 bool SparcAsmParser::
659 ParseDirective(AsmToken DirectiveID)
660 {
661   StringRef IDVal = DirectiveID.getString();
662 
663   if (IDVal == ".byte")
664     return parseDirectiveWord(1, DirectiveID.getLoc());
665 
666   if (IDVal == ".half")
667     return parseDirectiveWord(2, DirectiveID.getLoc());
668 
669   if (IDVal == ".word")
670     return parseDirectiveWord(4, DirectiveID.getLoc());
671 
672   if (IDVal == ".nword")
673     return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
674 
675   if (is64Bit() && IDVal == ".xword")
676     return parseDirectiveWord(8, DirectiveID.getLoc());
677 
678   if (IDVal == ".register") {
679     // For now, ignore .register directive.
680     Parser.eatToEndOfStatement();
681     return false;
682   }
683 
684   // Let the MC layer to handle other directives.
685   return true;
686 }
687 
688 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
689   if (getLexer().isNot(AsmToken::EndOfStatement)) {
690     for (;;) {
691       const MCExpr *Value;
692       if (getParser().parseExpression(Value))
693         return true;
694 
695       getParser().getStreamer().EmitValue(Value, Size);
696 
697       if (getLexer().is(AsmToken::EndOfStatement))
698         break;
699 
700       // FIXME: Improve diagnostic.
701       if (getLexer().isNot(AsmToken::Comma))
702         return Error(L, "unexpected token in directive");
703       Parser.Lex();
704     }
705   }
706   Parser.Lex();
707   return false;
708 }
709 
710 SparcAsmParser::OperandMatchResultTy
711 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
712 
713   SMLoc S, E;
714   unsigned BaseReg = 0;
715 
716   if (ParseRegister(BaseReg, S, E)) {
717     return MatchOperand_NoMatch;
718   }
719 
720   switch (getLexer().getKind()) {
721   default: return MatchOperand_NoMatch;
722 
723   case AsmToken::Comma:
724   case AsmToken::RBrac:
725   case AsmToken::EndOfStatement:
726     Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
727     return MatchOperand_Success;
728 
729   case AsmToken:: Plus:
730     Parser.Lex(); // Eat the '+'
731     break;
732   case AsmToken::Minus:
733     break;
734   }
735 
736   std::unique_ptr<SparcOperand> Offset;
737   OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
738   if (ResTy != MatchOperand_Success || !Offset)
739     return MatchOperand_NoMatch;
740 
741   Operands.push_back(
742       Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
743                       : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
744 
745   return MatchOperand_Success;
746 }
747 
748 SparcAsmParser::OperandMatchResultTy
749 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
750 
751   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
752 
753   // If there wasn't a custom match, try the generic matcher below. Otherwise,
754   // there was a match, but an error occurred, in which case, just return that
755   // the operand parsing failed.
756   if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
757     return ResTy;
758 
759   if (getLexer().is(AsmToken::LBrac)) {
760     // Memory operand
761     Operands.push_back(SparcOperand::CreateToken("[",
762                                                  Parser.getTok().getLoc()));
763     Parser.Lex(); // Eat the [
764 
765     if (Mnemonic == "cas" || Mnemonic == "casx") {
766       SMLoc S = Parser.getTok().getLoc();
767       if (getLexer().getKind() != AsmToken::Percent)
768         return MatchOperand_NoMatch;
769       Parser.Lex(); // eat %
770 
771       unsigned RegNo, RegKind;
772       if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
773         return MatchOperand_NoMatch;
774 
775       Parser.Lex(); // Eat the identifier token.
776       SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
777       Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
778       ResTy = MatchOperand_Success;
779     } else {
780       ResTy = parseMEMOperand(Operands);
781     }
782 
783     if (ResTy != MatchOperand_Success)
784       return ResTy;
785 
786     if (!getLexer().is(AsmToken::RBrac))
787       return MatchOperand_ParseFail;
788 
789     Operands.push_back(SparcOperand::CreateToken("]",
790                                                  Parser.getTok().getLoc()));
791     Parser.Lex(); // Eat the ]
792 
793     // Parse an optional address-space identifier after the address.
794     if (getLexer().is(AsmToken::Integer)) {
795       std::unique_ptr<SparcOperand> Op;
796       ResTy = parseSparcAsmOperand(Op, false);
797       if (ResTy != MatchOperand_Success || !Op)
798         return MatchOperand_ParseFail;
799       Operands.push_back(std::move(Op));
800     }
801     return MatchOperand_Success;
802   }
803 
804   std::unique_ptr<SparcOperand> Op;
805 
806   ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
807   if (ResTy != MatchOperand_Success || !Op)
808     return MatchOperand_ParseFail;
809 
810   // Push the parsed operand into the list of operands
811   Operands.push_back(std::move(Op));
812 
813   return MatchOperand_Success;
814 }
815 
816 SparcAsmParser::OperandMatchResultTy
817 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
818                                      bool isCall) {
819 
820   SMLoc S = Parser.getTok().getLoc();
821   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
822   const MCExpr *EVal;
823 
824   Op = nullptr;
825   switch (getLexer().getKind()) {
826   default:  break;
827 
828   case AsmToken::Percent:
829     Parser.Lex(); // Eat the '%'.
830     unsigned RegNo;
831     unsigned RegKind;
832     if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
833       StringRef name = Parser.getTok().getString();
834       Parser.Lex(); // Eat the identifier token.
835       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
836       switch (RegNo) {
837       default:
838         Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
839         break;
840       case Sparc::PSR:
841         Op = SparcOperand::CreateToken("%psr", S);
842         break;
843       case Sparc::FSR:
844         Op = SparcOperand::CreateToken("%fsr", S);
845         break;
846       case Sparc::FQ:
847         Op = SparcOperand::CreateToken("%fq", S);
848         break;
849       case Sparc::CPSR:
850         Op = SparcOperand::CreateToken("%csr", S);
851         break;
852       case Sparc::CPQ:
853         Op = SparcOperand::CreateToken("%cq", S);
854         break;
855       case Sparc::WIM:
856         Op = SparcOperand::CreateToken("%wim", S);
857         break;
858       case Sparc::TBR:
859         Op = SparcOperand::CreateToken("%tbr", S);
860         break;
861       case Sparc::ICC:
862         if (name == "xcc")
863           Op = SparcOperand::CreateToken("%xcc", S);
864         else
865           Op = SparcOperand::CreateToken("%icc", S);
866         break;
867       }
868       break;
869     }
870     if (matchSparcAsmModifiers(EVal, E)) {
871       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
872       Op = SparcOperand::CreateImm(EVal, S, E);
873     }
874     break;
875 
876   case AsmToken::Minus:
877   case AsmToken::Integer:
878   case AsmToken::LParen:
879   case AsmToken::Dot:
880     if (!getParser().parseExpression(EVal, E))
881       Op = SparcOperand::CreateImm(EVal, S, E);
882     break;
883 
884   case AsmToken::Identifier: {
885     StringRef Identifier;
886     if (!getParser().parseIdentifier(Identifier)) {
887       E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
888       MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
889 
890       const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
891                                                   getContext());
892       if (isCall &&
893           getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_)
894         Res = SparcMCExpr::create(SparcMCExpr::VK_Sparc_WPLT30, Res,
895                                   getContext());
896       Op = SparcOperand::CreateImm(Res, S, E);
897     }
898     break;
899   }
900   }
901   return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
902 }
903 
904 SparcAsmParser::OperandMatchResultTy
905 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
906 
907   // parse (,a|,pn|,pt)+
908 
909   while (getLexer().is(AsmToken::Comma)) {
910 
911     Parser.Lex(); // Eat the comma
912 
913     if (!getLexer().is(AsmToken::Identifier))
914       return MatchOperand_ParseFail;
915     StringRef modName = Parser.getTok().getString();
916     if (modName == "a" || modName == "pn" || modName == "pt") {
917       Operands.push_back(SparcOperand::CreateToken(modName,
918                                                    Parser.getTok().getLoc()));
919       Parser.Lex(); // eat the identifier.
920     }
921   }
922   return MatchOperand_Success;
923 }
924 
925 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok,
926                                        unsigned &RegNo,
927                                        unsigned &RegKind)
928 {
929   int64_t intVal = 0;
930   RegNo = 0;
931   RegKind = SparcOperand::rk_None;
932   if (Tok.is(AsmToken::Identifier)) {
933     StringRef name = Tok.getString();
934 
935     // %fp
936     if (name.equals("fp")) {
937       RegNo = Sparc::I6;
938       RegKind = SparcOperand::rk_IntReg;
939       return true;
940     }
941     // %sp
942     if (name.equals("sp")) {
943       RegNo = Sparc::O6;
944       RegKind = SparcOperand::rk_IntReg;
945       return true;
946     }
947 
948     if (name.equals("y")) {
949       RegNo = Sparc::Y;
950       RegKind = SparcOperand::rk_Special;
951       return true;
952     }
953 
954     if (name.substr(0, 3).equals_lower("asr")
955         && !name.substr(3).getAsInteger(10, intVal)
956         && intVal > 0 && intVal < 32) {
957       RegNo = ASRRegs[intVal];
958       RegKind = SparcOperand::rk_Special;
959       return true;
960     }
961 
962     // %fprs is an alias of %asr6.
963     if (name.equals("fprs")) {
964       RegNo = ASRRegs[6];
965       RegKind = SparcOperand::rk_Special;
966       return true;
967     }
968 
969     if (name.equals("icc")) {
970       RegNo = Sparc::ICC;
971       RegKind = SparcOperand::rk_Special;
972       return true;
973     }
974 
975     if (name.equals("psr")) {
976       RegNo = Sparc::PSR;
977       RegKind = SparcOperand::rk_Special;
978       return true;
979     }
980 
981     if (name.equals("fsr")) {
982       RegNo = Sparc::FSR;
983       RegKind = SparcOperand::rk_Special;
984       return true;
985     }
986 
987     if (name.equals("fq")) {
988       RegNo = Sparc::FQ;
989       RegKind = SparcOperand::rk_Special;
990       return true;
991     }
992 
993     if (name.equals("csr")) {
994       RegNo = Sparc::CPSR;
995       RegKind = SparcOperand::rk_Special;
996       return true;
997     }
998 
999     if (name.equals("cq")) {
1000       RegNo = Sparc::CPQ;
1001       RegKind = SparcOperand::rk_Special;
1002       return true;
1003     }
1004 
1005     if (name.equals("wim")) {
1006       RegNo = Sparc::WIM;
1007       RegKind = SparcOperand::rk_Special;
1008       return true;
1009     }
1010 
1011     if (name.equals("tbr")) {
1012       RegNo = Sparc::TBR;
1013       RegKind = SparcOperand::rk_Special;
1014       return true;
1015     }
1016 
1017     if (name.equals("xcc")) {
1018       // FIXME:: check 64bit.
1019       RegNo = Sparc::ICC;
1020       RegKind = SparcOperand::rk_Special;
1021       return true;
1022     }
1023 
1024     // %fcc0 - %fcc3
1025     if (name.substr(0, 3).equals_lower("fcc")
1026         && !name.substr(3).getAsInteger(10, intVal)
1027         && intVal < 4) {
1028       // FIXME: check 64bit and  handle %fcc1 - %fcc3
1029       RegNo = Sparc::FCC0 + intVal;
1030       RegKind = SparcOperand::rk_Special;
1031       return true;
1032     }
1033 
1034     // %g0 - %g7
1035     if (name.substr(0, 1).equals_lower("g")
1036         && !name.substr(1).getAsInteger(10, intVal)
1037         && intVal < 8) {
1038       RegNo = IntRegs[intVal];
1039       RegKind = SparcOperand::rk_IntReg;
1040       return true;
1041     }
1042     // %o0 - %o7
1043     if (name.substr(0, 1).equals_lower("o")
1044         && !name.substr(1).getAsInteger(10, intVal)
1045         && intVal < 8) {
1046       RegNo = IntRegs[8 + intVal];
1047       RegKind = SparcOperand::rk_IntReg;
1048       return true;
1049     }
1050     if (name.substr(0, 1).equals_lower("l")
1051         && !name.substr(1).getAsInteger(10, intVal)
1052         && intVal < 8) {
1053       RegNo = IntRegs[16 + intVal];
1054       RegKind = SparcOperand::rk_IntReg;
1055       return true;
1056     }
1057     if (name.substr(0, 1).equals_lower("i")
1058         && !name.substr(1).getAsInteger(10, intVal)
1059         && intVal < 8) {
1060       RegNo = IntRegs[24 + intVal];
1061       RegKind = SparcOperand::rk_IntReg;
1062       return true;
1063     }
1064     // %f0 - %f31
1065     if (name.substr(0, 1).equals_lower("f")
1066         && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
1067       RegNo = FloatRegs[intVal];
1068       RegKind = SparcOperand::rk_FloatReg;
1069       return true;
1070     }
1071     // %f32 - %f62
1072     if (name.substr(0, 1).equals_lower("f")
1073         && !name.substr(1, 2).getAsInteger(10, intVal)
1074         && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
1075       // FIXME: Check V9
1076       RegNo = DoubleRegs[intVal/2];
1077       RegKind = SparcOperand::rk_DoubleReg;
1078       return true;
1079     }
1080 
1081     // %r0 - %r31
1082     if (name.substr(0, 1).equals_lower("r")
1083         && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
1084       RegNo = IntRegs[intVal];
1085       RegKind = SparcOperand::rk_IntReg;
1086       return true;
1087     }
1088 
1089     // %c0 - %c31
1090     if (name.substr(0, 1).equals_lower("c")
1091         && !name.substr(1).getAsInteger(10, intVal)
1092         && intVal < 32) {
1093       RegNo = CoprocRegs[intVal];
1094       RegKind = SparcOperand::rk_CoprocReg;
1095       return true;
1096     }
1097 
1098     if (name.equals("tpc")) {
1099       RegNo = Sparc::TPC;
1100       RegKind = SparcOperand::rk_Special;
1101       return true;
1102     }
1103     if (name.equals("tnpc")) {
1104       RegNo = Sparc::TNPC;
1105       RegKind = SparcOperand::rk_Special;
1106       return true;
1107     }
1108     if (name.equals("tstate")) {
1109       RegNo = Sparc::TSTATE;
1110       RegKind = SparcOperand::rk_Special;
1111       return true;
1112     }
1113     if (name.equals("tt")) {
1114       RegNo = Sparc::TT;
1115       RegKind = SparcOperand::rk_Special;
1116       return true;
1117     }
1118     if (name.equals("tick")) {
1119       RegNo = Sparc::TICK;
1120       RegKind = SparcOperand::rk_Special;
1121       return true;
1122     }
1123     if (name.equals("tba")) {
1124       RegNo = Sparc::TBA;
1125       RegKind = SparcOperand::rk_Special;
1126       return true;
1127     }
1128     if (name.equals("pstate")) {
1129       RegNo = Sparc::PSTATE;
1130       RegKind = SparcOperand::rk_Special;
1131       return true;
1132     }
1133     if (name.equals("tl")) {
1134       RegNo = Sparc::TL;
1135       RegKind = SparcOperand::rk_Special;
1136       return true;
1137     }
1138     if (name.equals("pil")) {
1139       RegNo = Sparc::PIL;
1140       RegKind = SparcOperand::rk_Special;
1141       return true;
1142     }
1143     if (name.equals("cwp")) {
1144       RegNo = Sparc::CWP;
1145       RegKind = SparcOperand::rk_Special;
1146       return true;
1147     }
1148     if (name.equals("cansave")) {
1149       RegNo = Sparc::CANSAVE;
1150       RegKind = SparcOperand::rk_Special;
1151       return true;
1152     }
1153     if (name.equals("canrestore")) {
1154       RegNo = Sparc::CANRESTORE;
1155       RegKind = SparcOperand::rk_Special;
1156       return true;
1157     }
1158     if (name.equals("cleanwin")) {
1159       RegNo = Sparc::CLEANWIN;
1160       RegKind = SparcOperand::rk_Special;
1161       return true;
1162     }
1163     if (name.equals("otherwin")) {
1164       RegNo = Sparc::OTHERWIN;
1165       RegKind = SparcOperand::rk_Special;
1166       return true;
1167     }
1168     if (name.equals("wstate")) {
1169       RegNo = Sparc::WSTATE;
1170       RegKind = SparcOperand::rk_Special;
1171       return true;
1172     }
1173   }
1174   return false;
1175 }
1176 
1177 // Determine if an expression contains a reference to the symbol
1178 // "_GLOBAL_OFFSET_TABLE_".
1179 static bool hasGOTReference(const MCExpr *Expr) {
1180   switch (Expr->getKind()) {
1181   case MCExpr::Target:
1182     if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1183       return hasGOTReference(SE->getSubExpr());
1184     break;
1185 
1186   case MCExpr::Constant:
1187     break;
1188 
1189   case MCExpr::Binary: {
1190     const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
1191     return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
1192   }
1193 
1194   case MCExpr::SymbolRef: {
1195     const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
1196     return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
1197   }
1198 
1199   case MCExpr::Unary:
1200     return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
1201   }
1202   return false;
1203 }
1204 
1205 const SparcMCExpr *
1206 SparcAsmParser::adjustPICRelocation(SparcMCExpr::VariantKind VK,
1207                                     const MCExpr *subExpr)
1208 {
1209   // When in PIC mode, "%lo(...)" and "%hi(...)" behave differently.
1210   // If the expression refers contains _GLOBAL_OFFSETE_TABLE, it is
1211   // actually a %pc10 or %pc22 relocation. Otherwise, they are interpreted
1212   // as %got10 or %got22 relocation.
1213 
1214   if (getContext().getObjectFileInfo()->getRelocM() == Reloc::PIC_) {
1215     switch(VK) {
1216     default: break;
1217     case SparcMCExpr::VK_Sparc_LO:
1218       VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC10
1219                                      : SparcMCExpr::VK_Sparc_GOT10);
1220       break;
1221     case SparcMCExpr::VK_Sparc_HI:
1222       VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC22
1223                                      : SparcMCExpr::VK_Sparc_GOT22);
1224       break;
1225     }
1226   }
1227 
1228   return SparcMCExpr::create(VK, subExpr, getContext());
1229 }
1230 
1231 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
1232                                             SMLoc &EndLoc)
1233 {
1234   AsmToken Tok = Parser.getTok();
1235   if (!Tok.is(AsmToken::Identifier))
1236     return false;
1237 
1238   StringRef name = Tok.getString();
1239 
1240   SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
1241 
1242   if (VK == SparcMCExpr::VK_Sparc_None)
1243     return false;
1244 
1245   Parser.Lex(); // Eat the identifier.
1246   if (Parser.getTok().getKind() != AsmToken::LParen)
1247     return false;
1248 
1249   Parser.Lex(); // Eat the LParen token.
1250   const MCExpr *subExpr;
1251   if (Parser.parseParenExpression(subExpr, EndLoc))
1252     return false;
1253 
1254   EVal = adjustPICRelocation(VK, subExpr);
1255   return true;
1256 }
1257 
1258 extern "C" void LLVMInitializeSparcAsmParser() {
1259   RegisterMCAsmParser<SparcAsmParser> A(TheSparcTarget);
1260   RegisterMCAsmParser<SparcAsmParser> B(TheSparcV9Target);
1261   RegisterMCAsmParser<SparcAsmParser> C(TheSparcelTarget);
1262 }
1263 
1264 #define GET_REGISTER_MATCHER
1265 #define GET_MATCHER_IMPLEMENTATION
1266 #include "SparcGenAsmMatcher.inc"
1267 
1268 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1269                                                     unsigned Kind) {
1270   SparcOperand &Op = (SparcOperand &)GOp;
1271   if (Op.isFloatOrDoubleReg()) {
1272     switch (Kind) {
1273     default: break;
1274     case MCK_DFPRegs:
1275       if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1276         return MCTargetAsmParser::Match_Success;
1277       break;
1278     case MCK_QFPRegs:
1279       if (SparcOperand::MorphToQuadReg(Op))
1280         return MCTargetAsmParser::Match_Success;
1281       break;
1282     }
1283   }
1284   if (Op.isIntReg() && Kind == MCK_IntPair) {
1285     if (SparcOperand::MorphToIntPairReg(Op))
1286       return MCTargetAsmParser::Match_Success;
1287   }
1288   if (Op.isCoprocReg() && Kind == MCK_CoprocPair) {
1289      if (SparcOperand::MorphToCoprocPairReg(Op))
1290        return MCTargetAsmParser::Match_Success;
1291    }
1292   return Match_InvalidOperand;
1293 }
1294