1 //===- SPIRVTargetMachine.cpp - Define TargetMachine for SPIR-V -*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about SPIR-V target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "SPIRVTargetMachine.h"
14 #include "SPIRV.h"
15 #include "SPIRVCallLowering.h"
16 #include "SPIRVGlobalRegistry.h"
17 #include "SPIRVLegalizerInfo.h"
18 #include "SPIRVTargetObjectFile.h"
19 #include "SPIRVTargetTransformInfo.h"
20 #include "TargetInfo/SPIRVTargetInfo.h"
21 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
22 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
23 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
24 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/CodeGen/TargetPassConfig.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/InitializePasses.h"
30 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Pass.h"
32 #include "llvm/Target/TargetOptions.h"
33 
34 using namespace llvm;
35 
36 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSPIRVTarget() {
37   // Register the target.
38   RegisterTargetMachine<SPIRVTargetMachine> X(getTheSPIRV32Target());
39   RegisterTargetMachine<SPIRVTargetMachine> Y(getTheSPIRV64Target());
40 
41   PassRegistry &PR = *PassRegistry::getPassRegistry();
42   initializeGlobalISel(PR);
43   initializeSPIRVModuleAnalysisPass(PR);
44 }
45 
46 static std::string computeDataLayout(const Triple &TT) {
47   std::string DataLayout = "e-m:e";
48 
49   const auto Arch = TT.getArch();
50   if (Arch == Triple::spirv32)
51     DataLayout += "-p:32:32";
52   else if (Arch == Triple::spirv64)
53     DataLayout += "-p:64:64";
54   return DataLayout;
55 }
56 
57 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
58   if (!RM)
59     return Reloc::PIC_;
60   return *RM;
61 }
62 
63 // Pin SPIRVTargetObjectFile's vtables to this file.
64 SPIRVTargetObjectFile::~SPIRVTargetObjectFile() {}
65 
66 SPIRVTargetMachine::SPIRVTargetMachine(const Target &T, const Triple &TT,
67                                        StringRef CPU, StringRef FS,
68                                        const TargetOptions &Options,
69                                        Optional<Reloc::Model> RM,
70                                        Optional<CodeModel::Model> CM,
71                                        CodeGenOpt::Level OL, bool JIT)
72     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
73                         getEffectiveRelocModel(RM),
74                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
75       TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
76       Subtarget(TT, CPU.str(), FS.str(), *this) {
77   initAsmInfo();
78   setGlobalISel(true);
79   setFastISel(false);
80   setO0WantsFastISel(false);
81   setRequiresStructuredCFG(false);
82 }
83 
84 namespace {
85 // SPIR-V Code Generator Pass Configuration Options.
86 class SPIRVPassConfig : public TargetPassConfig {
87 public:
88   SPIRVPassConfig(SPIRVTargetMachine &TM, PassManagerBase &PM)
89       : TargetPassConfig(TM, PM) {}
90 
91   SPIRVTargetMachine &getSPIRVTargetMachine() const {
92     return getTM<SPIRVTargetMachine>();
93   }
94   void addIRPasses() override;
95   void addISelPrepare() override;
96 
97   bool addIRTranslator() override;
98   bool addLegalizeMachineIR() override;
99   bool addRegBankSelect() override;
100   bool addGlobalInstructionSelect() override;
101 
102   FunctionPass *createTargetRegisterAllocator(bool) override;
103   void addFastRegAlloc() override {}
104   void addOptimizedRegAlloc() override {}
105 
106   void addPostRegAlloc() override;
107 };
108 } // namespace
109 
110 // We do not use physical registers, and maintain virtual registers throughout
111 // the entire pipeline, so return nullptr to disable register allocation.
112 FunctionPass *SPIRVPassConfig::createTargetRegisterAllocator(bool) {
113   return nullptr;
114 }
115 
116 // Disable passes that break from assuming no virtual registers exist.
117 void SPIRVPassConfig::addPostRegAlloc() {
118   // Do not work with vregs instead of physical regs.
119   disablePass(&MachineCopyPropagationID);
120   disablePass(&PostRAMachineSinkingID);
121   disablePass(&PostRASchedulerID);
122   disablePass(&FuncletLayoutID);
123   disablePass(&StackMapLivenessID);
124   disablePass(&PatchableFunctionID);
125   disablePass(&ShrinkWrapID);
126   disablePass(&LiveDebugValuesID);
127 
128   // Do not work with OpPhi.
129   disablePass(&BranchFolderPassID);
130   disablePass(&MachineBlockPlacementID);
131 
132   TargetPassConfig::addPostRegAlloc();
133 }
134 
135 TargetTransformInfo
136 SPIRVTargetMachine::getTargetTransformInfo(const Function &F) const {
137   return TargetTransformInfo(SPIRVTTIImpl(this, F));
138 }
139 
140 TargetPassConfig *SPIRVTargetMachine::createPassConfig(PassManagerBase &PM) {
141   return new SPIRVPassConfig(*this, PM);
142 }
143 
144 void SPIRVPassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); }
145 
146 void SPIRVPassConfig::addISelPrepare() { TargetPassConfig::addISelPrepare(); }
147 
148 bool SPIRVPassConfig::addIRTranslator() {
149   addPass(new IRTranslator(getOptLevel()));
150   return false;
151 }
152 
153 // Use a default legalizer.
154 bool SPIRVPassConfig::addLegalizeMachineIR() {
155   addPass(new Legalizer());
156   return false;
157 }
158 
159 // Do not add a RegBankSelect pass, as we only ever need virtual registers.
160 bool SPIRVPassConfig::addRegBankSelect() {
161   disablePass(&RegBankSelect::ID);
162   return false;
163 }
164 
165 namespace {
166 // A custom subclass of InstructionSelect, which is mostly the same except from
167 // not requiring RegBankSelect to occur previously.
168 class SPIRVInstructionSelect : public InstructionSelect {
169   // We don't use register banks, so unset the requirement for them
170   MachineFunctionProperties getRequiredProperties() const override {
171     return InstructionSelect::getRequiredProperties().reset(
172         MachineFunctionProperties::Property::RegBankSelected);
173   }
174 };
175 } // namespace
176 
177 bool SPIRVPassConfig::addGlobalInstructionSelect() {
178   addPass(new SPIRVInstructionSelect());
179   return false;
180 }
181