1 //===- RISCVTargetTransformInfo.h - RISC-V specific TTI ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file defines a TargetTransformInfo::Concept conforming object specific 10 /// to the RISC-V target machine. It uses the target's detailed information to 11 /// provide more precise answers to certain TTI queries, while letting the 12 /// target independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H 17 #define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H 18 19 #include "RISCVSubtarget.h" 20 #include "RISCVTargetMachine.h" 21 #include "llvm/Analysis/TargetTransformInfo.h" 22 #include "llvm/CodeGen/BasicTTIImpl.h" 23 #include "llvm/IR/Function.h" 24 25 namespace llvm { 26 27 class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> { 28 using BaseT = BasicTTIImplBase<RISCVTTIImpl>; 29 using TTI = TargetTransformInfo; 30 31 friend BaseT; 32 33 const RISCVSubtarget *ST; 34 const RISCVTargetLowering *TLI; 35 36 const RISCVSubtarget *getST() const { return ST; } 37 const RISCVTargetLowering *getTLI() const { return TLI; } 38 39 public: 40 explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F) 41 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 42 TLI(ST->getTargetLowering()) {} 43 44 int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind); 45 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, 46 Type *Ty, TTI::TargetCostKind CostKind, 47 Instruction *Inst = nullptr); 48 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 49 Type *Ty, TTI::TargetCostKind CostKind); 50 51 bool shouldExpandReduction(const IntrinsicInst *II) const; 52 bool supportsScalableVectors() const { return ST->hasStdExtV(); } 53 Optional<unsigned> getMaxVScale() const; 54 55 unsigned getRegisterBitWidth(bool Vector) const { 56 if (Vector) { 57 if (ST->hasStdExtV()) 58 return ST->getMinRVVVectorSizeInBits(); 59 return 0; 60 } 61 return ST->getXLen(); 62 } 63 64 bool isLegalElementTypeForRVV(Type *ScalarTy) { 65 if (ScalarTy->isPointerTy()) 66 return true; 67 68 if (ScalarTy->isIntegerTy(8) || ScalarTy->isIntegerTy(16) || 69 ScalarTy->isIntegerTy(32) || ScalarTy->isIntegerTy(64)) 70 return true; 71 72 if (ScalarTy->isHalfTy()) 73 return ST->hasStdExtZfh(); 74 if (ScalarTy->isFloatTy()) 75 return ST->hasStdExtF(); 76 if (ScalarTy->isDoubleTy()) 77 return ST->hasStdExtD(); 78 79 return false; 80 } 81 82 bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) { 83 if (!ST->hasStdExtV()) 84 return false; 85 86 // Only support fixed vectors if we know the minimum vector size. 87 if (isa<FixedVectorType>(DataType) && ST->getMinRVVVectorSizeInBits() == 0) 88 return false; 89 90 return isLegalElementTypeForRVV(DataType->getScalarType()); 91 } 92 93 bool isLegalMaskedLoad(Type *DataType, Align Alignment) { 94 return isLegalMaskedLoadStore(DataType, Alignment); 95 } 96 bool isLegalMaskedStore(Type *DataType, Align Alignment) { 97 return isLegalMaskedLoadStore(DataType, Alignment); 98 } 99 100 bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment) { 101 if (!ST->hasStdExtV()) 102 return false; 103 104 // Only support fixed vectors if we know the minimum vector size. 105 if (isa<FixedVectorType>(DataType) && ST->getMinRVVVectorSizeInBits() == 0) 106 return false; 107 108 return isLegalElementTypeForRVV(DataType->getScalarType()); 109 } 110 111 bool isLegalMaskedGather(Type *DataType, Align Alignment) { 112 return isLegalMaskedGatherScatter(DataType, Alignment); 113 } 114 bool isLegalMaskedScatter(Type *DataType, Align Alignment) { 115 return isLegalMaskedGatherScatter(DataType, Alignment); 116 } 117 }; 118 119 } // end namespace llvm 120 121 #endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H 122