1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "RISCVTargetTransformInfo.h"
10 #include "MCTargetDesc/RISCVMatInt.h"
11 #include "llvm/Analysis/TargetTransformInfo.h"
12 #include "llvm/CodeGen/BasicTTIImpl.h"
13 #include "llvm/CodeGen/TargetLowering.h"
14 #include <cmath>
15 using namespace llvm;
16 
17 #define DEBUG_TYPE "riscvtti"
18 
19 static cl::opt<unsigned> RVVRegisterWidthLMUL(
20     "riscv-v-register-bit-width-lmul",
21     cl::desc(
22         "The LMUL to use for getRegisterBitWidth queries. Affects LMUL used "
23         "by autovectorized code. Fractional LMULs are not supported."),
24     cl::init(1), cl::Hidden);
25 
26 InstructionCost RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty,
27                                             TTI::TargetCostKind CostKind) {
28   assert(Ty->isIntegerTy() &&
29          "getIntImmCost can only estimate cost of materialising integers");
30 
31   // We have a Zero register, so 0 is always free.
32   if (Imm == 0)
33     return TTI::TCC_Free;
34 
35   // Otherwise, we check how many instructions it will take to materialise.
36   const DataLayout &DL = getDataLayout();
37   return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty),
38                                     getST()->getFeatureBits());
39 }
40 
41 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
42                                                 const APInt &Imm, Type *Ty,
43                                                 TTI::TargetCostKind CostKind,
44                                                 Instruction *Inst) {
45   assert(Ty->isIntegerTy() &&
46          "getIntImmCost can only estimate cost of materialising integers");
47 
48   // We have a Zero register, so 0 is always free.
49   if (Imm == 0)
50     return TTI::TCC_Free;
51 
52   // Some instructions in RISC-V can take a 12-bit immediate. Some of these are
53   // commutative, in others the immediate comes from a specific argument index.
54   bool Takes12BitImm = false;
55   unsigned ImmArgIdx = ~0U;
56 
57   switch (Opcode) {
58   case Instruction::GetElementPtr:
59     // Never hoist any arguments to a GetElementPtr. CodeGenPrepare will
60     // split up large offsets in GEP into better parts than ConstantHoisting
61     // can.
62     return TTI::TCC_Free;
63   case Instruction::And:
64     // zext.h
65     if (Imm == UINT64_C(0xffff) && ST->hasStdExtZbb())
66       return TTI::TCC_Free;
67     // zext.w
68     if (Imm == UINT64_C(0xffffffff) && ST->hasStdExtZbb())
69       return TTI::TCC_Free;
70     LLVM_FALLTHROUGH;
71   case Instruction::Add:
72   case Instruction::Or:
73   case Instruction::Xor:
74   case Instruction::Mul:
75     Takes12BitImm = true;
76     break;
77   case Instruction::Sub:
78   case Instruction::Shl:
79   case Instruction::LShr:
80   case Instruction::AShr:
81     Takes12BitImm = true;
82     ImmArgIdx = 1;
83     break;
84   default:
85     break;
86   }
87 
88   if (Takes12BitImm) {
89     // Check immediate is the correct argument...
90     if (Instruction::isCommutative(Opcode) || Idx == ImmArgIdx) {
91       // ... and fits into the 12-bit immediate.
92       if (Imm.getMinSignedBits() <= 64 &&
93           getTLI()->isLegalAddImmediate(Imm.getSExtValue())) {
94         return TTI::TCC_Free;
95       }
96     }
97 
98     // Otherwise, use the full materialisation cost.
99     return getIntImmCost(Imm, Ty, CostKind);
100   }
101 
102   // By default, prevent hoisting.
103   return TTI::TCC_Free;
104 }
105 
106 InstructionCost
107 RISCVTTIImpl::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
108                                   const APInt &Imm, Type *Ty,
109                                   TTI::TargetCostKind CostKind) {
110   // Prevent hoisting in unknown cases.
111   return TTI::TCC_Free;
112 }
113 
114 TargetTransformInfo::PopcntSupportKind
115 RISCVTTIImpl::getPopcntSupport(unsigned TyWidth) {
116   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
117   return ST->hasStdExtZbb() ? TTI::PSK_FastHardware : TTI::PSK_Software;
118 }
119 
120 bool RISCVTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
121   // Currently, the ExpandReductions pass can't expand scalable-vector
122   // reductions, but we still request expansion as RVV doesn't support certain
123   // reductions and the SelectionDAG can't legalize them either.
124   switch (II->getIntrinsicID()) {
125   default:
126     return false;
127   // These reductions have no equivalent in RVV
128   case Intrinsic::vector_reduce_mul:
129   case Intrinsic::vector_reduce_fmul:
130     return true;
131   }
132 }
133 
134 Optional<unsigned> RISCVTTIImpl::getMaxVScale() const {
135   // There is no assumption of the maximum vector length in V specification.
136   // We use the value specified by users as the maximum vector length.
137   // This function will use the assumed maximum vector length to get the
138   // maximum vscale for LoopVectorizer.
139   // If users do not specify the maximum vector length, we have no way to
140   // know whether the LoopVectorizer is safe to do or not.
141   // We only consider to use single vector register (LMUL = 1) to vectorize.
142   unsigned MaxVectorSizeInBits = ST->getMaxRVVVectorSizeInBits();
143   if (ST->hasVInstructions() && MaxVectorSizeInBits != 0)
144     return MaxVectorSizeInBits / RISCV::RVVBitsPerBlock;
145   return BaseT::getMaxVScale();
146 }
147 
148 TypeSize
149 RISCVTTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
150   unsigned LMUL = PowerOf2Floor(
151       std::max<unsigned>(std::min<unsigned>(RVVRegisterWidthLMUL, 8), 1));
152   switch (K) {
153   case TargetTransformInfo::RGK_Scalar:
154     return TypeSize::getFixed(ST->getXLen());
155   case TargetTransformInfo::RGK_FixedWidthVector:
156     return TypeSize::getFixed(
157         ST->hasVInstructions() ? LMUL * ST->getMinRVVVectorSizeInBits() : 0);
158   case TargetTransformInfo::RGK_ScalableVector:
159     return TypeSize::getScalable(
160         ST->hasVInstructions() ? LMUL * RISCV::RVVBitsPerBlock : 0);
161   }
162 
163   llvm_unreachable("Unsupported register kind");
164 }
165 
166 InstructionCost RISCVTTIImpl::getSpliceCost(VectorType *Tp, int Index) {
167   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Tp);
168 
169   unsigned Cost = 2; // vslidedown+vslideup.
170   // TODO: LMUL should increase cost.
171   // TODO: Multiplying by LT.first implies this legalizes into multiple copies
172   // of similar code, but I think we expand through memory.
173   return Cost * LT.first;
174 }
175 
176 InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
177                                              VectorType *Tp, ArrayRef<int> Mask,
178                                              int Index, VectorType *SubTp,
179                                              ArrayRef<Value *> Args) {
180   if (Kind == TTI::SK_Splice && isa<ScalableVectorType>(Tp))
181     return getSpliceCost(Tp, Index);
182   return BaseT::getShuffleCost(Kind, Tp, Mask, Index, SubTp);
183 }
184 
185 InstructionCost
186 RISCVTTIImpl::getMaskedMemoryOpCost(unsigned Opcode, Type *Src, Align Alignment,
187                                     unsigned AddressSpace,
188                                     TTI::TargetCostKind CostKind) {
189   if (!isa<ScalableVectorType>(Src))
190     return BaseT::getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
191                                         CostKind);
192 
193   return getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
194 }
195 
196 InstructionCost RISCVTTIImpl::getGatherScatterOpCost(
197     unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
198     Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) {
199   if (CostKind != TTI::TCK_RecipThroughput)
200     return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
201                                          Alignment, CostKind, I);
202 
203   if ((Opcode == Instruction::Load &&
204        !isLegalMaskedGather(DataTy, Align(Alignment))) ||
205       (Opcode == Instruction::Store &&
206        !isLegalMaskedScatter(DataTy, Align(Alignment))))
207     return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
208                                          Alignment, CostKind, I);
209 
210   // FIXME: Only supporting fixed vectors for now.
211   if (!isa<FixedVectorType>(DataTy))
212     return BaseT::getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
213                                          Alignment, CostKind, I);
214 
215   auto *VTy = cast<FixedVectorType>(DataTy);
216   unsigned NumLoads = VTy->getNumElements();
217   InstructionCost MemOpCost =
218       getMemoryOpCost(Opcode, VTy->getElementType(), Alignment, 0, CostKind, I);
219   return NumLoads * MemOpCost;
220 }
221 
222 InstructionCost RISCVTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst,
223                                                Type *Src,
224                                                TTI::CastContextHint CCH,
225                                                TTI::TargetCostKind CostKind,
226                                                const Instruction *I) {
227   if (isa<VectorType>(Dst) && isa<VectorType>(Src)) {
228     // FIXME: Need to compute legalizing cost for illegal types.
229     if (!isTypeLegal(Src) || !isTypeLegal(Dst))
230       return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
231 
232     // Skip if element size of Dst or Src is bigger than ELEN.
233     if (Src->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors() ||
234         Dst->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
235       return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
236 
237     int ISD = TLI->InstructionOpcodeToISD(Opcode);
238     assert(ISD && "Invalid opcode");
239 
240     // FIXME: Need to consider vsetvli and lmul.
241     int PowDiff = (int)Log2_32(Dst->getScalarSizeInBits()) -
242                   (int)Log2_32(Src->getScalarSizeInBits());
243     switch (ISD) {
244     case ISD::SIGN_EXTEND:
245     case ISD::ZERO_EXTEND:
246       return 1;
247     case ISD::TRUNCATE:
248     case ISD::FP_EXTEND:
249     case ISD::FP_ROUND:
250       // Counts of narrow/widen instructions.
251       return std::abs(PowDiff);
252     case ISD::FP_TO_SINT:
253     case ISD::FP_TO_UINT:
254     case ISD::SINT_TO_FP:
255     case ISD::UINT_TO_FP:
256       if (std::abs(PowDiff) <= 1)
257         return 1;
258       // Backend could lower (v[sz]ext i8 to double) to vfcvt(v[sz]ext.f8 i8),
259       // so it only need two conversion.
260       if (Src->isIntOrIntVectorTy())
261         return 2;
262       // Counts of narrow/widen instructions.
263       return std::abs(PowDiff);
264     }
265   }
266   return BaseT::getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
267 }
268 
269 InstructionCost
270 RISCVTTIImpl::getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
271                                      bool IsUnsigned,
272                                      TTI::TargetCostKind CostKind) {
273   // FIXME: Only supporting fixed vectors for now.
274   if (!isa<FixedVectorType>(Ty))
275     return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
276 
277   if (!ST->useRVVForFixedLengthVectors())
278     return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
279 
280   // Skip if scalar size of Ty is bigger than ELEN.
281   if (Ty->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
282     return BaseT::getMinMaxReductionCost(Ty, CondTy, IsUnsigned, CostKind);
283 
284   // IR Reduction is composed by two vmv and one rvv reduction instruction.
285   InstructionCost BaseCost = 2;
286   unsigned VL = cast<FixedVectorType>(Ty)->getNumElements();
287   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
288   return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
289 }
290 
291 InstructionCost
292 RISCVTTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *VTy,
293                                          Optional<FastMathFlags> FMF,
294                                          TTI::TargetCostKind CostKind) {
295   // FIXME: Only supporting fixed vectors for now.
296   if (!isa<FixedVectorType>(VTy))
297     return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
298 
299   // FIXME: Do not support i1 and/or reduction now.
300   if (VTy->getElementType()->isIntegerTy(1))
301     return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
302 
303   if (!ST->useRVVForFixedLengthVectors())
304     return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
305 
306   // Skip if scalar size of VTy is bigger than ELEN.
307   if (VTy->getScalarSizeInBits() > ST->getMaxELENForFixedLengthVectors())
308     return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
309 
310   int ISD = TLI->InstructionOpcodeToISD(Opcode);
311   assert(ISD && "Invalid opcode");
312 
313   if (ISD != ISD::ADD && ISD != ISD::OR && ISD != ISD::XOR && ISD != ISD::AND &&
314       ISD != ISD::FADD)
315     return BaseT::getArithmeticReductionCost(Opcode, VTy, FMF, CostKind);
316 
317   // IR Reduction is composed by two vmv and one rvv reduction instruction.
318   InstructionCost BaseCost = 2;
319   unsigned VL = cast<FixedVectorType>(VTy)->getNumElements();
320   std::pair<InstructionCost, MVT> LT = TLI->getTypeLegalizationCost(DL, VTy);
321 
322   if (TTI::requiresOrderedReduction(FMF))
323     return (LT.first - 1) + BaseCost + VL;
324   return (LT.first - 1) + BaseCost + Log2_32_Ceil(VL);
325 }
326 
327 void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
328                                            TTI::UnrollingPreferences &UP,
329                                            OptimizationRemarkEmitter *ORE) {
330   // TODO: More tuning on benchmarks and metrics with changes as needed
331   //       would apply to all settings below to enable performance.
332 
333   // Support explicit targets enabled for SiFive with the unrolling preferences
334   // below
335   bool UseDefaultPreferences = true;
336   if (ST->getProcFamily() == RISCVSubtarget::SiFive7)
337     UseDefaultPreferences = false;
338 
339   if (UseDefaultPreferences)
340     return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP, ORE);
341 
342   // Enable Upper bound unrolling universally, not dependant upon the conditions
343   // below.
344   UP.UpperBound = true;
345 
346   // Disable loop unrolling for Oz and Os.
347   UP.OptSizeThreshold = 0;
348   UP.PartialOptSizeThreshold = 0;
349   if (L->getHeader()->getParent()->hasOptSize())
350     return;
351 
352   SmallVector<BasicBlock *, 4> ExitingBlocks;
353   L->getExitingBlocks(ExitingBlocks);
354   LLVM_DEBUG(dbgs() << "Loop has:\n"
355                     << "Blocks: " << L->getNumBlocks() << "\n"
356                     << "Exit blocks: " << ExitingBlocks.size() << "\n");
357 
358   // Only allow another exit other than the latch. This acts as an early exit
359   // as it mirrors the profitability calculation of the runtime unroller.
360   if (ExitingBlocks.size() > 2)
361     return;
362 
363   // Limit the CFG of the loop body for targets with a branch predictor.
364   // Allowing 4 blocks permits if-then-else diamonds in the body.
365   if (L->getNumBlocks() > 4)
366     return;
367 
368   // Don't unroll vectorized loops, including the remainder loop
369   if (getBooleanLoopAttribute(L, "llvm.loop.isvectorized"))
370     return;
371 
372   // Scan the loop: don't unroll loops with calls as this could prevent
373   // inlining.
374   InstructionCost Cost = 0;
375   for (auto *BB : L->getBlocks()) {
376     for (auto &I : *BB) {
377       // Initial setting - Don't unroll loops containing vectorized
378       // instructions.
379       if (I.getType()->isVectorTy())
380         return;
381 
382       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
383         if (const Function *F = cast<CallBase>(I).getCalledFunction()) {
384           if (!isLoweredToCall(F))
385             continue;
386         }
387         return;
388       }
389 
390       SmallVector<const Value *> Operands(I.operand_values());
391       Cost +=
392           getUserCost(&I, Operands, TargetTransformInfo::TCK_SizeAndLatency);
393     }
394   }
395 
396   LLVM_DEBUG(dbgs() << "Cost of loop: " << Cost << "\n");
397 
398   UP.Partial = true;
399   UP.Runtime = true;
400   UP.UnrollRemainder = true;
401   UP.UnrollAndJam = true;
402   UP.UnrollAndJamInnerLoopThreshold = 60;
403 
404   // Force unrolling small loops can be very useful because of the branch
405   // taken cost of the backedge.
406   if (Cost < 12)
407     UP.Force = true;
408 }
409 
410 void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
411                                          TTI::PeelingPreferences &PP) {
412   BaseT::getPeelingPreferences(L, SE, PP);
413 }
414 
415 InstructionCost RISCVTTIImpl::getRegUsageForType(Type *Ty) {
416   TypeSize Size = Ty->getPrimitiveSizeInBits();
417   if (Ty->isVectorTy()) {
418     if (Size.isScalable() && ST->hasVInstructions())
419       return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
420 
421     if (ST->useRVVForFixedLengthVectors())
422       return divideCeil(Size, ST->getMinRVVVectorSizeInBits());
423   }
424 
425   return BaseT::getRegUsageForType(Ty);
426 }
427