1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about RISCV target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCV.h"
15 #include "RISCVTargetMachine.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/Support/FormattedStream.h"
22 #include "llvm/Support/TargetRegistry.h"
23 #include "llvm/Target/TargetOptions.h"
24 using namespace llvm;
25 
26 extern "C" void LLVMInitializeRISCVTarget() {
27   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
28   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
29 }
30 
31 static std::string computeDataLayout(const Triple &TT) {
32   if (TT.isArch64Bit()) {
33     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
34   } else {
35     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
36     return "e-m:e-p:32:32-i64:64-n32-S128";
37   }
38 }
39 
40 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
41                                            Optional<Reloc::Model> RM) {
42   if (!RM.hasValue())
43     return Reloc::Static;
44   return *RM;
45 }
46 
47 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
48   if (CM)
49     return *CM;
50   return CodeModel::Small;
51 }
52 
53 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
54                                        StringRef CPU, StringRef FS,
55                                        const TargetOptions &Options,
56                                        Optional<Reloc::Model> RM,
57                                        Optional<CodeModel::Model> CM,
58                                        CodeGenOpt::Level OL, bool JIT)
59     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
60                         getEffectiveRelocModel(TT, RM),
61                         getEffectiveCodeModel(CM), OL),
62       TLOF(make_unique<TargetLoweringObjectFileELF>()),
63       Subtarget(TT, CPU, FS, *this) {
64   initAsmInfo();
65 }
66 
67 namespace {
68 class RISCVPassConfig : public TargetPassConfig {
69 public:
70   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
71       : TargetPassConfig(TM, PM) {}
72 
73   RISCVTargetMachine &getRISCVTargetMachine() const {
74     return getTM<RISCVTargetMachine>();
75   }
76 
77   bool addInstSelector() override;
78   void addPreEmitPass() override;
79 };
80 }
81 
82 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
83   return new RISCVPassConfig(*this, PM);
84 }
85 
86 bool RISCVPassConfig::addInstSelector() {
87   addPass(createRISCVISelDag(getRISCVTargetMachine()));
88 
89   return false;
90 }
91 
92 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
93