1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
14 #include "RISCV.h"
15 #include "RISCVTargetObjectFile.h"
16 #include "RISCVTargetTransformInfo.h"
17 #include "TargetInfo/RISCVTargetInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
22 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
23 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/IR/LegacyPassManager.h"
28 #include "llvm/InitializePasses.h"
29 #include "llvm/Support/FormattedStream.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Target/TargetOptions.h"
32 using namespace llvm;
33 
34 extern "C" void LLVMInitializeRISCVTarget() {
35   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
36   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
37   auto PR = PassRegistry::getPassRegistry();
38   initializeGlobalISel(*PR);
39   initializeRISCVExpandPseudoPass(*PR);
40 }
41 
42 static StringRef computeDataLayout(const Triple &TT) {
43   if (TT.isArch64Bit()) {
44     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
45   } else {
46     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
47     return "e-m:e-p:32:32-i64:64-n32-S128";
48   }
49 }
50 
51 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
52                                            Optional<Reloc::Model> RM) {
53   if (!RM.hasValue())
54     return Reloc::Static;
55   return *RM;
56 }
57 
58 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
59                                        StringRef CPU, StringRef FS,
60                                        const TargetOptions &Options,
61                                        Optional<Reloc::Model> RM,
62                                        Optional<CodeModel::Model> CM,
63                                        CodeGenOpt::Level OL, bool JIT)
64     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
65                         getEffectiveRelocModel(TT, RM),
66                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
67       TLOF(std::make_unique<RISCVELFTargetObjectFile>()),
68       Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
69   initAsmInfo();
70 }
71 
72 TargetTransformInfo
73 RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
74   return TargetTransformInfo(RISCVTTIImpl(this, F));
75 }
76 
77 namespace {
78 class RISCVPassConfig : public TargetPassConfig {
79 public:
80   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
81       : TargetPassConfig(TM, PM) {}
82 
83   RISCVTargetMachine &getRISCVTargetMachine() const {
84     return getTM<RISCVTargetMachine>();
85   }
86 
87   void addIRPasses() override;
88   bool addInstSelector() override;
89   bool addIRTranslator() override;
90   bool addLegalizeMachineIR() override;
91   bool addRegBankSelect() override;
92   bool addGlobalInstructionSelect() override;
93   void addPreEmitPass() override;
94   void addPreEmitPass2() override;
95   void addPreRegAlloc() override;
96 };
97 }
98 
99 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
100   return new RISCVPassConfig(*this, PM);
101 }
102 
103 void RISCVPassConfig::addIRPasses() {
104   addPass(createAtomicExpandPass());
105   TargetPassConfig::addIRPasses();
106 }
107 
108 bool RISCVPassConfig::addInstSelector() {
109   addPass(createRISCVISelDag(getRISCVTargetMachine()));
110 
111   return false;
112 }
113 
114 bool RISCVPassConfig::addIRTranslator() {
115   addPass(new IRTranslator());
116   return false;
117 }
118 
119 bool RISCVPassConfig::addLegalizeMachineIR() {
120   addPass(new Legalizer());
121   return false;
122 }
123 
124 bool RISCVPassConfig::addRegBankSelect() {
125   addPass(new RegBankSelect());
126   return false;
127 }
128 
129 bool RISCVPassConfig::addGlobalInstructionSelect() {
130   addPass(new InstructionSelect());
131   return false;
132 }
133 
134 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
135 
136 void RISCVPassConfig::addPreEmitPass2() {
137   // Schedule the expansion of AMOs at the last possible moment, avoiding the
138   // possibility for other passes to break the requirements for forward
139   // progress in the LR/SC block.
140   addPass(createRISCVExpandPseudoPass());
141 }
142 
143 void RISCVPassConfig::addPreRegAlloc() {
144   addPass(createRISCVMergeBaseOffsetOptPass());
145 }
146