1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
14 #include "RISCV.h"
15 #include "RISCVTargetObjectFile.h"
16 #include "RISCVTargetTransformInfo.h"
17 #include "TargetInfo/RISCVTargetInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/Analysis/TargetTransformInfo.h"
20 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
21 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
22 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
23 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/IR/LegacyPassManager.h"
28 #include "llvm/InitializePasses.h"
29 #include "llvm/Support/FormattedStream.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Target/TargetOptions.h"
32 using namespace llvm;
33 
34 extern "C" void LLVMInitializeRISCVTarget() {
35   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
36   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
37   auto PR = PassRegistry::getPassRegistry();
38   initializeGlobalISel(*PR);
39   initializeRISCVExpandPseudoPass(*PR);
40 }
41 
42 static StringRef computeDataLayout(const Triple &TT) {
43   if (TT.isArch64Bit()) {
44     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
45   } else {
46     assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
47     return "e-m:e-p:32:32-i64:64-n32-S128";
48   }
49 }
50 
51 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
52                                            Optional<Reloc::Model> RM) {
53   if (!RM.hasValue())
54     return Reloc::Static;
55   return *RM;
56 }
57 
58 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
59                                        StringRef CPU, StringRef FS,
60                                        const TargetOptions &Options,
61                                        Optional<Reloc::Model> RM,
62                                        Optional<CodeModel::Model> CM,
63                                        CodeGenOpt::Level OL, bool JIT)
64     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
65                         getEffectiveRelocModel(TT, RM),
66                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
67       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
68   initAsmInfo();
69 }
70 
71 const RISCVSubtarget *
72 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
73   Attribute CPUAttr = F.getFnAttribute("target-cpu");
74   Attribute FSAttr = F.getFnAttribute("target-features");
75 
76   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
77                         ? CPUAttr.getValueAsString().str()
78                         : TargetCPU;
79   std::string FS = !FSAttr.hasAttribute(Attribute::None)
80                        ? FSAttr.getValueAsString().str()
81                        : TargetFS;
82   std::string Key = CPU + FS;
83   auto &I = SubtargetMap[Key];
84   if (!I) {
85     // This needs to be done before we create a new subtarget since any
86     // creation will depend on the TM and the code generation flags on the
87     // function that reside in TargetOptions.
88     resetTargetOptions(F);
89     I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, FS,
90                                          Options.MCOptions.getABIName(), *this);
91   }
92   return I.get();
93 }
94 
95 TargetTransformInfo
96 RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
97   return TargetTransformInfo(RISCVTTIImpl(this, F));
98 }
99 
100 namespace {
101 class RISCVPassConfig : public TargetPassConfig {
102 public:
103   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
104       : TargetPassConfig(TM, PM) {}
105 
106   RISCVTargetMachine &getRISCVTargetMachine() const {
107     return getTM<RISCVTargetMachine>();
108   }
109 
110   void addIRPasses() override;
111   bool addInstSelector() override;
112   bool addIRTranslator() override;
113   bool addLegalizeMachineIR() override;
114   bool addRegBankSelect() override;
115   bool addGlobalInstructionSelect() override;
116   void addPreEmitPass() override;
117   void addPreEmitPass2() override;
118   void addPreRegAlloc() override;
119 };
120 }
121 
122 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
123   return new RISCVPassConfig(*this, PM);
124 }
125 
126 void RISCVPassConfig::addIRPasses() {
127   addPass(createAtomicExpandPass());
128   TargetPassConfig::addIRPasses();
129 }
130 
131 bool RISCVPassConfig::addInstSelector() {
132   addPass(createRISCVISelDag(getRISCVTargetMachine()));
133 
134   return false;
135 }
136 
137 bool RISCVPassConfig::addIRTranslator() {
138   addPass(new IRTranslator());
139   return false;
140 }
141 
142 bool RISCVPassConfig::addLegalizeMachineIR() {
143   addPass(new Legalizer());
144   return false;
145 }
146 
147 bool RISCVPassConfig::addRegBankSelect() {
148   addPass(new RegBankSelect());
149   return false;
150 }
151 
152 bool RISCVPassConfig::addGlobalInstructionSelect() {
153   addPass(new InstructionSelect());
154   return false;
155 }
156 
157 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
158 
159 void RISCVPassConfig::addPreEmitPass2() {
160   // Schedule the expansion of AMOs at the last possible moment, avoiding the
161   // possibility for other passes to break the requirements for forward
162   // progress in the LR/SC block.
163   addPass(createRISCVExpandPseudoPass());
164 }
165 
166 void RISCVPassConfig::addPreRegAlloc() {
167   addPass(createRISCVMergeBaseOffsetOptPass());
168 }
169