1 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implements the info about RISCV target spec.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVTargetMachine.h"
14 #include "MCTargetDesc/RISCVBaseInfo.h"
15 #include "RISCV.h"
16 #include "RISCVMachineFunctionInfo.h"
17 #include "RISCVTargetObjectFile.h"
18 #include "RISCVTargetTransformInfo.h"
19 #include "TargetInfo/RISCVTargetInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/Analysis/TargetTransformInfo.h"
22 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
23 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
24 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
25 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
26 #include "llvm/CodeGen/MIRParser/MIParser.h"
27 #include "llvm/CodeGen/MIRYamlMapping.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/CodeGen/TargetPassConfig.h"
31 #include "llvm/IR/LegacyPassManager.h"
32 #include "llvm/InitializePasses.h"
33 #include "llvm/MC/TargetRegistry.h"
34 #include "llvm/Support/FormattedStream.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Transforms/IPO.h"
37 using namespace llvm;
38 
39 static cl::opt<bool> EnableRedundantCopyElimination(
40     "riscv-enable-copyelim",
41     cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
42     cl::Hidden);
43 
44 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
45   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
46   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
47   auto *PR = PassRegistry::getPassRegistry();
48   initializeGlobalISel(*PR);
49   initializeRISCVGatherScatterLoweringPass(*PR);
50   initializeRISCVMergeBaseOffsetOptPass(*PR);
51   initializeRISCVSExtWRemovalPass(*PR);
52   initializeRISCVExpandPseudoPass(*PR);
53   initializeRISCVInsertVSETVLIPass(*PR);
54 }
55 
56 static StringRef computeDataLayout(const Triple &TT) {
57   if (TT.isArch64Bit())
58     return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
59   assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
60   return "e-m:e-p:32:32-i64:64-n32-S128";
61 }
62 
63 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
64                                            Optional<Reloc::Model> RM) {
65   if (!RM.hasValue())
66     return Reloc::Static;
67   return *RM;
68 }
69 
70 RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
71                                        StringRef CPU, StringRef FS,
72                                        const TargetOptions &Options,
73                                        Optional<Reloc::Model> RM,
74                                        Optional<CodeModel::Model> CM,
75                                        CodeGenOpt::Level OL, bool JIT)
76     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
77                         getEffectiveRelocModel(TT, RM),
78                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
79       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
80   initAsmInfo();
81 
82   // RISC-V supports the MachineOutliner.
83   setMachineOutliner(true);
84   setSupportsDefaultOutlining(true);
85 }
86 
87 const RISCVSubtarget *
88 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
89   Attribute CPUAttr = F.getFnAttribute("target-cpu");
90   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
91   Attribute FSAttr = F.getFnAttribute("target-features");
92 
93   std::string CPU =
94       CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU;
95   std::string TuneCPU =
96       TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU;
97   std::string FS =
98       FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS;
99   std::string Key = CPU + TuneCPU + FS;
100   auto &I = SubtargetMap[Key];
101   if (!I) {
102     // This needs to be done before we create a new subtarget since any
103     // creation will depend on the TM and the code generation flags on the
104     // function that reside in TargetOptions.
105     resetTargetOptions(F);
106     auto ABIName = Options.MCOptions.getABIName();
107     if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
108             F.getParent()->getModuleFlag("target-abi"))) {
109       auto TargetABI = RISCVABI::getTargetABI(ABIName);
110       if (TargetABI != RISCVABI::ABI_Unknown &&
111           ModuleTargetABI->getString() != ABIName) {
112         report_fatal_error("-target-abi option != target-abi module flag");
113       }
114       ABIName = ModuleTargetABI->getString();
115     }
116     I = std::make_unique<RISCVSubtarget>(TargetTriple, CPU, TuneCPU, FS, ABIName, *this);
117   }
118   return I.get();
119 }
120 
121 TargetTransformInfo
122 RISCVTargetMachine::getTargetTransformInfo(const Function &F) const {
123   return TargetTransformInfo(RISCVTTIImpl(this, F));
124 }
125 
126 // A RISC-V hart has a single byte-addressable address space of 2^XLEN bytes
127 // for all memory accesses, so it is reasonable to assume that an
128 // implementation has no-op address space casts. If an implementation makes a
129 // change to this, they can override it here.
130 bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
131                                              unsigned DstAS) const {
132   return true;
133 }
134 
135 namespace {
136 class RISCVPassConfig : public TargetPassConfig {
137 public:
138   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
139       : TargetPassConfig(TM, PM) {}
140 
141   RISCVTargetMachine &getRISCVTargetMachine() const {
142     return getTM<RISCVTargetMachine>();
143   }
144 
145   void addIRPasses() override;
146   bool addPreISel() override;
147   bool addInstSelector() override;
148   bool addIRTranslator() override;
149   bool addLegalizeMachineIR() override;
150   bool addRegBankSelect() override;
151   bool addGlobalInstructionSelect() override;
152   void addPreEmitPass() override;
153   void addPreEmitPass2() override;
154   void addPreSched2() override;
155   void addMachineSSAOptimization() override;
156   void addPreRegAlloc() override;
157   void addPostRegAlloc() override;
158 };
159 } // namespace
160 
161 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
162   return new RISCVPassConfig(*this, PM);
163 }
164 
165 void RISCVPassConfig::addIRPasses() {
166   addPass(createAtomicExpandPass());
167 
168   addPass(createRISCVGatherScatterLoweringPass());
169 
170   TargetPassConfig::addIRPasses();
171 }
172 
173 bool RISCVPassConfig::addPreISel() {
174   if (TM->getOptLevel() != CodeGenOpt::None) {
175     // Add a barrier before instruction selection so that we will not get
176     // deleted block address after enabling default outlining. See D99707 for
177     // more details.
178     addPass(createBarrierNoopPass());
179   }
180   return false;
181 }
182 
183 bool RISCVPassConfig::addInstSelector() {
184   addPass(createRISCVISelDag(getRISCVTargetMachine()));
185 
186   return false;
187 }
188 
189 bool RISCVPassConfig::addIRTranslator() {
190   addPass(new IRTranslator(getOptLevel()));
191   return false;
192 }
193 
194 bool RISCVPassConfig::addLegalizeMachineIR() {
195   addPass(new Legalizer());
196   return false;
197 }
198 
199 bool RISCVPassConfig::addRegBankSelect() {
200   addPass(new RegBankSelect());
201   return false;
202 }
203 
204 bool RISCVPassConfig::addGlobalInstructionSelect() {
205   addPass(new InstructionSelect(getOptLevel()));
206   return false;
207 }
208 
209 void RISCVPassConfig::addPreSched2() {}
210 
211 void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
212 
213 void RISCVPassConfig::addPreEmitPass2() {
214   addPass(createRISCVExpandPseudoPass());
215   // Schedule the expansion of AMOs at the last possible moment, avoiding the
216   // possibility for other passes to break the requirements for forward
217   // progress in the LR/SC block.
218   addPass(createRISCVExpandAtomicPseudoPass());
219 }
220 
221 void RISCVPassConfig::addMachineSSAOptimization() {
222   TargetPassConfig::addMachineSSAOptimization();
223 
224   if (TM->getTargetTriple().getArch() == Triple::riscv64)
225     addPass(createRISCVSExtWRemovalPass());
226 }
227 
228 void RISCVPassConfig::addPreRegAlloc() {
229   if (TM->getOptLevel() != CodeGenOpt::None)
230     addPass(createRISCVMergeBaseOffsetOptPass());
231   addPass(createRISCVInsertVSETVLIPass());
232 }
233 
234 void RISCVPassConfig::addPostRegAlloc() {
235   if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
236     addPass(createRISCVRedundantCopyEliminationPass());
237 }
238 
239 yaml::MachineFunctionInfo *
240 RISCVTargetMachine::createDefaultFuncInfoYAML() const {
241   return new yaml::RISCVMachineFunctionInfo();
242 }
243 
244 yaml::MachineFunctionInfo *
245 RISCVTargetMachine::convertFuncInfoToYAML(const MachineFunction &MF) const {
246   const auto *MFI = MF.getInfo<RISCVMachineFunctionInfo>();
247   return new yaml::RISCVMachineFunctionInfo(*MFI);
248 }
249 
250 bool RISCVTargetMachine::parseMachineFunctionInfo(
251     const yaml::MachineFunctionInfo &MFI, PerFunctionMIParsingState &PFS,
252     SMDiagnostic &Error, SMRange &SourceRange) const {
253   const auto &YamlMFI =
254       static_cast<const yaml::RISCVMachineFunctionInfo &>(MFI);
255   PFS.MF.getInfo<RISCVMachineFunctionInfo>()->initializeBaseYamlFields(YamlMFI);
256   return false;
257 }
258