1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/MC/TargetRegistry.h"
21 #include "llvm/Support/ErrorHandling.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "riscv-subtarget"
26 
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #define GET_SUBTARGETINFO_CTOR
29 #include "RISCVGenSubtargetInfo.inc"
30 
31 static cl::opt<bool> EnableSubRegLiveness("riscv-enable-subreg-liveness",
32                                           cl::init(false), cl::Hidden);
33 
34 static cl::opt<int> RVVVectorBitsMax(
35     "riscv-v-vector-bits-max",
36     cl::desc("Assume V extension vector registers are at most this big, "
37              "with zero meaning no maximum size is assumed."),
38     cl::init(0), cl::Hidden);
39 
40 static cl::opt<int> RVVVectorBitsMin(
41     "riscv-v-vector-bits-min",
42     cl::desc("Assume V extension vector registers are at least this big, "
43              "with zero meaning no minimum size is assumed. A value of -1 "
44              "means use Zvl*b extension. This is primarily used to enable "
45              "autovectorization with fixed width vectors."),
46     cl::init(0), cl::Hidden);
47 
48 static cl::opt<unsigned> RVVVectorLMULMax(
49     "riscv-v-fixed-length-vector-lmul-max",
50     cl::desc("The maximum LMUL value to use for fixed length vectors. "
51              "Fractional LMUL values are not supported."),
52     cl::init(8), cl::Hidden);
53 
54 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
55     "riscv-disable-using-constant-pool-for-large-ints",
56     cl::desc("Disable using constant pool for large integers."),
57     cl::init(false), cl::Hidden);
58 
59 static cl::opt<unsigned> RISCVMaxBuildIntsCost(
60     "riscv-max-build-ints-cost",
61     cl::desc("The maximum cost used for building integers."), cl::init(0),
62     cl::Hidden);
63 
64 void RISCVSubtarget::anchor() {}
65 
66 RISCVSubtarget &
67 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
68                                                 StringRef TuneCPU, StringRef FS,
69                                                 StringRef ABIName) {
70   // Determine default and user-specified characteristics
71   bool Is64Bit = TT.isArch64Bit();
72   if (CPU.empty() || CPU == "generic")
73     CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
74 
75   if (TuneCPU.empty())
76     TuneCPU = CPU;
77 
78   ParseSubtargetFeatures(CPU, TuneCPU, FS);
79   if (Is64Bit) {
80     XLenVT = MVT::i64;
81     XLen = 64;
82   }
83 
84   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
85   RISCVFeatures::validate(TT, getFeatureBits());
86   return *this;
87 }
88 
89 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
90                                StringRef TuneCPU, StringRef FS,
91                                StringRef ABIName, const TargetMachine &TM)
92     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
93       UserReservedRegister(RISCV::NUM_TARGET_REGS),
94       FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
95       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
96   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
97   Legalizer.reset(new RISCVLegalizerInfo(*this));
98 
99   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
100   RegBankInfo.reset(RBI);
101   InstSelector.reset(createRISCVInstructionSelector(
102       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
103 }
104 
105 const CallLowering *RISCVSubtarget::getCallLowering() const {
106   return CallLoweringInfo.get();
107 }
108 
109 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
110   return InstSelector.get();
111 }
112 
113 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
114   return Legalizer.get();
115 }
116 
117 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
118   return RegBankInfo.get();
119 }
120 
121 bool RISCVSubtarget::useConstantPoolForLargeInts() const {
122   return !RISCVDisableUsingConstantPoolForLargeInts;
123 }
124 
125 unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
126   // Loading integer from constant pool needs two instructions (the reason why
127   // the minimum cost is 2): an address calculation instruction and a load
128   // instruction. Usually, address calculation and instructions used for
129   // building integers (addi, slli, etc.) can be done in one cycle, so here we
130   // set the default cost to (LoadLatency + 1) if no threshold is provided.
131   return RISCVMaxBuildIntsCost == 0
132              ? getSchedModel().LoadLatency + 1
133              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
134 }
135 
136 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
137   assert(hasVInstructions() &&
138          "Tried to get vector length without Zve or V extension support!");
139   if (RVVVectorBitsMax == 0)
140     return 0;
141 
142   // ZvlLen specifies the minimum required vlen. The upper bound provided by
143   // riscv-v-vector-bits-max should be no less than it.
144   if (RVVVectorBitsMax < (int)ZvlLen)
145     report_fatal_error("riscv-v-vector-bits-max specified is lower "
146                        "than the Zvl*b limitation");
147 
148   // FIXME: Change to >= 32 when VLEN = 32 is supported
149   assert(
150       RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
151       isPowerOf2_32(RVVVectorBitsMax) &&
152       "V or Zve* extension requires vector length to be in the range of 64 to "
153       "65536 and a power of 2!");
154   assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
155          "Minimum V extension vector length should not be larger than its "
156          "maximum!");
157   unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
158   return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max);
159 }
160 
161 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
162   assert(hasVInstructions() &&
163          "Tried to get vector length without Zve or V extension support!");
164 
165   if (RVVVectorBitsMin == -1)
166     return ZvlLen;
167 
168   // ZvlLen specifies the minimum required vlen. The lower bound provided by
169   // riscv-v-vector-bits-min should be no less than it.
170   if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < (int)ZvlLen)
171     report_fatal_error("riscv-v-vector-bits-min specified is lower "
172                        "than the Zvl*b limitation");
173 
174   // FIXME: Change to >= 32 when VLEN = 32 is supported
175   assert(
176       (RVVVectorBitsMin == 0 ||
177        (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 &&
178         isPowerOf2_32(RVVVectorBitsMin))) &&
179       "V or Zve* extension requires vector length to be in the range of 64 to "
180       "65536 and a power of 2!");
181   assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
182          "Minimum V extension vector length should not be larger than its "
183          "maximum!");
184   unsigned Min = RVVVectorBitsMin;
185   if (RVVVectorBitsMax != 0)
186     Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
187   return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min);
188 }
189 
190 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
191   assert(hasVInstructions() &&
192          "Tried to get vector length without Zve or V extension support!");
193   assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
194          "V extension requires a LMUL to be at most 8 and a power of 2!");
195   return PowerOf2Floor(
196       std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
197 }
198 
199 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
200   return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
201 }
202 
203 bool RISCVSubtarget::enableSubRegLiveness() const {
204   // TODO: Enable for for RVV to better handle LMUL>1 and segment load/store.
205   return EnableSubRegLiveness;
206 }
207