1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/MC/TargetRegistry.h"
21 #include "llvm/Support/ErrorHandling.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "riscv-subtarget"
26 
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #define GET_SUBTARGETINFO_CTOR
29 #include "RISCVGenSubtargetInfo.inc"
30 
31 static cl::opt<int> RVVVectorBitsMax(
32     "riscv-v-vector-bits-max",
33     cl::desc("Assume V extension vector registers are at most this big, "
34              "with zero meaning no maximum size is assumed."),
35     cl::init(0), cl::Hidden);
36 
37 static cl::opt<int> RVVVectorBitsMin(
38     "riscv-v-vector-bits-min",
39     cl::desc("Assume V extension vector registers are at least this big, "
40              "with zero meaning no minimum size is assumed. A value of -1 "
41              "means use Zvl*b extension. This is primarily used to enable "
42              "autovectorization with fixed width vectors."),
43     cl::init(0), cl::Hidden);
44 
45 static cl::opt<unsigned> RVVVectorLMULMax(
46     "riscv-v-fixed-length-vector-lmul-max",
47     cl::desc("The maximum LMUL value to use for fixed length vectors. "
48              "Fractional LMUL values are not supported."),
49     cl::init(8), cl::Hidden);
50 
51 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
52     "riscv-disable-using-constant-pool-for-large-ints",
53     cl::desc("Disable using constant pool for large integers."),
54     cl::init(false), cl::Hidden);
55 
56 static cl::opt<unsigned> RISCVMaxBuildIntsCost(
57     "riscv-max-build-ints-cost",
58     cl::desc("The maximum cost used for building integers."), cl::init(0),
59     cl::Hidden);
60 
61 void RISCVSubtarget::anchor() {}
62 
63 RISCVSubtarget &
64 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
65                                                 StringRef TuneCPU, StringRef FS,
66                                                 StringRef ABIName) {
67   // Determine default and user-specified characteristics
68   bool Is64Bit = TT.isArch64Bit();
69   if (CPU.empty() || CPU == "generic")
70     CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
71 
72   if (TuneCPU.empty())
73     TuneCPU = CPU;
74 
75   ParseSubtargetFeatures(CPU, TuneCPU, FS);
76   if (Is64Bit) {
77     XLenVT = MVT::i64;
78     XLen = 64;
79   }
80 
81   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
82   RISCVFeatures::validate(TT, getFeatureBits());
83   return *this;
84 }
85 
86 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
87                                StringRef TuneCPU, StringRef FS,
88                                StringRef ABIName, const TargetMachine &TM)
89     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
90       UserReservedRegister(RISCV::NUM_TARGET_REGS),
91       FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
92       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
93   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
94   Legalizer.reset(new RISCVLegalizerInfo(*this));
95 
96   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
97   RegBankInfo.reset(RBI);
98   InstSelector.reset(createRISCVInstructionSelector(
99       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
100 }
101 
102 const CallLowering *RISCVSubtarget::getCallLowering() const {
103   return CallLoweringInfo.get();
104 }
105 
106 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
107   return InstSelector.get();
108 }
109 
110 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
111   return Legalizer.get();
112 }
113 
114 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
115   return RegBankInfo.get();
116 }
117 
118 bool RISCVSubtarget::useConstantPoolForLargeInts() const {
119   return !RISCVDisableUsingConstantPoolForLargeInts;
120 }
121 
122 unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
123   // Loading integer from constant pool needs two instructions (the reason why
124   // the minimum cost is 2): an address calculation instruction and a load
125   // instruction. Usually, address calculation and instructions used for
126   // building integers (addi, slli, etc.) can be done in one cycle, so here we
127   // set the default cost to (LoadLatency + 1) if no threshold is provided.
128   return RISCVMaxBuildIntsCost == 0
129              ? getSchedModel().LoadLatency + 1
130              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
131 }
132 
133 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
134   assert(hasVInstructions() &&
135          "Tried to get vector length without Zve or V extension support!");
136   if (RVVVectorBitsMax == 0)
137     return 0;
138 
139   // ZvlLen specifies the minimum required vlen. The upper bound provided by
140   // riscv-v-vector-bits-max should be no less than it.
141   if (RVVVectorBitsMax < (int)ZvlLen)
142     report_fatal_error("riscv-v-vector-bits-max specified is lower "
143                        "than the Zvl*b limitation");
144 
145   // FIXME: Change to >= 32 when VLEN = 32 is supported
146   assert(
147       RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
148       isPowerOf2_32(RVVVectorBitsMax) &&
149       "V or Zve* extension requires vector length to be in the range of 64 to "
150       "65536 and a power of 2!");
151   assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
152          "Minimum V extension vector length should not be larger than its "
153          "maximum!");
154   unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
155   return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max);
156 }
157 
158 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
159   assert(hasVInstructions() &&
160          "Tried to get vector length without Zve or V extension support!");
161 
162   if (RVVVectorBitsMin == -1)
163     return ZvlLen;
164 
165   // ZvlLen specifies the minimum required vlen. The lower bound provided by
166   // riscv-v-vector-bits-min should be no less than it.
167   if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < (int)ZvlLen)
168     report_fatal_error("riscv-v-vector-bits-min specified is lower "
169                        "than the Zvl*b limitation");
170 
171   // FIXME: Change to >= 32 when VLEN = 32 is supported
172   assert(
173       (RVVVectorBitsMin == 0 ||
174        (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 &&
175         isPowerOf2_32(RVVVectorBitsMin))) &&
176       "V or Zve* extension requires vector length to be in the range of 64 to "
177       "65536 and a power of 2!");
178   assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
179          "Minimum V extension vector length should not be larger than its "
180          "maximum!");
181   unsigned Min = RVVVectorBitsMin;
182   if (RVVVectorBitsMax != 0)
183     Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
184   return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min);
185 }
186 
187 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
188   assert(hasVInstructions() &&
189          "Tried to get vector length without Zve or V extension support!");
190   assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
191          "V extension requires a LMUL to be at most 8 and a power of 2!");
192   return PowerOf2Floor(
193       std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
194 }
195 
196 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
197   return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
198 }
199