1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/MC/TargetRegistry.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "riscv-subtarget"
25 
26 #define GET_SUBTARGETINFO_TARGET_DESC
27 #define GET_SUBTARGETINFO_CTOR
28 #include "RISCVGenSubtargetInfo.inc"
29 
30 static cl::opt<unsigned> RVVVectorBitsMax(
31     "riscv-v-vector-bits-max",
32     cl::desc("Assume V extension vector registers are at most this big, "
33              "with zero meaning no maximum size is assumed."),
34     cl::init(0), cl::Hidden);
35 
36 static cl::opt<unsigned> RVVVectorBitsMin(
37     "riscv-v-vector-bits-min",
38     cl::desc("Assume V extension vector registers are at least this big, "
39              "with zero meaning no minimum size is assumed."),
40     cl::init(0), cl::Hidden);
41 
42 static cl::opt<unsigned> RVVVectorLMULMax(
43     "riscv-v-fixed-length-vector-lmul-max",
44     cl::desc("The maximum LMUL value to use for fixed length vectors. "
45              "Fractional LMUL values are not supported."),
46     cl::init(8), cl::Hidden);
47 
48 static cl::opt<unsigned> RVVVectorELENMax(
49     "riscv-v-fixed-length-vector-elen-max",
50     cl::desc("The maximum ELEN value to use for fixed length vectors."),
51     cl::init(64), cl::Hidden);
52 
53 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
54     "riscv-disable-using-constant-pool-for-large-ints",
55     cl::desc("Disable using constant pool for large integers."),
56     cl::init(false), cl::Hidden);
57 
58 static cl::opt<unsigned> RISCVMaxBuildIntsCost(
59     "riscv-max-build-ints-cost",
60     cl::desc("The maximum cost used for building integers."), cl::init(0),
61     cl::Hidden);
62 
63 void RISCVSubtarget::anchor() {}
64 
65 RISCVSubtarget &
66 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
67                                                 StringRef TuneCPU, StringRef FS,
68                                                 StringRef ABIName) {
69   // Determine default and user-specified characteristics
70   bool Is64Bit = TT.isArch64Bit();
71   if (CPU.empty())
72     CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
73   if (CPU == "generic")
74     report_fatal_error(Twine("CPU 'generic' is not supported. Use ") +
75                        (Is64Bit ? "generic-rv64" : "generic-rv32"));
76 
77   if (TuneCPU.empty())
78     TuneCPU = CPU;
79 
80   ParseSubtargetFeatures(CPU, TuneCPU, FS);
81   if (Is64Bit) {
82     XLenVT = MVT::i64;
83     XLen = 64;
84   }
85 
86   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
87   RISCVFeatures::validate(TT, getFeatureBits());
88   return *this;
89 }
90 
91 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
92                                StringRef TuneCPU, StringRef FS,
93                                StringRef ABIName, const TargetMachine &TM)
94     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
95       UserReservedRegister(RISCV::NUM_TARGET_REGS),
96       FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
97       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
98   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
99   Legalizer.reset(new RISCVLegalizerInfo(*this));
100 
101   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
102   RegBankInfo.reset(RBI);
103   InstSelector.reset(createRISCVInstructionSelector(
104       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
105 }
106 
107 const CallLowering *RISCVSubtarget::getCallLowering() const {
108   return CallLoweringInfo.get();
109 }
110 
111 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
112   return InstSelector.get();
113 }
114 
115 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
116   return Legalizer.get();
117 }
118 
119 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
120   return RegBankInfo.get();
121 }
122 
123 bool RISCVSubtarget::useConstantPoolForLargeInts() const {
124   return !RISCVDisableUsingConstantPoolForLargeInts;
125 }
126 
127 unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
128   // Loading integer from constant pool needs two instructions (the reason why
129   // the minimum cost is 2): an address calculation instruction and a load
130   // instruction. Usually, address calculation and instructions used for
131   // building integers (addi, slli, etc.) can be done in one cycle, so here we
132   // set the default cost to (LoadLatency + 1) if no threshold is provided.
133   return RISCVMaxBuildIntsCost == 0
134              ? getSchedModel().LoadLatency + 1
135              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
136 }
137 
138 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
139   assert(hasVInstructions() &&
140          "Tried to get vector length without Zve or V extension support!");
141   if (RVVVectorBitsMax == 0)
142     return 0;
143   assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
144          isPowerOf2_32(RVVVectorBitsMax) &&
145          "V extension requires vector length to be in the range of 128 to "
146          "65536 and a power of 2!");
147   assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
148          "Minimum V extension vector length should not be larger than its "
149          "maximum!");
150   unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
151   return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max);
152 }
153 
154 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
155   assert(hasVInstructions() &&
156          "Tried to get vector length without Zve or V extension support!");
157   assert((RVVVectorBitsMin == 0 ||
158           (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
159            isPowerOf2_32(RVVVectorBitsMin))) &&
160          "V extension requires vector length to be in the range of 128 to "
161          "65536 and a power of 2!");
162   assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
163          "Minimum V extension vector length should not be larger than its "
164          "maximum!");
165   unsigned Min = RVVVectorBitsMin;
166   if (RVVVectorBitsMax != 0)
167     Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
168   return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min);
169 }
170 
171 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
172   assert(hasVInstructions() &&
173          "Tried to get vector length without Zve or V extension support!");
174   assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
175          "V extension requires a LMUL to be at most 8 and a power of 2!");
176   return PowerOf2Floor(
177       std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
178 }
179 
180 unsigned RISCVSubtarget::getMaxELENForFixedLengthVectors() const {
181   assert(hasVInstructions() &&
182          "Tried to get maximum ELEN without Zve or V extension support!");
183   assert(RVVVectorELENMax <= 64 && RVVVectorELENMax >= 8 &&
184          isPowerOf2_32(RVVVectorELENMax) &&
185          "V extension requires a ELEN to be a power of 2 between 8 and 64!");
186   return PowerOf2Floor(
187       std::max<unsigned>(std::min<unsigned>(RVVVectorELENMax, 64), 8));
188 }
189 
190 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
191   return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
192 }
193