1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RISCV specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "RISCVSubtarget.h" 14 #include "RISCV.h" 15 #include "RISCVCallLowering.h" 16 #include "RISCVFrameLowering.h" 17 #include "RISCVLegalizerInfo.h" 18 #include "RISCVRegisterBankInfo.h" 19 #include "RISCVTargetMachine.h" 20 #include "llvm/Support/TargetRegistry.h" 21 22 using namespace llvm; 23 24 #define DEBUG_TYPE "riscv-subtarget" 25 26 #define GET_SUBTARGETINFO_TARGET_DESC 27 #define GET_SUBTARGETINFO_CTOR 28 #include "RISCVGenSubtargetInfo.inc" 29 30 static cl::opt<unsigned> RVVVectorBitsMax( 31 "riscv-v-vector-bits-max", 32 cl::desc("Assume V extension vector registers are at most this big, " 33 "with zero meaning no maximum size is assumed."), 34 cl::init(0), cl::Hidden); 35 36 static cl::opt<unsigned> RVVVectorBitsMin( 37 "riscv-v-vector-bits-min", 38 cl::desc("Assume V extension vector registers are at least this big, " 39 "with zero meaning no minimum size is assumed."), 40 cl::init(0), cl::Hidden); 41 42 static cl::opt<unsigned> RVVVectorLMULMax( 43 "riscv-v-fixed-length-vector-lmul-max", 44 cl::desc("The maximum LMUL value to use for fixed length vectors. " 45 "Fractional LMUL values are not supported."), 46 cl::init(8), cl::Hidden); 47 48 void RISCVSubtarget::anchor() {} 49 50 RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies( 51 const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, StringRef ABIName) { 52 // Determine default and user-specified characteristics 53 bool Is64Bit = TT.isArch64Bit(); 54 std::string CPUName = std::string(CPU); 55 std::string TuneCPUName = std::string(TuneCPU); 56 if (CPUName.empty()) 57 CPUName = Is64Bit ? "generic-rv64" : "generic-rv32"; 58 if (TuneCPUName.empty()) 59 TuneCPUName = CPUName; 60 ParseSubtargetFeatures(CPUName, TuneCPUName, FS); 61 if (Is64Bit) { 62 XLenVT = MVT::i64; 63 XLen = 64; 64 } 65 66 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); 67 RISCVFeatures::validate(TT, getFeatureBits()); 68 return *this; 69 } 70 71 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, 72 StringRef TuneCPU, StringRef FS, 73 StringRef ABIName, const TargetMachine &TM) 74 : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS), 75 UserReservedRegister(RISCV::NUM_TARGET_REGS), 76 FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)), 77 InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) { 78 CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering())); 79 Legalizer.reset(new RISCVLegalizerInfo(*this)); 80 81 auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo()); 82 RegBankInfo.reset(RBI); 83 InstSelector.reset(createRISCVInstructionSelector( 84 *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI)); 85 } 86 87 const CallLowering *RISCVSubtarget::getCallLowering() const { 88 return CallLoweringInfo.get(); 89 } 90 91 InstructionSelector *RISCVSubtarget::getInstructionSelector() const { 92 return InstSelector.get(); 93 } 94 95 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const { 96 return Legalizer.get(); 97 } 98 99 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const { 100 return RegBankInfo.get(); 101 } 102 103 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const { 104 assert(hasStdExtV() && "Tried to get vector length without V support!"); 105 if (RVVVectorBitsMax == 0) 106 return 0; 107 assert(RVVVectorBitsMax >= 128 && isPowerOf2_32(RVVVectorBitsMax) && 108 "V extension requires vector length to be at least 128 and a power of " 109 "2!"); 110 assert(RVVVectorBitsMax >= RVVVectorBitsMin && 111 "Minimum V extension vector length should not be larger than its " 112 "maximum!"); 113 unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax); 114 return PowerOf2Floor(Max < 128 ? 0 : Max); 115 } 116 117 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const { 118 assert(hasStdExtV() && 119 "Tried to get vector length without V extension support!"); 120 assert((RVVVectorBitsMin == 0 || 121 (RVVVectorBitsMin >= 128 && isPowerOf2_32(RVVVectorBitsMin))) && 122 "V extension requires vector length to be at least 128 and a power of " 123 "2!"); 124 assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) && 125 "Minimum V extension vector length should not be larger than its " 126 "maximum!"); 127 unsigned Min = RVVVectorBitsMin; 128 if (RVVVectorBitsMax != 0) 129 Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax); 130 return PowerOf2Floor(Min < 128 ? 0 : Min); 131 } 132 133 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const { 134 assert(hasStdExtV() && 135 "Tried to get maximum LMUL without V extension support!"); 136 assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) && 137 "V extension requires a LMUL to be at most 8 and a power of 2!"); 138 return PowerOf2Floor(std::max<unsigned>(RVVVectorLMULMax, 1)); 139 } 140 141 bool RISCVSubtarget::useRVVForFixedLengthVectors() const { 142 return hasStdExtV() && getMinRVVVectorSizeInBits() != 0; 143 } 144 145 unsigned RISCVSubtarget::getLMULForFixedLengthVector(MVT VT) const { 146 unsigned MinVLen = getMinRVVVectorSizeInBits(); 147 148 // Masks only occupy a single register. An LMUL==1 operation can only use 149 // at most 1/8 of the register. Only an LMUL==8 operaton on i8 types can 150 // use the whole register. 151 if (VT.getVectorElementType() == MVT::i1) 152 MinVLen /= 8; 153 154 return divideCeil(VT.getSizeInBits(), MinVLen); 155 } 156