1 //===-- RISCVSubtarget.cpp - RISCV Subtarget Information ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the RISCV specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVSubtarget.h"
14 #include "RISCV.h"
15 #include "RISCVCallLowering.h"
16 #include "RISCVFrameLowering.h"
17 #include "RISCVLegalizerInfo.h"
18 #include "RISCVRegisterBankInfo.h"
19 #include "RISCVTargetMachine.h"
20 #include "llvm/MC/TargetRegistry.h"
21 #include "llvm/Support/ErrorHandling.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "riscv-subtarget"
26 
27 #define GET_SUBTARGETINFO_TARGET_DESC
28 #define GET_SUBTARGETINFO_CTOR
29 #include "RISCVGenSubtargetInfo.inc"
30 
31 static cl::opt<unsigned> RVVVectorBitsMax(
32     "riscv-v-vector-bits-max",
33     cl::desc("Assume V extension vector registers are at most this big, "
34              "with zero meaning no maximum size is assumed."),
35     cl::init(0), cl::Hidden);
36 
37 static cl::opt<unsigned> RVVVectorBitsMin(
38     "riscv-v-vector-bits-min",
39     cl::desc("Assume V extension vector registers are at least this big, "
40              "with zero meaning no minimum size is assumed."),
41     cl::init(0), cl::Hidden);
42 
43 static cl::opt<unsigned> RVVVectorLMULMax(
44     "riscv-v-fixed-length-vector-lmul-max",
45     cl::desc("The maximum LMUL value to use for fixed length vectors. "
46              "Fractional LMUL values are not supported."),
47     cl::init(8), cl::Hidden);
48 
49 static cl::opt<bool> RISCVDisableUsingConstantPoolForLargeInts(
50     "riscv-disable-using-constant-pool-for-large-ints",
51     cl::desc("Disable using constant pool for large integers."),
52     cl::init(false), cl::Hidden);
53 
54 static cl::opt<unsigned> RISCVMaxBuildIntsCost(
55     "riscv-max-build-ints-cost",
56     cl::desc("The maximum cost used for building integers."), cl::init(0),
57     cl::Hidden);
58 
59 void RISCVSubtarget::anchor() {}
60 
61 RISCVSubtarget &
62 RISCVSubtarget::initializeSubtargetDependencies(const Triple &TT, StringRef CPU,
63                                                 StringRef TuneCPU, StringRef FS,
64                                                 StringRef ABIName) {
65   // Determine default and user-specified characteristics
66   bool Is64Bit = TT.isArch64Bit();
67   if (CPU.empty() || CPU == "generic")
68     CPU = Is64Bit ? "generic-rv64" : "generic-rv32";
69 
70   if (TuneCPU.empty())
71     TuneCPU = CPU;
72 
73   ParseSubtargetFeatures(CPU, TuneCPU, FS);
74   if (Is64Bit) {
75     XLenVT = MVT::i64;
76     XLen = 64;
77   }
78 
79   TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName);
80   RISCVFeatures::validate(TT, getFeatureBits());
81   return *this;
82 }
83 
84 RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU,
85                                StringRef TuneCPU, StringRef FS,
86                                StringRef ABIName, const TargetMachine &TM)
87     : RISCVGenSubtargetInfo(TT, CPU, TuneCPU, FS),
88       UserReservedRegister(RISCV::NUM_TARGET_REGS),
89       FrameLowering(initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
90       InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
91   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
92   Legalizer.reset(new RISCVLegalizerInfo(*this));
93 
94   auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
95   RegBankInfo.reset(RBI);
96   InstSelector.reset(createRISCVInstructionSelector(
97       *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
98 }
99 
100 const CallLowering *RISCVSubtarget::getCallLowering() const {
101   return CallLoweringInfo.get();
102 }
103 
104 InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
105   return InstSelector.get();
106 }
107 
108 const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
109   return Legalizer.get();
110 }
111 
112 const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
113   return RegBankInfo.get();
114 }
115 
116 bool RISCVSubtarget::useConstantPoolForLargeInts() const {
117   return !RISCVDisableUsingConstantPoolForLargeInts;
118 }
119 
120 unsigned RISCVSubtarget::getMaxBuildIntsCost() const {
121   // Loading integer from constant pool needs two instructions (the reason why
122   // the minimum cost is 2): an address calculation instruction and a load
123   // instruction. Usually, address calculation and instructions used for
124   // building integers (addi, slli, etc.) can be done in one cycle, so here we
125   // set the default cost to (LoadLatency + 1) if no threshold is provided.
126   return RISCVMaxBuildIntsCost == 0
127              ? getSchedModel().LoadLatency + 1
128              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
129 }
130 
131 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
132   assert(hasVInstructions() &&
133          "Tried to get vector length without Zve or V extension support!");
134   if (RVVVectorBitsMax == 0)
135     return 0;
136 
137   // ZvlLen specifies the minimum required vlen. The upper bound provided by
138   // riscv-v-vector-bits-max should be no less than it.
139   if (RVVVectorBitsMax < ZvlLen)
140     report_fatal_error("riscv-v-vector-bits-max specified is lower "
141                        "than the Zvl*b limitation");
142 
143   // FIXME: Change to >= 32 when VLEN = 32 is supported
144   assert(
145       RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
146       isPowerOf2_32(RVVVectorBitsMax) &&
147       "V or Zve* extension requires vector length to be in the range of 64 to "
148       "65536 and a power of 2!");
149   assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
150          "Minimum V extension vector length should not be larger than its "
151          "maximum!");
152   unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
153   return PowerOf2Floor((Max < 64 || Max > 65536) ? 0 : Max);
154 }
155 
156 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
157   // ZvlLen specifies the minimum required vlen. The lower bound provided by
158   // riscv-v-vector-bits-min should be no less than it.
159   if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
160     report_fatal_error("riscv-v-vector-bits-min specified is lower "
161                        "than the Zvl*b limitation");
162 
163   assert(hasVInstructions() &&
164          "Tried to get vector length without Zve or V extension support!");
165   // FIXME: Change to >= 32 when VLEN = 32 is supported
166   assert(
167       (RVVVectorBitsMin == 0 ||
168        (RVVVectorBitsMin >= 64 && RVVVectorBitsMin <= 65536 &&
169         isPowerOf2_32(RVVVectorBitsMin))) &&
170       "V or Zve* extension requires vector length to be in the range of 64 to "
171       "65536 and a power of 2!");
172   assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
173          "Minimum V extension vector length should not be larger than its "
174          "maximum!");
175   unsigned Min = RVVVectorBitsMin;
176   if (RVVVectorBitsMax != 0)
177     Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
178   return PowerOf2Floor((Min < 64 || Min > 65536) ? 0 : Min);
179 }
180 
181 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
182   assert(hasVInstructions() &&
183          "Tried to get vector length without Zve or V extension support!");
184   assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
185          "V extension requires a LMUL to be at most 8 and a power of 2!");
186   return PowerOf2Floor(
187       std::max<unsigned>(std::min<unsigned>(RVVVectorLMULMax, 8), 1));
188 }
189 
190 bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
191   return hasVInstructions() && getMinRVVVectorSizeInBits() != 0;
192 }
193