1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the RISCV implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVRegisterInfo.h" 15 #include "RISCV.h" 16 #include "RISCVSubtarget.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/RegisterScavenging.h" 21 #include "llvm/CodeGen/TargetFrameLowering.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/Support/ErrorHandling.h" 24 25 #define GET_REGINFO_TARGET_DESC 26 #include "RISCVGenRegisterInfo.inc" 27 28 using namespace llvm; 29 30 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) 31 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, 32 /*PC*/0, HwMode) {} 33 34 const MCPhysReg * 35 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 36 return CSR_SaveList; 37 } 38 39 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 40 BitVector Reserved(getNumRegs()); 41 42 // Use markSuperRegs to ensure any register aliases are also reserved 43 markSuperRegs(Reserved, RISCV::X0); // zero 44 markSuperRegs(Reserved, RISCV::X1); // ra 45 markSuperRegs(Reserved, RISCV::X2); // sp 46 markSuperRegs(Reserved, RISCV::X3); // gp 47 markSuperRegs(Reserved, RISCV::X4); // tp 48 markSuperRegs(Reserved, RISCV::X8); // fp 49 assert(checkAllSuperRegsMarked(Reserved)); 50 return Reserved; 51 } 52 53 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { 54 return CSR_NoRegs_RegMask; 55 } 56 57 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 58 int SPAdj, unsigned FIOperandNum, 59 RegScavenger *RS) const { 60 // TODO: this implementation is a temporary placeholder which does just 61 // enough to allow other aspects of code generation to be tested 62 63 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value"); 64 65 MachineInstr &MI = *II; 66 MachineFunction &MF = *MI.getParent()->getParent(); 67 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); 68 DebugLoc DL = MI.getDebugLoc(); 69 70 unsigned FrameReg = getFrameRegister(MF); 71 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 72 int Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg); 73 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 74 75 assert(TFI->hasFP(MF) && "eliminateFrameIndex currently requires hasFP"); 76 77 // Offsets must be directly encoded in a 12-bit immediate field 78 if (!isInt<12>(Offset)) { 79 report_fatal_error( 80 "Frame offsets outside of the signed 12-bit range not supported"); 81 } 82 83 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false); 84 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 85 } 86 87 unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 88 return RISCV::X8; 89 } 90 91 const uint32_t * 92 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/, 93 CallingConv::ID /*CC*/) const { 94 return CSR_RegMask; 95 } 96