1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVMachineFunctionInfo.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "RISCVGenRegisterInfo.inc"
27 
28 using namespace llvm;
29 
30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
32 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
33 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
34               "Register list not consecutive");
35 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
36 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
37               "Register list not consecutive");
38 
39 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
40     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
41                            /*PC*/0, HwMode) {}
42 
43 const MCPhysReg *
44 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
45   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
46   if (MF->getFunction().hasFnAttribute("interrupt")) {
47     if (Subtarget.hasStdExtD())
48       return CSR_XLEN_F64_Interrupt_SaveList;
49     if (Subtarget.hasStdExtF())
50       return CSR_XLEN_F32_Interrupt_SaveList;
51     return CSR_Interrupt_SaveList;
52   }
53 
54   switch (Subtarget.getTargetABI()) {
55   default:
56     llvm_unreachable("Unrecognized ABI");
57   case RISCVABI::ABI_ILP32:
58   case RISCVABI::ABI_LP64:
59     return CSR_ILP32_LP64_SaveList;
60   case RISCVABI::ABI_ILP32F:
61   case RISCVABI::ABI_LP64F:
62     return CSR_ILP32F_LP64F_SaveList;
63   case RISCVABI::ABI_ILP32D:
64   case RISCVABI::ABI_LP64D:
65     return CSR_ILP32D_LP64D_SaveList;
66   }
67 }
68 
69 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
70   const RISCVFrameLowering *TFI = getFrameLowering(MF);
71   BitVector Reserved(getNumRegs());
72 
73   // Mark any registers requested to be reserved as such
74   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
75     if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
76       markSuperRegs(Reserved, Reg);
77   }
78 
79   // Use markSuperRegs to ensure any register aliases are also reserved
80   markSuperRegs(Reserved, RISCV::X0); // zero
81   markSuperRegs(Reserved, RISCV::X2); // sp
82   markSuperRegs(Reserved, RISCV::X3); // gp
83   markSuperRegs(Reserved, RISCV::X4); // tp
84   if (TFI->hasFP(MF))
85     markSuperRegs(Reserved, RISCV::X8); // fp
86   // Reserve the base register if we need to realign the stack and allocate
87   // variable-sized objects at runtime.
88   if (TFI->hasBP(MF))
89     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
90   assert(checkAllSuperRegsMarked(Reserved));
91   return Reserved;
92 }
93 
94 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
95                                          MCRegister PhysReg) const {
96   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
97 }
98 
99 bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
100   return PhysReg == RISCV::X0;
101 }
102 
103 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
104   return CSR_NoRegs_RegMask;
105 }
106 
107 // Frame indexes representing locations of CSRs which are given a fixed location
108 // by save/restore libcalls.
109 static const std::map<unsigned, int> FixedCSRFIMap = {
110   {/*ra*/  RISCV::X1,   -1},
111   {/*s0*/  RISCV::X8,   -2},
112   {/*s1*/  RISCV::X9,   -3},
113   {/*s2*/  RISCV::X18,  -4},
114   {/*s3*/  RISCV::X19,  -5},
115   {/*s4*/  RISCV::X20,  -6},
116   {/*s5*/  RISCV::X21,  -7},
117   {/*s6*/  RISCV::X22,  -8},
118   {/*s7*/  RISCV::X23,  -9},
119   {/*s8*/  RISCV::X24,  -10},
120   {/*s9*/  RISCV::X25,  -11},
121   {/*s10*/ RISCV::X26,  -12},
122   {/*s11*/ RISCV::X27,  -13}
123 };
124 
125 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
126                                              Register Reg,
127                                              int &FrameIdx) const {
128   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
129   if (!RVFI->useSaveRestoreLibCalls())
130     return false;
131 
132   auto FII = FixedCSRFIMap.find(Reg);
133   if (FII == FixedCSRFIMap.end())
134     return false;
135 
136   FrameIdx = FII->second;
137   return true;
138 }
139 
140 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
141                                             int SPAdj, unsigned FIOperandNum,
142                                             RegScavenger *RS) const {
143   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
144 
145   MachineInstr &MI = *II;
146   MachineFunction &MF = *MI.getParent()->getParent();
147   MachineRegisterInfo &MRI = MF.getRegInfo();
148   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
149   DebugLoc DL = MI.getDebugLoc();
150 
151   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
152   Register FrameReg;
153   int Offset =
154       getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
155       MI.getOperand(FIOperandNum + 1).getImm();
156 
157   if (!isInt<32>(Offset)) {
158     report_fatal_error(
159         "Frame offsets outside of the signed 32-bit range not supported");
160   }
161 
162   MachineBasicBlock &MBB = *MI.getParent();
163   bool FrameRegIsKill = false;
164 
165   if (!isInt<12>(Offset)) {
166     assert(isInt<32>(Offset) && "Int32 expected");
167     // The offset won't fit in an immediate, so use a scratch register instead
168     // Modify Offset and FrameReg appropriately
169     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
170     TII->movImm(MBB, II, DL, ScratchReg, Offset);
171     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
172         .addReg(FrameReg)
173         .addReg(ScratchReg, RegState::Kill);
174     Offset = 0;
175     FrameReg = ScratchReg;
176     FrameRegIsKill = true;
177   }
178 
179   MI.getOperand(FIOperandNum)
180       .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
181   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
182 }
183 
184 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
185   const TargetFrameLowering *TFI = getFrameLowering(MF);
186   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
187 }
188 
189 const uint32_t *
190 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
191                                         CallingConv::ID /*CC*/) const {
192   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
193 
194   switch (Subtarget.getTargetABI()) {
195   default:
196     llvm_unreachable("Unrecognized ABI");
197   case RISCVABI::ABI_ILP32:
198   case RISCVABI::ABI_LP64:
199     return CSR_ILP32_LP64_RegMask;
200   case RISCVABI::ABI_ILP32F:
201   case RISCVABI::ABI_LP64F:
202     return CSR_ILP32F_LP64F_RegMask;
203   case RISCVABI::ABI_ILP32D:
204   case RISCVABI::ABI_LP64D:
205     return CSR_ILP32D_LP64D_RegMask;
206   }
207 }
208