1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVMachineFunctionInfo.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "RISCVGenRegisterInfo.inc"
27 
28 using namespace llvm;
29 
30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
32 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
33 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
34               "Register list not consecutive");
35 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
36 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
37               "Register list not consecutive");
38 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
39 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
40 
41 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
42     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
43                            /*PC*/0, HwMode) {}
44 
45 const MCPhysReg *
46 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
47   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
48   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
49     return CSR_NoRegs_SaveList;
50   if (MF->getFunction().hasFnAttribute("interrupt")) {
51     if (Subtarget.hasStdExtD())
52       return CSR_XLEN_F64_Interrupt_SaveList;
53     if (Subtarget.hasStdExtF())
54       return CSR_XLEN_F32_Interrupt_SaveList;
55     return CSR_Interrupt_SaveList;
56   }
57 
58   switch (Subtarget.getTargetABI()) {
59   default:
60     llvm_unreachable("Unrecognized ABI");
61   case RISCVABI::ABI_ILP32:
62   case RISCVABI::ABI_LP64:
63     return CSR_ILP32_LP64_SaveList;
64   case RISCVABI::ABI_ILP32F:
65   case RISCVABI::ABI_LP64F:
66     return CSR_ILP32F_LP64F_SaveList;
67   case RISCVABI::ABI_ILP32D:
68   case RISCVABI::ABI_LP64D:
69     return CSR_ILP32D_LP64D_SaveList;
70   }
71 }
72 
73 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
74   const RISCVFrameLowering *TFI = getFrameLowering(MF);
75   BitVector Reserved(getNumRegs());
76 
77   // Mark any registers requested to be reserved as such
78   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
79     if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
80       markSuperRegs(Reserved, Reg);
81   }
82 
83   // Use markSuperRegs to ensure any register aliases are also reserved
84   markSuperRegs(Reserved, RISCV::X0); // zero
85   markSuperRegs(Reserved, RISCV::X2); // sp
86   markSuperRegs(Reserved, RISCV::X3); // gp
87   markSuperRegs(Reserved, RISCV::X4); // tp
88   if (TFI->hasFP(MF))
89     markSuperRegs(Reserved, RISCV::X8); // fp
90   // Reserve the base register if we need to realign the stack and allocate
91   // variable-sized objects at runtime.
92   if (TFI->hasBP(MF))
93     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
94   assert(checkAllSuperRegsMarked(Reserved));
95   return Reserved;
96 }
97 
98 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
99                                          MCRegister PhysReg) const {
100   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
101 }
102 
103 bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
104   return PhysReg == RISCV::X0;
105 }
106 
107 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
108   return CSR_NoRegs_RegMask;
109 }
110 
111 // Frame indexes representing locations of CSRs which are given a fixed location
112 // by save/restore libcalls.
113 static const std::map<unsigned, int> FixedCSRFIMap = {
114   {/*ra*/  RISCV::X1,   -1},
115   {/*s0*/  RISCV::X8,   -2},
116   {/*s1*/  RISCV::X9,   -3},
117   {/*s2*/  RISCV::X18,  -4},
118   {/*s3*/  RISCV::X19,  -5},
119   {/*s4*/  RISCV::X20,  -6},
120   {/*s5*/  RISCV::X21,  -7},
121   {/*s6*/  RISCV::X22,  -8},
122   {/*s7*/  RISCV::X23,  -9},
123   {/*s8*/  RISCV::X24,  -10},
124   {/*s9*/  RISCV::X25,  -11},
125   {/*s10*/ RISCV::X26,  -12},
126   {/*s11*/ RISCV::X27,  -13}
127 };
128 
129 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
130                                              Register Reg,
131                                              int &FrameIdx) const {
132   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
133   if (!RVFI->useSaveRestoreLibCalls(MF))
134     return false;
135 
136   auto FII = FixedCSRFIMap.find(Reg);
137   if (FII == FixedCSRFIMap.end())
138     return false;
139 
140   FrameIdx = FII->second;
141   return true;
142 }
143 
144 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
145                                             int SPAdj, unsigned FIOperandNum,
146                                             RegScavenger *RS) const {
147   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
148 
149   MachineInstr &MI = *II;
150   MachineFunction &MF = *MI.getParent()->getParent();
151   MachineRegisterInfo &MRI = MF.getRegInfo();
152   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
153   DebugLoc DL = MI.getDebugLoc();
154 
155   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
156   Register FrameReg;
157   int Offset = getFrameLowering(MF)
158                    ->getFrameIndexReference(MF, FrameIndex, FrameReg)
159                    .getFixed() +
160                MI.getOperand(FIOperandNum + 1).getImm();
161 
162   if (!isInt<32>(Offset)) {
163     report_fatal_error(
164         "Frame offsets outside of the signed 32-bit range not supported");
165   }
166 
167   MachineBasicBlock &MBB = *MI.getParent();
168   bool FrameRegIsKill = false;
169 
170   if (!isInt<12>(Offset)) {
171     assert(isInt<32>(Offset) && "Int32 expected");
172     // The offset won't fit in an immediate, so use a scratch register instead
173     // Modify Offset and FrameReg appropriately
174     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
175     TII->movImm(MBB, II, DL, ScratchReg, Offset);
176     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
177         .addReg(FrameReg)
178         .addReg(ScratchReg, RegState::Kill);
179     Offset = 0;
180     FrameReg = ScratchReg;
181     FrameRegIsKill = true;
182   }
183 
184   MI.getOperand(FIOperandNum)
185       .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
186   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
187 }
188 
189 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
190   const TargetFrameLowering *TFI = getFrameLowering(MF);
191   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
192 }
193 
194 const uint32_t *
195 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
196                                         CallingConv::ID CC) const {
197   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
198 
199   if (CC == CallingConv::GHC)
200     return CSR_NoRegs_RegMask;
201   switch (Subtarget.getTargetABI()) {
202   default:
203     llvm_unreachable("Unrecognized ABI");
204   case RISCVABI::ABI_ILP32:
205   case RISCVABI::ABI_LP64:
206     return CSR_ILP32_LP64_RegMask;
207   case RISCVABI::ABI_ILP32F:
208   case RISCVABI::ABI_LP64F:
209     return CSR_ILP32F_LP64F_RegMask;
210   case RISCVABI::ABI_ILP32D:
211   case RISCVABI::ABI_LP64D:
212     return CSR_ILP32D_LP64D_RegMask;
213   }
214 }
215