1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the RISCV implementation of the TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "RISCVRegisterInfo.h" 15 #include "RISCV.h" 16 #include "RISCVSubtarget.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/RegisterScavenging.h" 21 #include "llvm/CodeGen/TargetFrameLowering.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/Support/ErrorHandling.h" 24 25 #define GET_REGINFO_TARGET_DESC 26 #include "RISCVGenRegisterInfo.inc" 27 28 using namespace llvm; 29 30 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) 31 : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0, 32 /*PC*/0, HwMode) {} 33 34 const MCPhysReg * 35 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 36 return CSR_SaveList; 37 } 38 39 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 40 BitVector Reserved(getNumRegs()); 41 42 // Use markSuperRegs to ensure any register aliases are also reserved 43 markSuperRegs(Reserved, RISCV::X0); // zero 44 markSuperRegs(Reserved, RISCV::X1); // ra 45 markSuperRegs(Reserved, RISCV::X2); // sp 46 markSuperRegs(Reserved, RISCV::X3); // gp 47 markSuperRegs(Reserved, RISCV::X4); // tp 48 markSuperRegs(Reserved, RISCV::X8); // fp 49 assert(checkAllSuperRegsMarked(Reserved)); 50 return Reserved; 51 } 52 53 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { 54 return CSR_NoRegs_RegMask; 55 } 56 57 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 58 int SPAdj, unsigned FIOperandNum, 59 RegScavenger *RS) const { 60 assert(SPAdj == 0 && "Unexpected non-zero SPAdj value"); 61 62 MachineInstr &MI = *II; 63 MachineFunction &MF = *MI.getParent()->getParent(); 64 MachineRegisterInfo &MRI = MF.getRegInfo(); 65 const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo(); 66 DebugLoc DL = MI.getDebugLoc(); 67 68 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 69 unsigned FrameReg; 70 int Offset = 71 getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) + 72 MI.getOperand(FIOperandNum + 1).getImm(); 73 74 if (!isInt<32>(Offset)) { 75 report_fatal_error( 76 "Frame offsets outside of the signed 32-bit range not supported"); 77 } 78 79 MachineBasicBlock &MBB = *MI.getParent(); 80 bool FrameRegIsKill = false; 81 82 if (!isInt<12>(Offset)) { 83 assert(isInt<32>(Offset) && "Int32 expected"); 84 // The offset won't fit in an immediate, so use a scratch register instead 85 // Modify Offset and FrameReg appropriately 86 unsigned ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass); 87 TII->movImm32(MBB, II, DL, ScratchReg, Offset); 88 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg) 89 .addReg(FrameReg) 90 .addReg(ScratchReg, RegState::Kill); 91 Offset = 0; 92 FrameReg = ScratchReg; 93 FrameRegIsKill = true; 94 } 95 96 MI.getOperand(FIOperandNum) 97 .ChangeToRegister(FrameReg, false, false, FrameRegIsKill); 98 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 99 } 100 101 unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 102 const TargetFrameLowering *TFI = getFrameLowering(MF); 103 return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2; 104 } 105 106 const uint32_t * 107 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & /*MF*/, 108 CallingConv::ID /*CC*/) const { 109 return CSR_RegMask; 110 } 111