1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the RISCV implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "RISCVRegisterInfo.h"
15 #include "RISCV.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Target/TargetFrameLowering.h"
23 #include "llvm/Target/TargetInstrInfo.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "RISCVGenRegisterInfo.inc"
27 
28 using namespace llvm;
29 
30 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
31     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
32                            /*PC*/0, HwMode) {}
33 
34 const MCPhysReg *
35 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
36   return CSR_SaveList;
37 }
38 
39 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
40   BitVector Reserved(getNumRegs());
41 
42   // Use markSuperRegs to ensure any register aliases are also reserved
43   markSuperRegs(Reserved, RISCV::X0); // zero
44   markSuperRegs(Reserved, RISCV::X1); // ra
45   markSuperRegs(Reserved, RISCV::X2); // sp
46   markSuperRegs(Reserved, RISCV::X3); // gp
47   markSuperRegs(Reserved, RISCV::X4); // tp
48   markSuperRegs(Reserved, RISCV::X8); // fp
49   assert(checkAllSuperRegsMarked(Reserved));
50   return Reserved;
51 }
52 
53 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
54                                             int SPAdj, unsigned FIOperandNum,
55                                             RegScavenger *RS) const {
56   report_fatal_error("Subroutines not supported yet");
57 }
58 
59 unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
60   return RISCV::X8;
61 }
62