1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVSubtarget.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/RegisterScavenging.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 
24 #define GET_REGINFO_TARGET_DESC
25 #include "RISCVGenRegisterInfo.inc"
26 
27 using namespace llvm;
28 
29 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
30 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
31 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
32 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
33               "Register list not consecutive");
34 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
35 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
36               "Register list not consecutive");
37 
38 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
39     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
40                            /*PC*/0, HwMode) {}
41 
42 const MCPhysReg *
43 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
44   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
45   if (MF->getFunction().hasFnAttribute("interrupt")) {
46     if (Subtarget.hasStdExtD())
47       return CSR_XLEN_F64_Interrupt_SaveList;
48     if (Subtarget.hasStdExtF())
49       return CSR_XLEN_F32_Interrupt_SaveList;
50     return CSR_Interrupt_SaveList;
51   }
52 
53   switch (Subtarget.getTargetABI()) {
54   default:
55     llvm_unreachable("Unrecognized ABI");
56   case RISCVABI::ABI_ILP32:
57   case RISCVABI::ABI_LP64:
58     return CSR_ILP32_LP64_SaveList;
59   case RISCVABI::ABI_ILP32F:
60   case RISCVABI::ABI_LP64F:
61     return CSR_ILP32F_LP64F_SaveList;
62   case RISCVABI::ABI_ILP32D:
63   case RISCVABI::ABI_LP64D:
64     return CSR_ILP32D_LP64D_SaveList;
65   }
66 }
67 
68 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
69   const TargetFrameLowering *TFI = getFrameLowering(MF);
70   BitVector Reserved(getNumRegs());
71 
72   // Mark any registers requested to be reserved as such
73   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
74     if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
75       markSuperRegs(Reserved, Reg);
76   }
77 
78   // Use markSuperRegs to ensure any register aliases are also reserved
79   markSuperRegs(Reserved, RISCV::X0); // zero
80   markSuperRegs(Reserved, RISCV::X2); // sp
81   markSuperRegs(Reserved, RISCV::X3); // gp
82   markSuperRegs(Reserved, RISCV::X4); // tp
83   if (TFI->hasFP(MF))
84     markSuperRegs(Reserved, RISCV::X8); // fp
85   assert(checkAllSuperRegsMarked(Reserved));
86   return Reserved;
87 }
88 
89 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
90                                          unsigned PhysReg) const {
91   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
92 }
93 
94 bool RISCVRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
95   return PhysReg == RISCV::X0;
96 }
97 
98 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
99   return CSR_NoRegs_RegMask;
100 }
101 
102 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
103                                             int SPAdj, unsigned FIOperandNum,
104                                             RegScavenger *RS) const {
105   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
106 
107   MachineInstr &MI = *II;
108   MachineFunction &MF = *MI.getParent()->getParent();
109   MachineRegisterInfo &MRI = MF.getRegInfo();
110   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
111   DebugLoc DL = MI.getDebugLoc();
112 
113   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
114   unsigned FrameReg;
115   int Offset =
116       getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
117       MI.getOperand(FIOperandNum + 1).getImm();
118 
119   if (!isInt<32>(Offset)) {
120     report_fatal_error(
121         "Frame offsets outside of the signed 32-bit range not supported");
122   }
123 
124   MachineBasicBlock &MBB = *MI.getParent();
125   bool FrameRegIsKill = false;
126 
127   if (!isInt<12>(Offset)) {
128     assert(isInt<32>(Offset) && "Int32 expected");
129     // The offset won't fit in an immediate, so use a scratch register instead
130     // Modify Offset and FrameReg appropriately
131     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
132     TII->movImm(MBB, II, DL, ScratchReg, Offset);
133     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
134         .addReg(FrameReg)
135         .addReg(ScratchReg, RegState::Kill);
136     Offset = 0;
137     FrameReg = ScratchReg;
138     FrameRegIsKill = true;
139   }
140 
141   MI.getOperand(FIOperandNum)
142       .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
143   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
144 }
145 
146 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
147   const TargetFrameLowering *TFI = getFrameLowering(MF);
148   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
149 }
150 
151 const uint32_t *
152 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
153                                         CallingConv::ID /*CC*/) const {
154   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
155   if (MF.getFunction().hasFnAttribute("interrupt")) {
156     if (Subtarget.hasStdExtD())
157       return CSR_XLEN_F64_Interrupt_RegMask;
158     if (Subtarget.hasStdExtF())
159       return CSR_XLEN_F32_Interrupt_RegMask;
160     return CSR_Interrupt_RegMask;
161   }
162 
163   switch (Subtarget.getTargetABI()) {
164   default:
165     llvm_unreachable("Unrecognized ABI");
166   case RISCVABI::ABI_ILP32:
167   case RISCVABI::ABI_LP64:
168     return CSR_ILP32_LP64_RegMask;
169   case RISCVABI::ABI_ILP32F:
170   case RISCVABI::ABI_LP64F:
171     return CSR_ILP32F_LP64F_RegMask;
172   case RISCVABI::ABI_ILP32D:
173   case RISCVABI::ABI_LP64D:
174     return CSR_ILP32D_LP64D_RegMask;
175   }
176 }
177