1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVMachineFunctionInfo.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "RISCVGenRegisterInfo.inc"
27 
28 using namespace llvm;
29 
30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
32 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
33 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
34               "Register list not consecutive");
35 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
36 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
37               "Register list not consecutive");
38 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
39 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
40 
41 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
42     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
43                            /*PC*/0, HwMode) {}
44 
45 const MCPhysReg *
46 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
47   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
48   if (MF->getFunction().hasFnAttribute("interrupt")) {
49     if (Subtarget.hasStdExtD())
50       return CSR_XLEN_F64_Interrupt_SaveList;
51     if (Subtarget.hasStdExtF())
52       return CSR_XLEN_F32_Interrupt_SaveList;
53     return CSR_Interrupt_SaveList;
54   }
55 
56   switch (Subtarget.getTargetABI()) {
57   default:
58     llvm_unreachable("Unrecognized ABI");
59   case RISCVABI::ABI_ILP32:
60   case RISCVABI::ABI_LP64:
61     return CSR_ILP32_LP64_SaveList;
62   case RISCVABI::ABI_ILP32F:
63   case RISCVABI::ABI_LP64F:
64     return CSR_ILP32F_LP64F_SaveList;
65   case RISCVABI::ABI_ILP32D:
66   case RISCVABI::ABI_LP64D:
67     return CSR_ILP32D_LP64D_SaveList;
68   }
69 }
70 
71 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
72   const RISCVFrameLowering *TFI = getFrameLowering(MF);
73   BitVector Reserved(getNumRegs());
74 
75   // Mark any registers requested to be reserved as such
76   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
77     if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
78       markSuperRegs(Reserved, Reg);
79   }
80 
81   // Use markSuperRegs to ensure any register aliases are also reserved
82   markSuperRegs(Reserved, RISCV::X0); // zero
83   markSuperRegs(Reserved, RISCV::X2); // sp
84   markSuperRegs(Reserved, RISCV::X3); // gp
85   markSuperRegs(Reserved, RISCV::X4); // tp
86   if (TFI->hasFP(MF))
87     markSuperRegs(Reserved, RISCV::X8); // fp
88   // Reserve the base register if we need to realign the stack and allocate
89   // variable-sized objects at runtime.
90   if (TFI->hasBP(MF))
91     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
92   assert(checkAllSuperRegsMarked(Reserved));
93   return Reserved;
94 }
95 
96 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
97                                          MCRegister PhysReg) const {
98   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
99 }
100 
101 bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
102   return PhysReg == RISCV::X0;
103 }
104 
105 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
106   return CSR_NoRegs_RegMask;
107 }
108 
109 // Frame indexes representing locations of CSRs which are given a fixed location
110 // by save/restore libcalls.
111 static const std::map<unsigned, int> FixedCSRFIMap = {
112   {/*ra*/  RISCV::X1,   -1},
113   {/*s0*/  RISCV::X8,   -2},
114   {/*s1*/  RISCV::X9,   -3},
115   {/*s2*/  RISCV::X18,  -4},
116   {/*s3*/  RISCV::X19,  -5},
117   {/*s4*/  RISCV::X20,  -6},
118   {/*s5*/  RISCV::X21,  -7},
119   {/*s6*/  RISCV::X22,  -8},
120   {/*s7*/  RISCV::X23,  -9},
121   {/*s8*/  RISCV::X24,  -10},
122   {/*s9*/  RISCV::X25,  -11},
123   {/*s10*/ RISCV::X26,  -12},
124   {/*s11*/ RISCV::X27,  -13}
125 };
126 
127 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
128                                              Register Reg,
129                                              int &FrameIdx) const {
130   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
131   if (!RVFI->useSaveRestoreLibCalls(MF))
132     return false;
133 
134   auto FII = FixedCSRFIMap.find(Reg);
135   if (FII == FixedCSRFIMap.end())
136     return false;
137 
138   FrameIdx = FII->second;
139   return true;
140 }
141 
142 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
143                                             int SPAdj, unsigned FIOperandNum,
144                                             RegScavenger *RS) const {
145   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
146 
147   MachineInstr &MI = *II;
148   MachineFunction &MF = *MI.getParent()->getParent();
149   MachineRegisterInfo &MRI = MF.getRegInfo();
150   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
151   DebugLoc DL = MI.getDebugLoc();
152 
153   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
154   Register FrameReg;
155   int Offset = getFrameLowering(MF)
156                    ->getFrameIndexReference(MF, FrameIndex, FrameReg)
157                    .getFixed() +
158                MI.getOperand(FIOperandNum + 1).getImm();
159 
160   if (!isInt<32>(Offset)) {
161     report_fatal_error(
162         "Frame offsets outside of the signed 32-bit range not supported");
163   }
164 
165   MachineBasicBlock &MBB = *MI.getParent();
166   bool FrameRegIsKill = false;
167 
168   if (!isInt<12>(Offset)) {
169     assert(isInt<32>(Offset) && "Int32 expected");
170     // The offset won't fit in an immediate, so use a scratch register instead
171     // Modify Offset and FrameReg appropriately
172     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
173     TII->movImm(MBB, II, DL, ScratchReg, Offset);
174     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
175         .addReg(FrameReg)
176         .addReg(ScratchReg, RegState::Kill);
177     Offset = 0;
178     FrameReg = ScratchReg;
179     FrameRegIsKill = true;
180   }
181 
182   MI.getOperand(FIOperandNum)
183       .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
184   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
185 }
186 
187 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
188   const TargetFrameLowering *TFI = getFrameLowering(MF);
189   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
190 }
191 
192 const uint32_t *
193 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
194                                         CallingConv::ID /*CC*/) const {
195   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
196 
197   switch (Subtarget.getTargetABI()) {
198   default:
199     llvm_unreachable("Unrecognized ABI");
200   case RISCVABI::ABI_ILP32:
201   case RISCVABI::ABI_LP64:
202     return CSR_ILP32_LP64_RegMask;
203   case RISCVABI::ABI_ILP32F:
204   case RISCVABI::ABI_LP64F:
205     return CSR_ILP32F_LP64F_RegMask;
206   case RISCVABI::ABI_ILP32D:
207   case RISCVABI::ABI_LP64D:
208     return CSR_ILP32D_LP64D_RegMask;
209   }
210 }
211