1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVMachineFunctionInfo.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "RISCVGenRegisterInfo.inc"
27 
28 using namespace llvm;
29 
30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
32 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
33 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
34               "Register list not consecutive");
35 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
36 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
37               "Register list not consecutive");
38 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
39 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
40               "Register list not consecutive");
41 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
42 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
43 
44 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
45     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
46                            /*PC*/0, HwMode) {}
47 
48 const MCPhysReg *
49 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
50   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
51   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
52     return CSR_NoRegs_SaveList;
53   if (MF->getFunction().hasFnAttribute("interrupt")) {
54     if (Subtarget.hasStdExtD())
55       return CSR_XLEN_F64_Interrupt_SaveList;
56     if (Subtarget.hasStdExtF())
57       return CSR_XLEN_F32_Interrupt_SaveList;
58     return CSR_Interrupt_SaveList;
59   }
60 
61   switch (Subtarget.getTargetABI()) {
62   default:
63     llvm_unreachable("Unrecognized ABI");
64   case RISCVABI::ABI_ILP32:
65   case RISCVABI::ABI_LP64:
66     return CSR_ILP32_LP64_SaveList;
67   case RISCVABI::ABI_ILP32F:
68   case RISCVABI::ABI_LP64F:
69     return CSR_ILP32F_LP64F_SaveList;
70   case RISCVABI::ABI_ILP32D:
71   case RISCVABI::ABI_LP64D:
72     return CSR_ILP32D_LP64D_SaveList;
73   }
74 }
75 
76 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
77   const RISCVFrameLowering *TFI = getFrameLowering(MF);
78   BitVector Reserved(getNumRegs());
79 
80   // Mark any registers requested to be reserved as such
81   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
82     if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
83       markSuperRegs(Reserved, Reg);
84   }
85 
86   // Use markSuperRegs to ensure any register aliases are also reserved
87   markSuperRegs(Reserved, RISCV::X0); // zero
88   markSuperRegs(Reserved, RISCV::X2); // sp
89   markSuperRegs(Reserved, RISCV::X3); // gp
90   markSuperRegs(Reserved, RISCV::X4); // tp
91   if (TFI->hasFP(MF))
92     markSuperRegs(Reserved, RISCV::X8); // fp
93   // Reserve the base register if we need to realign the stack and allocate
94   // variable-sized objects at runtime.
95   if (TFI->hasBP(MF))
96     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
97 
98   // V registers for code generation. We handle them manually.
99   markSuperRegs(Reserved, RISCV::VL);
100   markSuperRegs(Reserved, RISCV::VTYPE);
101 
102   assert(checkAllSuperRegsMarked(Reserved));
103   return Reserved;
104 }
105 
106 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
107                                          MCRegister PhysReg) const {
108   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
109 }
110 
111 bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
112   return PhysReg == RISCV::X0;
113 }
114 
115 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
116   return CSR_NoRegs_RegMask;
117 }
118 
119 // Frame indexes representing locations of CSRs which are given a fixed location
120 // by save/restore libcalls.
121 static const std::map<unsigned, int> FixedCSRFIMap = {
122   {/*ra*/  RISCV::X1,   -1},
123   {/*s0*/  RISCV::X8,   -2},
124   {/*s1*/  RISCV::X9,   -3},
125   {/*s2*/  RISCV::X18,  -4},
126   {/*s3*/  RISCV::X19,  -5},
127   {/*s4*/  RISCV::X20,  -6},
128   {/*s5*/  RISCV::X21,  -7},
129   {/*s6*/  RISCV::X22,  -8},
130   {/*s7*/  RISCV::X23,  -9},
131   {/*s8*/  RISCV::X24,  -10},
132   {/*s9*/  RISCV::X25,  -11},
133   {/*s10*/ RISCV::X26,  -12},
134   {/*s11*/ RISCV::X27,  -13}
135 };
136 
137 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
138                                              Register Reg,
139                                              int &FrameIdx) const {
140   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
141   if (!RVFI->useSaveRestoreLibCalls(MF))
142     return false;
143 
144   auto FII = FixedCSRFIMap.find(Reg);
145   if (FII == FixedCSRFIMap.end())
146     return false;
147 
148   FrameIdx = FII->second;
149   return true;
150 }
151 
152 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
153                                             int SPAdj, unsigned FIOperandNum,
154                                             RegScavenger *RS) const {
155   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
156 
157   MachineInstr &MI = *II;
158   MachineFunction &MF = *MI.getParent()->getParent();
159   MachineRegisterInfo &MRI = MF.getRegInfo();
160   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
161   DebugLoc DL = MI.getDebugLoc();
162 
163   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
164   Register FrameReg;
165   int Offset = getFrameLowering(MF)
166                    ->getFrameIndexReference(MF, FrameIndex, FrameReg)
167                    .getFixed() +
168                MI.getOperand(FIOperandNum + 1).getImm();
169 
170   if (!isInt<32>(Offset)) {
171     report_fatal_error(
172         "Frame offsets outside of the signed 32-bit range not supported");
173   }
174 
175   MachineBasicBlock &MBB = *MI.getParent();
176   bool FrameRegIsKill = false;
177 
178   if (!isInt<12>(Offset)) {
179     assert(isInt<32>(Offset) && "Int32 expected");
180     // The offset won't fit in an immediate, so use a scratch register instead
181     // Modify Offset and FrameReg appropriately
182     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
183     TII->movImm(MBB, II, DL, ScratchReg, Offset);
184     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
185         .addReg(FrameReg)
186         .addReg(ScratchReg, RegState::Kill);
187     Offset = 0;
188     FrameReg = ScratchReg;
189     FrameRegIsKill = true;
190   }
191 
192   MI.getOperand(FIOperandNum)
193       .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
194   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
195 }
196 
197 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
198   const TargetFrameLowering *TFI = getFrameLowering(MF);
199   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
200 }
201 
202 const uint32_t *
203 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
204                                         CallingConv::ID CC) const {
205   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
206 
207   if (CC == CallingConv::GHC)
208     return CSR_NoRegs_RegMask;
209   switch (Subtarget.getTargetABI()) {
210   default:
211     llvm_unreachable("Unrecognized ABI");
212   case RISCVABI::ABI_ILP32:
213   case RISCVABI::ABI_LP64:
214     return CSR_ILP32_LP64_RegMask;
215   case RISCVABI::ABI_ILP32F:
216   case RISCVABI::ABI_LP64F:
217     return CSR_ILP32F_LP64F_RegMask;
218   case RISCVABI::ABI_ILP32D:
219   case RISCVABI::ABI_LP64D:
220     return CSR_ILP32D_LP64D_RegMask;
221   }
222 }
223