1 //===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the RISCV implementation of the TargetRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "RISCVRegisterInfo.h"
14 #include "RISCV.h"
15 #include "RISCVMachineFunctionInfo.h"
16 #include "RISCVSubtarget.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/RegisterScavenging.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/Support/ErrorHandling.h"
24 
25 #define GET_REGINFO_TARGET_DESC
26 #include "RISCVGenRegisterInfo.inc"
27 
28 using namespace llvm;
29 
30 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
31 static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
32 static_assert(RISCV::F1_H == RISCV::F0_H + 1, "Register list not consecutive");
33 static_assert(RISCV::F31_H == RISCV::F0_H + 31,
34               "Register list not consecutive");
35 static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
36 static_assert(RISCV::F31_F == RISCV::F0_F + 31,
37               "Register list not consecutive");
38 static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
39 static_assert(RISCV::F31_D == RISCV::F0_D + 31,
40               "Register list not consecutive");
41 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
42 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
43 
44 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
45     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
46                            /*PC*/0, HwMode) {}
47 
48 const MCPhysReg *
49 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
50   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
51   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
52     return CSR_NoRegs_SaveList;
53   if (MF->getFunction().hasFnAttribute("interrupt")) {
54     if (Subtarget.hasStdExtD())
55       return CSR_XLEN_F64_Interrupt_SaveList;
56     if (Subtarget.hasStdExtF())
57       return CSR_XLEN_F32_Interrupt_SaveList;
58     return CSR_Interrupt_SaveList;
59   }
60 
61   switch (Subtarget.getTargetABI()) {
62   default:
63     llvm_unreachable("Unrecognized ABI");
64   case RISCVABI::ABI_ILP32:
65   case RISCVABI::ABI_LP64:
66     return CSR_ILP32_LP64_SaveList;
67   case RISCVABI::ABI_ILP32F:
68   case RISCVABI::ABI_LP64F:
69     return CSR_ILP32F_LP64F_SaveList;
70   case RISCVABI::ABI_ILP32D:
71   case RISCVABI::ABI_LP64D:
72     return CSR_ILP32D_LP64D_SaveList;
73   }
74 }
75 
76 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
77   const RISCVFrameLowering *TFI = getFrameLowering(MF);
78   BitVector Reserved(getNumRegs());
79 
80   // Mark any registers requested to be reserved as such
81   for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
82     if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
83       markSuperRegs(Reserved, Reg);
84   }
85 
86   // Use markSuperRegs to ensure any register aliases are also reserved
87   markSuperRegs(Reserved, RISCV::X0); // zero
88   markSuperRegs(Reserved, RISCV::X2); // sp
89   markSuperRegs(Reserved, RISCV::X3); // gp
90   markSuperRegs(Reserved, RISCV::X4); // tp
91   if (TFI->hasFP(MF))
92     markSuperRegs(Reserved, RISCV::X8); // fp
93   // Reserve the base register if we need to realign the stack and allocate
94   // variable-sized objects at runtime.
95   if (TFI->hasBP(MF))
96     markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
97 
98   // V registers for code generation. We handle them manually.
99   markSuperRegs(Reserved, RISCV::VL);
100   markSuperRegs(Reserved, RISCV::VTYPE);
101   markSuperRegs(Reserved, RISCV::VXSAT);
102   markSuperRegs(Reserved, RISCV::VXRM);
103 
104   // Floating point environment registers.
105   markSuperRegs(Reserved, RISCV::FRM);
106   markSuperRegs(Reserved, RISCV::FFLAGS);
107   markSuperRegs(Reserved, RISCV::FCSR);
108 
109   assert(checkAllSuperRegsMarked(Reserved));
110   return Reserved;
111 }
112 
113 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
114                                          MCRegister PhysReg) const {
115   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
116 }
117 
118 bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
119   return PhysReg == RISCV::X0;
120 }
121 
122 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
123   return CSR_NoRegs_RegMask;
124 }
125 
126 // Frame indexes representing locations of CSRs which are given a fixed location
127 // by save/restore libcalls.
128 static const std::map<unsigned, int> FixedCSRFIMap = {
129   {/*ra*/  RISCV::X1,   -1},
130   {/*s0*/  RISCV::X8,   -2},
131   {/*s1*/  RISCV::X9,   -3},
132   {/*s2*/  RISCV::X18,  -4},
133   {/*s3*/  RISCV::X19,  -5},
134   {/*s4*/  RISCV::X20,  -6},
135   {/*s5*/  RISCV::X21,  -7},
136   {/*s6*/  RISCV::X22,  -8},
137   {/*s7*/  RISCV::X23,  -9},
138   {/*s8*/  RISCV::X24,  -10},
139   {/*s9*/  RISCV::X25,  -11},
140   {/*s10*/ RISCV::X26,  -12},
141   {/*s11*/ RISCV::X27,  -13}
142 };
143 
144 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
145                                              Register Reg,
146                                              int &FrameIdx) const {
147   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
148   if (!RVFI->useSaveRestoreLibCalls(MF))
149     return false;
150 
151   auto FII = FixedCSRFIMap.find(Reg);
152   if (FII == FixedCSRFIMap.end())
153     return false;
154 
155   FrameIdx = FII->second;
156   return true;
157 }
158 
159 static bool isRVVWholeLoadStore(unsigned Opcode) {
160   switch (Opcode) {
161   default:
162     return false;
163   case RISCV::VS1R_V:
164   case RISCV::VS2R_V:
165   case RISCV::VS4R_V:
166   case RISCV::VS8R_V:
167   case RISCV::VL1RE8_V:
168   case RISCV::VL2RE8_V:
169   case RISCV::VL4RE8_V:
170   case RISCV::VL8RE8_V:
171   case RISCV::VL1RE16_V:
172   case RISCV::VL2RE16_V:
173   case RISCV::VL4RE16_V:
174   case RISCV::VL8RE16_V:
175   case RISCV::VL1RE32_V:
176   case RISCV::VL2RE32_V:
177   case RISCV::VL4RE32_V:
178   case RISCV::VL8RE32_V:
179   case RISCV::VL1RE64_V:
180   case RISCV::VL2RE64_V:
181   case RISCV::VL4RE64_V:
182   case RISCV::VL8RE64_V:
183     return true;
184   }
185 }
186 
187 void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
188                                             int SPAdj, unsigned FIOperandNum,
189                                             RegScavenger *RS) const {
190   assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
191 
192   MachineInstr &MI = *II;
193   MachineFunction &MF = *MI.getParent()->getParent();
194   MachineRegisterInfo &MRI = MF.getRegInfo();
195   const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
196   DebugLoc DL = MI.getDebugLoc();
197 
198   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
199   Register FrameReg;
200   StackOffset Offset =
201       getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg);
202   bool isRVV = RISCVVPseudosTable::getPseudoInfo(MI.getOpcode()) ||
203                isRVVWholeLoadStore(MI.getOpcode()) ||
204                TII->isRVVSpillForZvlsseg(MI.getOpcode());
205   if (!isRVV)
206     Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
207 
208   if (!isInt<32>(Offset.getFixed())) {
209     report_fatal_error(
210         "Frame offsets outside of the signed 32-bit range not supported");
211   }
212 
213   MachineBasicBlock &MBB = *MI.getParent();
214   bool FrameRegIsKill = false;
215 
216   if (!isInt<12>(Offset.getFixed())) {
217     // The offset won't fit in an immediate, so use a scratch register instead
218     // Modify Offset and FrameReg appropriately
219     Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
220     TII->movImm(MBB, II, DL, ScratchReg, Offset.getFixed());
221     if (MI.getOpcode() == RISCV::ADDI && !Offset.getScalable()) {
222       BuildMI(MBB, II, DL, TII->get(RISCV::ADD), MI.getOperand(0).getReg())
223         .addReg(FrameReg)
224         .addReg(ScratchReg, RegState::Kill);
225       MI.eraseFromParent();
226       return;
227     }
228     BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
229         .addReg(FrameReg)
230         .addReg(ScratchReg, RegState::Kill);
231     Offset = StackOffset::get(0, Offset.getScalable());
232     FrameReg = ScratchReg;
233     FrameRegIsKill = true;
234   }
235 
236   if (!Offset.getScalable()) {
237     // Offset = (fixed offset, 0)
238     MI.getOperand(FIOperandNum)
239         .ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
240     if (!isRVV)
241       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
242     else {
243       if (Offset.getFixed()) {
244         Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
245         BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), ScratchReg)
246           .addReg(FrameReg, getKillRegState(FrameRegIsKill))
247           .addImm(Offset.getFixed());
248         MI.getOperand(FIOperandNum)
249           .ChangeToRegister(ScratchReg, false, false, true);
250       }
251     }
252   } else {
253     // Offset = (fixed offset, scalable offset)
254     unsigned Opc = RISCV::ADD;
255     int64_t ScalableValue = Offset.getScalable();
256     if (ScalableValue < 0) {
257       ScalableValue = -ScalableValue;
258       Opc = RISCV::SUB;
259     }
260 
261     // 1. Get vlenb && multiply vlen with number of vector register.
262     Register FactorRegister =
263         TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
264 
265     // 2. Calculate address: FrameReg + result of multiply
266     if (MI.getOpcode() == RISCV::ADDI && !Offset.getFixed()) {
267       BuildMI(MBB, II, DL, TII->get(Opc), MI.getOperand(0).getReg())
268           .addReg(FrameReg, getKillRegState(FrameRegIsKill))
269           .addReg(FactorRegister, RegState::Kill);
270       MI.eraseFromParent();
271       return;
272     }
273     Register VL = MRI.createVirtualRegister(&RISCV::GPRRegClass);
274     BuildMI(MBB, II, DL, TII->get(Opc), VL)
275         .addReg(FrameReg, getKillRegState(FrameRegIsKill))
276         .addReg(FactorRegister, RegState::Kill);
277 
278     if (isRVV && Offset.getFixed()) {
279       // Scalable load/store has no immediate argument. We need to add the
280       // fixed part into the load/store base address.
281       BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), VL)
282           .addReg(VL)
283           .addImm(Offset.getFixed());
284     }
285 
286     // 3. Replace address register with calculated address register
287     MI.getOperand(FIOperandNum).ChangeToRegister(VL, false, false, true);
288     if (!isRVV)
289       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset.getFixed());
290   }
291 
292   MachineFrameInfo &MFI = MF.getFrameInfo();
293   auto ZvlssegInfo = TII->isRVVSpillForZvlsseg(MI.getOpcode());
294   if (ZvlssegInfo) {
295     int64_t ScalableValue = MFI.getObjectSize(FrameIndex) / ZvlssegInfo->first;
296     Register FactorRegister =
297         TII->getVLENFactoredAmount(MF, MBB, II, ScalableValue);
298     MI.getOperand(FIOperandNum + 1)
299         .ChangeToRegister(FactorRegister, /*isDef=*/false);
300   }
301 }
302 
303 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
304   const TargetFrameLowering *TFI = getFrameLowering(MF);
305   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
306 }
307 
308 const uint32_t *
309 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
310                                         CallingConv::ID CC) const {
311   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
312 
313   if (CC == CallingConv::GHC)
314     return CSR_NoRegs_RegMask;
315   switch (Subtarget.getTargetABI()) {
316   default:
317     llvm_unreachable("Unrecognized ABI");
318   case RISCVABI::ABI_ILP32:
319   case RISCVABI::ABI_LP64:
320     return CSR_ILP32_LP64_RegMask;
321   case RISCVABI::ABI_ILP32F:
322   case RISCVABI::ABI_LP64F:
323     return CSR_ILP32F_LP64F_RegMask;
324   case RISCVABI::ABI_ILP32D:
325   case RISCVABI::ABI_LP64D:
326     return CSR_ILP32D_LP64D_RegMask;
327   }
328 }
329 
330 const TargetRegisterClass *
331 RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
332                                              const MachineFunction &) const {
333   if (RC == &RISCV::VMV0RegClass)
334     return &RISCV::VRRegClass;
335   return RC;
336 }
337