1 //===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains code to lower RISCV MachineInstrs to their corresponding
11 // MCInst records.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "RISCV.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 
25 using namespace llvm;
26 
27 void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI,
28                                           MCInst &OutMI) {
29   OutMI.setOpcode(MI->getOpcode());
30 
31   for (const MachineOperand &MO : MI->operands()) {
32     MCOperand MCOp;
33     switch (MO.getType()) {
34     default:
35       report_fatal_error(
36           "LowerRISCVMachineInstrToMCInst: unknown operand type");
37     case MachineOperand::MO_Register:
38       // Ignore all implicit register operands.
39       if (MO.isImplicit())
40         continue;
41       MCOp = MCOperand::createReg(MO.getReg());
42       break;
43     case MachineOperand::MO_Immediate:
44       MCOp = MCOperand::createImm(MO.getImm());
45       break;
46     }
47 
48     OutMI.addOperand(MCOp);
49   }
50 }
51