1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// version 1.0. 12/// 13/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 14/// 15/// Note: the patterns for RVV intrinsics are found in 16/// RISCVInstrInfoVPseudos.td. 17/// 18//===----------------------------------------------------------------------===// 19 20//===----------------------------------------------------------------------===// 21// Helpers to define the VL patterns. 22//===----------------------------------------------------------------------===// 23 24def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 25 SDTCisSameAs<0, 2>, 26 SDTCisVec<0>, SDTCisInt<0>, 27 SDTCVecEltisVT<3, i1>, 28 SDTCisSameNumEltsAs<0, 3>, 29 SDTCisVT<4, XLenVT>]>; 30 31def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 32 SDTCisVec<0>, SDTCisFP<0>, 33 SDTCVecEltisVT<2, i1>, 34 SDTCisSameNumEltsAs<0, 2>, 35 SDTCisVT<3, XLenVT>]>; 36def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<3, i1>, 40 SDTCisSameNumEltsAs<0, 3>, 41 SDTCisVT<4, XLenVT>]>; 42 43def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 44 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, 45 SDTCisSameAs<0, 1>, 46 SDTCisVT<2, XLenVT>, 47 SDTCisVT<3, XLenVT>]>>; 48def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 49 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 50 SDTCisSameAs<0, 1>, 51 SDTCisEltOfVec<2, 0>, 52 SDTCisVT<3, XLenVT>]>>; 53def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 54 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 55 SDTCisInt<0>, 56 SDTCisVT<2, XLenVT>, 57 SDTCisVT<3, XLenVT>]>>; 58def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 59 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 60 SDTCisFP<0>, 61 SDTCisEltOfVec<2, 0>, 62 SDTCisVT<3, XLenVT>]>>; 63 64def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 65def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 66def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 67def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 68def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 69def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 70def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 71def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 72def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 73def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 74def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 76def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 77def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 78def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 79def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 80def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 81def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 83 84def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 88 89def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 90def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 91def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 92def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 93def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 94def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 95def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 96def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 97def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 98def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 99 100def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 101 SDTCisSameAs<0, 2>, 102 SDTCisSameAs<0, 3>, 103 SDTCisVec<0>, SDTCisFP<0>, 104 SDTCVecEltisVT<4, i1>, 105 SDTCisSameNumEltsAs<0, 4>, 106 SDTCisVT<5, XLenVT>]>; 107def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 108 109def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 110 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 111 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 112]>; 113def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 114 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 115 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 116]>; 117 118def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 119def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 120def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 121 122def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 127 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 128 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 129]>; 130 131def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 132def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 133def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 134def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 135 136def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 137 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 138 SDTCisVec<1>, 139 SDTCisSameNumEltsAs<0, 1>, 140 SDTCisSameAs<1, 2>, 141 SDTCisVT<3, OtherVT>, 142 SDTCisSameAs<0, 4>, 143 SDTCisVT<5, XLenVT>]>>; 144 145def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 146 SDTypeProfile<1, 4, [SDTCisVec<0>, 147 SDTCisSameAs<0, 1>, 148 SDTCisVT<2, XLenVT>, 149 SDTCVecEltisVT<3, i1>, 150 SDTCisSameNumEltsAs<0, 3>, 151 SDTCisVT<4, XLenVT>]>>; 152def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 153 SDTypeProfile<1, 4, [SDTCisVec<0>, 154 SDTCisSameAs<0, 1>, 155 SDTCisInt<2>, 156 SDTCisSameNumEltsAs<0, 2>, 157 SDTCisSameSizeAs<0, 2>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCVecEltisVT<2, i16>, 166 SDTCisSameNumEltsAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170 171def SDT_RISCVSelect_VL : SDTypeProfile<1, 4, [ 172 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>, 173 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, XLenVT> 174]>; 175 176def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", SDT_RISCVSelect_VL>; 177def riscv_vp_merge_vl : SDNode<"RISCVISD::VP_MERGE_VL", SDT_RISCVSelect_VL>; 178 179def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, 180 SDTCisVT<1, XLenVT>]>; 181def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; 182def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; 183 184def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 185 SDTCisSameAs<0, 2>, 186 SDTCVecEltisVT<0, i1>, 187 SDTCisVT<3, XLenVT>]>; 188def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 189def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 190def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 191 192def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 193 194def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 195 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 196 197def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 198 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 199 SDTCisVec<1>, SDTCisInt<1>, 200 SDTCVecEltisVT<2, i1>, 201 SDTCisSameNumEltsAs<1, 2>, 202 SDTCisVT<3, XLenVT>]>>; 203 204def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 205 SDTCisSameNumEltsAs<0, 1>, 206 SDTCisSameNumEltsAs<1, 2>, 207 SDTCVecEltisVT<2, i1>, 208 SDTCisVT<3, XLenVT>]>; 209def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 210def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 211 212def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 213 SDTypeProfile<1, 3, [SDTCisVec<0>, 214 SDTCisSameNumEltsAs<0, 1>, 215 SDTCisSameNumEltsAs<0, 2>, 216 SDTCVecEltisVT<2, i1>, 217 SDTCisVT<3, XLenVT>]>>; 218 219def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 220 SDTCisSameNumEltsAs<0, 1>, 221 SDTCisSameAs<1, 2>, 222 SDTCisSameNumEltsAs<1, 3>, 223 SDTCVecEltisVT<3, i1>, 224 SDTCisVT<4, XLenVT>]>; 225def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 226def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 227def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>; 228def riscv_vwadd_vl : SDNode<"RISCVISD::VWADD_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 229def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 230def riscv_vwsub_vl : SDNode<"RISCVISD::VWSUB_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 231def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 232 233def SDT_RISCVVWBinOpW_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 234 SDTCisSameAs<0, 1>, 235 SDTCisSameNumEltsAs<1, 2>, 236 SDTCisOpSmallerThanOp<2, 1>, 237 SDTCisSameNumEltsAs<1, 3>, 238 SDTCVecEltisVT<3, i1>, 239 SDTCisVT<4, XLenVT>]>; 240def riscv_vwadd_w_vl : SDNode<"RISCVISD::VWADD_W_VL", SDT_RISCVVWBinOpW_VL>; 241def riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWBinOpW_VL>; 242def riscv_vwsub_w_vl : SDNode<"RISCVISD::VWSUB_W_VL", SDT_RISCVVWBinOpW_VL>; 243def riscv_vwsubu_w_vl : SDNode<"RISCVISD::VWSUBU_W_VL", SDT_RISCVVWBinOpW_VL>; 244 245def SDTRVVVecReduce : SDTypeProfile<1, 5, [ 246 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 247 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT> 248]>; 249 250def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 251 (riscv_mul_vl node:$A, node:$B, node:$C, 252 node:$D), [{ 253 return N->hasOneUse(); 254}]>; 255 256def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 257 (riscv_vwmul_vl node:$A, node:$B, node:$C, 258 node:$D), [{ 259 return N->hasOneUse(); 260}]>; 261 262def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 263 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 264 node:$D), [{ 265 return N->hasOneUse(); 266}]>; 267 268def riscv_vwmulsu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 269 (riscv_vwmulsu_vl node:$A, node:$B, node:$C, 270 node:$D), [{ 271 return N->hasOneUse(); 272}]>; 273 274def riscv_sext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 275 (riscv_sext_vl node:$A, node:$B, node:$C), [{ 276 return N->hasOneUse(); 277}]>; 278 279def riscv_zext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 280 (riscv_zext_vl node:$A, node:$B, node:$C), [{ 281 return N->hasOneUse(); 282}]>; 283 284def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 285 (riscv_fpextend_vl node:$A, node:$B, node:$C), [{ 286 return N->hasOneUse(); 287}]>; 288 289foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 290 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 291 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 292 293// Give explicit Complexity to prefer simm5/uimm5. 294def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; 295def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 2>; 296def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>; 297def SplatPat_simm5_plus1 298 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>; 299def SplatPat_simm5_plus1_nonzero 300 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>; 301 302// Ignore the vl operand. 303def SplatFPOp : PatFrag<(ops node:$op), 304 (riscv_vfmv_v_f_vl undef, node:$op, srcvalue)>; 305 306def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 307def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 308def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 309def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 310 311multiclass VPatBinaryVL_V<SDNode vop, 312 string instruction_name, 313 string suffix, 314 ValueType result_type, 315 ValueType op1_type, 316 ValueType op2_type, 317 ValueType mask_type, 318 int sew, 319 LMULInfo vlmul, 320 VReg op1_reg_class, 321 VReg op2_reg_class> { 322 def : Pat<(result_type (vop 323 (op1_type op1_reg_class:$rs1), 324 (op2_type op2_reg_class:$rs2), 325 (mask_type V0), 326 VLOpFrag)), 327 (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_MASK") 328 (result_type (IMPLICIT_DEF)), 329 op1_reg_class:$rs1, 330 op2_reg_class:$rs2, 331 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 332} 333 334multiclass VPatBinaryVL_XI<SDNode vop, 335 string instruction_name, 336 string suffix, 337 ValueType result_type, 338 ValueType vop1_type, 339 ValueType vop2_type, 340 ValueType mask_type, 341 int sew, 342 LMULInfo vlmul, 343 VReg vop_reg_class, 344 ComplexPattern SplatPatKind, 345 DAGOperand xop_kind> { 346 def : Pat<(result_type (vop 347 (vop1_type vop_reg_class:$rs1), 348 (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))), 349 (mask_type V0), 350 VLOpFrag)), 351 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 352 (result_type (IMPLICIT_DEF)), 353 vop_reg_class:$rs1, 354 xop_kind:$rs2, 355 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 356} 357 358multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 359 foreach vti = AllIntegerVectors in { 360 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 361 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 362 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 363 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 364 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 365 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 366 } 367} 368 369multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 370 Operand ImmType = simm5> 371 : VPatBinaryVL_VV_VX<vop, instruction_name> { 372 foreach vti = AllIntegerVectors in { 373 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 374 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 375 vti.Log2SEW, vti.LMul, vti.RegClass, 376 !cast<ComplexPattern>(SplatPat#_#ImmType), 377 ImmType>; 378 } 379} 380 381multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 382 foreach VtiToWti = AllWidenableIntVectors in { 383 defvar vti = VtiToWti.Vti; 384 defvar wti = VtiToWti.Wti; 385 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 386 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 387 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 388 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 389 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 390 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 391 } 392} 393multiclass VPatBinaryWVL_VV_VX_WV_WX<SDNode vop, SDNode vop_w, 394 string instruction_name> 395 : VPatBinaryWVL_VV_VX<vop, instruction_name> { 396 foreach VtiToWti = AllWidenableIntVectors in { 397 defvar vti = VtiToWti.Vti; 398 defvar wti = VtiToWti.Wti; 399 defm : VPatBinaryVL_V<vop_w, instruction_name, "WV", 400 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 401 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass>; 402 defm : VPatBinaryVL_XI<vop_w, instruction_name, "WX", 403 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 404 vti.Log2SEW, vti.LMul, wti.RegClass, SplatPat, GPR>; 405 } 406} 407 408multiclass VPatBinaryVL_VF<SDNode vop, 409 string instruction_name, 410 ValueType result_type, 411 ValueType vop_type, 412 ValueType mask_type, 413 int sew, 414 LMULInfo vlmul, 415 VReg vop_reg_class, 416 RegisterClass scalar_reg_class> { 417 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 418 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 419 (mask_type V0), 420 VLOpFrag)), 421 (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_MASK") 422 (result_type (IMPLICIT_DEF)), 423 vop_reg_class:$rs1, 424 scalar_reg_class:$rs2, 425 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 426} 427 428multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 429 foreach vti = AllFloatVectors in { 430 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 431 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 432 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 433 defm : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 434 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 435 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 436 } 437} 438 439multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 440 foreach fvti = AllFloatVectors in { 441 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 442 fvti.RegClass:$rs1, 443 (fvti.Mask V0), 444 VLOpFrag)), 445 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 446 (fvti.Vector (IMPLICIT_DEF)), 447 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 448 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 449 } 450} 451 452multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 453 CondCode cc> { 454 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 455 vti.RegClass:$rs2, cc, 456 (vti.Mask V0), 457 VLOpFrag)), 458 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 459 (vti.Mask (IMPLICIT_DEF)), 460 vti.RegClass:$rs1, 461 vti.RegClass:$rs2, 462 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 463} 464 465// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 466multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 467 CondCode cc, CondCode invcc> 468 : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 469 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 470 vti.RegClass:$rs1, invcc, 471 (vti.Mask V0), 472 VLOpFrag)), 473 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 474 (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 475 vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 476} 477 478multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 479 CondCode cc, CondCode invcc> { 480 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); 481 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 482 (SplatPat (XLenVT GPR:$rs2)), cc, 483 (vti.Mask V0), 484 VLOpFrag)), 485 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 486 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 487 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 488 (vti.Vector vti.RegClass:$rs1), invcc, 489 (vti.Mask V0), 490 VLOpFrag)), 491 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 492 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 493} 494 495multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 496 CondCode cc, CondCode invcc> { 497 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 498 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 499 (SplatPat_simm5 simm5:$rs2), cc, 500 (vti.Mask V0), 501 VLOpFrag)), 502 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 503 XLenVT:$rs2, (vti.Mask V0), GPR:$vl, 504 vti.Log2SEW)>; 505 506 // FIXME: Can do some canonicalization to remove these patterns. 507 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 508 (vti.Vector vti.RegClass:$rs1), invcc, 509 (vti.Mask V0), 510 VLOpFrag)), 511 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 512 simm5:$rs2, (vti.Mask V0), GPR:$vl, 513 vti.Log2SEW)>; 514} 515 516multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti, 517 string instruction_name, 518 CondCode cc, CondCode invcc, 519 ComplexPattern splatpat_kind> { 520 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 521 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 522 (splatpat_kind simm5:$rs2), cc, 523 (vti.Mask V0), 524 VLOpFrag)), 525 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 526 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 527 vti.Log2SEW)>; 528 529 // FIXME: Can do some canonicalization to remove these patterns. 530 def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), 531 (vti.Vector vti.RegClass:$rs1), invcc, 532 (vti.Mask V0), 533 VLOpFrag)), 534 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 535 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 536 vti.Log2SEW)>; 537} 538 539multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 540 string inst_name, 541 string swapped_op_inst_name> { 542 foreach fvti = AllFloatVectors in { 543 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 544 fvti.RegClass:$rs2, 545 cc, 546 (fvti.Mask V0), 547 VLOpFrag)), 548 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX#"_MASK") 549 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 550 fvti.RegClass:$rs2, (fvti.Mask V0), 551 GPR:$vl, fvti.Log2SEW)>; 552 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 553 (SplatFPOp fvti.ScalarRegClass:$rs2), 554 cc, 555 (fvti.Mask V0), 556 VLOpFrag)), 557 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 558 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 559 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 560 GPR:$vl, fvti.Log2SEW)>; 561 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 562 (fvti.Vector fvti.RegClass:$rs1), 563 cc, 564 (fvti.Mask V0), 565 VLOpFrag)), 566 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 567 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 568 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 569 GPR:$vl, fvti.Log2SEW)>; 570 } 571} 572 573multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 574 list <VTypeInfoToFraction> fraction_list> { 575 foreach vtiTofti = fraction_list in { 576 defvar vti = vtiTofti.Vti; 577 defvar fti = vtiTofti.Fti; 578 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 579 (fti.Mask V0), VLOpFrag)), 580 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK") 581 (vti.Vector (IMPLICIT_DEF)), 582 fti.RegClass:$rs2, 583 (fti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 584 } 585} 586 587multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 588 foreach fvti = AllFloatVectors in { 589 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 590 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 591 (fvti.Mask V0), 592 VLOpFrag)), 593 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 594 (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 595 (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 596 } 597} 598 599multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 600 foreach fvti = AllFloatVectors in { 601 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 602 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 603 (ivti.Mask V0), 604 VLOpFrag)), 605 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 606 (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 607 (ivti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 608 } 609} 610 611multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 612 foreach fvtiToFWti = AllWidenableFloatVectors in { 613 defvar fvti = fvtiToFWti.Vti; 614 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 615 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 616 (fvti.Mask V0), 617 VLOpFrag)), 618 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 619 (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 620 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 621 } 622} 623 624multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 625 foreach vtiToWti = AllWidenableIntToFloatVectors in { 626 defvar ivti = vtiToWti.Vti; 627 defvar fwti = vtiToWti.Wti; 628 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 629 (ivti.Mask V0), 630 VLOpFrag)), 631 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 632 (fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 633 (ivti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 634 } 635} 636 637multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 638 foreach vtiToWti = AllWidenableIntToFloatVectors in { 639 defvar vti = vtiToWti.Vti; 640 defvar fwti = vtiToWti.Wti; 641 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 642 (fwti.Mask V0), 643 VLOpFrag)), 644 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK") 645 (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 646 (fwti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 647 } 648} 649 650multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 651 foreach fvtiToFWti = AllWidenableFloatVectors in { 652 defvar fvti = fvtiToFWti.Vti; 653 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 654 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 655 (iwti.Mask V0), 656 VLOpFrag)), 657 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 658 (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1, 659 (iwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 660 } 661} 662 663multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 664 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 665 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 666 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 667 (vti.Mask true_mask), 668 VLOpFrag)), 669 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 670 (vti_m1.Vector VR:$merge), 671 (vti.Vector vti.RegClass:$rs1), 672 (vti_m1.Vector VR:$rs2), 673 GPR:$vl, vti.Log2SEW)>; 674 675 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 676 (vti.Mask V0), VLOpFrag)), 677 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 678 (vti_m1.Vector VR:$merge), 679 (vti.Vector vti.RegClass:$rs1), 680 (vti_m1.Vector VR:$rs2), 681 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 682 } 683} 684 685multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> { 686 foreach vtiToWti = AllWidenableIntVectors in { 687 defvar vti = vtiToWti.Vti; 688 defvar wti = vtiToWti.Wti; 689 def : Pat< 690 (vti.Vector 691 (riscv_trunc_vector_vl 692 (op (wti.Vector wti.RegClass:$rs2), 693 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))), 694 (vti.Mask true_mask), 695 VLOpFrag)), 696 (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX) 697 wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 698 def : Pat< 699 (vti.Vector 700 (riscv_trunc_vector_vl 701 (op (wti.Vector wti.RegClass:$rs2), 702 (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))), 703 (vti.Mask true_mask), 704 VLOpFrag)), 705 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 706 wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 707 } 708} 709 710multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> { 711 defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>; 712 defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>; 713 foreach vtiToWti = AllWidenableIntVectors in { 714 defvar vti = vtiToWti.Vti; 715 defvar wti = vtiToWti.Wti; 716 def : Pat< 717 (vti.Vector 718 (riscv_trunc_vector_vl 719 (op (wti.Vector wti.RegClass:$rs2), 720 (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask), 721 VLOpFrag)), 722 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 723 wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW)>; 724 } 725} 726 727multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 728 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 729 defvar vti = vtiToWti.Vti; 730 defvar wti = vtiToWti.Wti; 731 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 732 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 733 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 734 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 735 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 736 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 737 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 738 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 739 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 740 VR:$rs2, (vti.Mask V0), VLOpFrag)), 741 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 742 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 743 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 744 } 745} 746 747multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 748 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 749 defvar vti = vtiToWti.Vti; 750 defvar wti = vtiToWti.Wti; 751 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 752 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 753 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 754 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 755 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 756 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 757 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 758 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 759 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 760 VR:$rs2, (vti.Mask V0), VLOpFrag)), 761 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 762 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 763 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 764 } 765} 766 767multiclass VPatWidenBinaryFPVL_VV_VF<SDNode op, PatFrags extop, string instruction_name> { 768 foreach fvtiToFWti = AllWidenableFloatVectors in { 769 defvar fvti = fvtiToFWti.Vti; 770 defvar fwti = fvtiToFWti.Wti; 771 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 772 (fvti.Mask true_mask), VLOpFrag)), 773 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 774 (fvti.Mask true_mask), VLOpFrag)), 775 (fwti.Mask true_mask), VLOpFrag)), 776 (!cast<Instruction>(instruction_name#"_VV_"#fvti.LMul.MX) 777 fvti.RegClass:$rs2, fvti.RegClass:$rs1, 778 GPR:$vl, fvti.Log2SEW)>; 779 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 780 (fvti.Mask true_mask), VLOpFrag)), 781 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 782 (fvti.Mask true_mask), VLOpFrag)), 783 (fwti.Mask true_mask), VLOpFrag)), 784 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 785 fvti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 786 GPR:$vl, fvti.Log2SEW)>; 787 } 788} 789 790multiclass VPatWidenBinaryFPVL_WV_WF<SDNode op, PatFrags extop, string instruction_name> { 791 foreach fvtiToFWti = AllWidenableFloatVectors in { 792 defvar fvti = fvtiToFWti.Vti; 793 defvar fwti = fvtiToFWti.Wti; 794 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 795 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 796 (fvti.Mask true_mask), VLOpFrag)), 797 (fwti.Mask true_mask), VLOpFrag)), 798 (!cast<Instruction>(instruction_name#"_WV_"#fvti.LMul.MX) 799 fwti.RegClass:$rs2, fvti.RegClass:$rs1, 800 GPR:$vl, fvti.Log2SEW)>; 801 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 802 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 803 (fvti.Mask true_mask), VLOpFrag)), 804 (fwti.Mask true_mask), VLOpFrag)), 805 (!cast<Instruction>(instruction_name#"_W"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 806 fwti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 807 GPR:$vl, fvti.Log2SEW)>; 808 } 809} 810 811multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> { 812 defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>; 813 defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>; 814} 815 816multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> { 817 foreach vtiToWti = AllWidenableIntVectors in { 818 defvar vti = vtiToWti.Vti; 819 defvar wti = vtiToWti.Wti; 820 def : Pat< 821 (vti.Vector 822 (riscv_trunc_vector_vl 823 (op (wti.Vector wti.RegClass:$rs2), 824 (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1)), 825 (vti.Mask true_mask), VLOpFrag)), 826 (wti.Mask true_mask), VLOpFrag), 827 (vti.Mask true_mask), VLOpFrag)), 828 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 829 wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; 830 } 831} 832 833multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> { 834 foreach vti = AllIntegerVectors in { 835 defvar suffix = vti.LMul.MX; 836 // NOTE: We choose VMADD because it has the most commuting freedom. So it 837 // works best with how TwoAddressInstructionPass tries commuting. 838 def : Pat<(vti.Vector 839 (op vti.RegClass:$rs2, 840 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 841 vti.RegClass:$rd, 842 (vti.Mask true_mask), VLOpFrag), 843 (vti.Mask true_mask), VLOpFrag)), 844 (!cast<Instruction>(instruction_name#"_VV_"# suffix) 845 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 846 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 847 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 848 // commutable. 849 def : Pat<(vti.Vector 850 (op vti.RegClass:$rs2, 851 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 852 vti.RegClass:$rd, 853 (vti.Mask true_mask), VLOpFrag), 854 (vti.Mask true_mask), VLOpFrag)), 855 (!cast<Instruction>(instruction_name#"_VX_" # suffix) 856 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 857 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 858 } 859} 860 861multiclass VPatWidenMultiplyAddVL_VV_VX<PatFrag op1, string instruction_name> { 862 foreach vtiTowti = AllWidenableIntVectors in { 863 defvar vti = vtiTowti.Vti; 864 defvar wti = vtiTowti.Wti; 865 def : Pat<(wti.Vector 866 (riscv_add_vl wti.RegClass:$rd, 867 (op1 vti.RegClass:$rs1, 868 (vti.Vector vti.RegClass:$rs2), 869 (vti.Mask true_mask), VLOpFrag), 870 (vti.Mask true_mask), VLOpFrag)), 871 (!cast<Instruction>(instruction_name#"_VV_" # vti.LMul.MX) 872 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 873 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 874 def : Pat<(wti.Vector 875 (riscv_add_vl wti.RegClass:$rd, 876 (op1 (SplatPat XLenVT:$rs1), 877 (vti.Vector vti.RegClass:$rs2), 878 (vti.Mask true_mask), VLOpFrag), 879 (vti.Mask true_mask), VLOpFrag)), 880 (!cast<Instruction>(instruction_name#"_VX_" # vti.LMul.MX) 881 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 882 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 883 } 884} 885 886multiclass VPatNarrowShiftSplat_WX_WI<SDNode op, string instruction_name> { 887 foreach vtiTowti = AllWidenableIntVectors in { 888 defvar vti = vtiTowti.Vti; 889 defvar wti = vtiTowti.Wti; 890 def : Pat<(vti.Vector (riscv_trunc_vector_vl 891 (wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 892 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 893 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 894 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 895 def : Pat<(vti.Vector (riscv_trunc_vector_vl 896 (wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 897 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 898 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 899 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 900 } 901} 902 903//===----------------------------------------------------------------------===// 904// Patterns. 905//===----------------------------------------------------------------------===// 906 907let Predicates = [HasVInstructions] in { 908 909// 12.1. Vector Single-Width Integer Add and Subtract 910defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 911defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 912// Handle VRSUB specially since it's the only integer binary op with reversed 913// pattern operands 914foreach vti = AllIntegerVectors in { 915 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 916 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 917 VLOpFrag), 918 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 919 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 920 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 921 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 922 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 923 VLOpFrag), 924 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 925 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 926 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 927} 928 929// 12.2. Vector Widening Integer Add/Subtract 930defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwadd_vl, riscv_vwadd_w_vl, "PseudoVWADD">; 931defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWADDU">; 932defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">; 933defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">; 934 935// 12.3. Vector Integer Extension 936defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 937 AllFractionableVF2IntVectors>; 938defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 939 AllFractionableVF2IntVectors>; 940defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 941 AllFractionableVF4IntVectors>; 942defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 943 AllFractionableVF4IntVectors>; 944defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 945 AllFractionableVF8IntVectors>; 946defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 947 AllFractionableVF8IntVectors>; 948 949// 12.5. Vector Bitwise Logical Instructions 950defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 951defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 952defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 953 954// 12.6. Vector Single-Width Bit Shift Instructions 955defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 956defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 957defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 958 959foreach vti = AllIntegerVectors in { 960 // Emit shift by 1 as an add since it might be faster. 961 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 962 (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)), 963 (vti.Mask true_mask), 964 VLOpFrag), 965 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 966 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 967} 968 969// 12.7. Vector Narrowing Integer Right Shift Instructions 970defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">; 971defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">; 972 973defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">; 974defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">; 975defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">; 976defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">; 977defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">; 978defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">; 979 980foreach vtiTowti = AllWidenableIntVectors in { 981 defvar vti = vtiTowti.Vti; 982 defvar wti = vtiTowti.Wti; 983 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 984 (vti.Mask V0), 985 VLOpFrag)), 986 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX#"_MASK") 987 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, X0, 988 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 989} 990 991// 12.8. Vector Integer Comparison Instructions 992foreach vti = AllIntegerVectors in { 993 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 994 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 995 996 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 997 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 998 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 999 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1000 1001 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 1002 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 1003 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 1004 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 1005 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1006 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1007 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 1008 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 1009 // There is no VMSGE(U)_VX instruction 1010 1011 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 1012 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 1013 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1014 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1015 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 1016 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 1017 1018 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT, 1019 SplatPat_simm5_plus1_nonzero>; 1020 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT, 1021 SplatPat_simm5_plus1_nonzero>; 1022 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE, 1023 SplatPat_simm5_plus1>; 1024 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE, 1025 SplatPat_simm5_plus1_nonzero>; 1026} // foreach vti = AllIntegerVectors 1027 1028// 12.9. Vector Integer Min/Max Instructions 1029defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 1030defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 1031defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 1032defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 1033 1034// 12.10. Vector Single-Width Integer Multiply Instructions 1035defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 1036defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 1037defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 1038 1039// 12.11. Vector Integer Divide Instructions 1040defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 1041defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 1042defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 1043defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 1044 1045// 12.12. Vector Widening Integer Multiply Instructions 1046defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 1047defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 1048defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; 1049 1050// 12.13 Vector Single-Width Integer Multiply-Add Instructions 1051defm : VPatMultiplyAddVL_VV_VX<riscv_add_vl, "PseudoVMADD">; 1052defm : VPatMultiplyAddVL_VV_VX<riscv_sub_vl, "PseudoVNMSUB">; 1053 1054// 12.14. Vector Widening Integer Multiply-Add Instructions 1055defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmul_vl_oneuse, "PseudoVWMACC">; 1056defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulu_vl_oneuse, "PseudoVWMACCU">; 1057defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulsu_vl_oneuse, "PseudoVWMACCSU">; 1058foreach vtiTowti = AllWidenableIntVectors in { 1059 defvar vti = vtiTowti.Vti; 1060 defvar wti = vtiTowti.Wti; 1061 def : Pat<(wti.Vector 1062 (riscv_add_vl wti.RegClass:$rd, 1063 (riscv_vwmulsu_vl_oneuse (vti.Vector vti.RegClass:$rs1), 1064 (SplatPat XLenVT:$rs2), 1065 (vti.Mask true_mask), VLOpFrag), 1066 (vti.Mask true_mask), VLOpFrag)), 1067 (!cast<Instruction>("PseudoVWMACCUS_VX_" # vti.LMul.MX) 1068 wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1, 1069 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1070} 1071 1072// 12.15. Vector Integer Merge Instructions 1073foreach vti = AllIntegerVectors in { 1074 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1075 vti.RegClass:$rs1, 1076 vti.RegClass:$rs2, 1077 VLOpFrag)), 1078 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 1079 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 1080 GPR:$vl, vti.Log2SEW)>; 1081 1082 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1083 (SplatPat XLenVT:$rs1), 1084 vti.RegClass:$rs2, 1085 VLOpFrag)), 1086 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 1087 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1088 1089 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1090 (SplatPat_simm5 simm5:$rs1), 1091 vti.RegClass:$rs2, 1092 VLOpFrag)), 1093 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 1094 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1095 1096 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1097 vti.RegClass:$rs1, 1098 vti.RegClass:$rs2, 1099 VLOpFrag)), 1100 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX#"_TU") 1101 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1, 1102 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1103 1104 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1105 (SplatPat XLenVT:$rs1), 1106 vti.RegClass:$rs2, 1107 VLOpFrag)), 1108 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX#"_TU") 1109 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1, 1110 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1111 1112 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1113 (SplatPat_simm5 simm5:$rs1), 1114 vti.RegClass:$rs2, 1115 VLOpFrag)), 1116 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU") 1117 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, 1118 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1119} 1120 1121// 12.16. Vector Integer Move Instructions 1122foreach vti = AllIntegerVectors in { 1123 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)), 1124 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 1125 $rs2, GPR:$vl, vti.Log2SEW)>; 1126 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, GPR:$rs2, VLOpFrag)), 1127 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX#"_TU") 1128 $passthru, $rs2, GPR:$vl, vti.Log2SEW)>; 1129 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 1130 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat XLenVT:$imm5), 1131 VLOpFrag)), 1132 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 1133 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1134 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, (ImmPat XLenVT:$imm5), 1135 VLOpFrag)), 1136 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX#"_TU") 1137 $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1138} 1139 1140// 12.1. Vector Single-Width Saturating Add and Subtract 1141defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 1142defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 1143defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 1144defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 1145 1146} // Predicates = [HasVInstructions] 1147 1148// 15.1. Vector Single-Width Integer Reduction Instructions 1149let Predicates = [HasVInstructions] in { 1150defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 1151defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 1152defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 1153defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 1154defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 1155defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 1156defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 1157defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 1158 1159// 15.2. Vector Widening Integer Reduction Instructions 1160defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1161defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1162defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1163defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1164defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1165} // Predicates = [HasVInstructions] 1166 1167// 15.3. Vector Single-Width Floating-Point Reduction Instructions 1168let Predicates = [HasVInstructionsAnyF] in { 1169defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 1170defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>; 1171defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 1172defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 1173 1174// 15.4. Vector Widening Floating-Point Reduction Instructions 1175defm : VPatWidenReductionVL<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1176defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_SEQ_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1177defm : VPatWidenReductionVL<rvv_vecreduce_FADD_vl, fpext_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1178defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1179} // Predicates = [HasVInstructionsAnyF] 1180 1181let Predicates = [HasVInstructionsAnyF] in { 1182 1183// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 1184defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 1185defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 1186defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 1187 1188// 14.3. Vector Widening Floating-Point Add/Subtract Instructions 1189defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fadd_vl, "PseudoVFWADD">; 1190defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fsub_vl, "PseudoVFWSUB">; 1191 1192// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 1193defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 1194defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 1195defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 1196 1197// 14.5. Vector Widening Floating-Point Multiply Instructions 1198defm : VPatWidenBinaryFPVL_VV_VF<riscv_fmul_vl, riscv_fpextend_vl_oneuse, "PseudoVFWMUL">; 1199 1200// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 1201foreach vti = AllFloatVectors in { 1202 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 1203 // works best with how TwoAddressInstructionPass tries commuting. 1204 defvar suffix = vti.LMul.MX; 1205 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1206 vti.RegClass:$rs2, (vti.Mask true_mask), 1207 VLOpFrag)), 1208 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 1209 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1210 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1211 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1212 vti.RegClass:$rs2, (vti.Mask V0), 1213 VLOpFrag)), 1214 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix #"_MASK") 1215 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1216 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 1217 1218 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1219 (riscv_fneg_vl vti.RegClass:$rs2, 1220 (vti.Mask true_mask), 1221 VLOpFrag), 1222 (vti.Mask true_mask), 1223 VLOpFrag)), 1224 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 1225 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1226 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1227 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1228 (riscv_fneg_vl vti.RegClass:$rs2, 1229 (vti.Mask srcvalue), 1230 VLOpFrag), 1231 (vti.Mask V0), 1232 VLOpFrag)), 1233 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix #"_MASK") 1234 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1235 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1236 1237 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1238 (vti.Mask srcvalue), 1239 VLOpFrag), 1240 vti.RegClass:$rd, 1241 (riscv_fneg_vl vti.RegClass:$rs2, 1242 (vti.Mask srcvalue), 1243 VLOpFrag), 1244 (vti.Mask true_mask), 1245 VLOpFrag)), 1246 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 1247 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1248 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1249 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1250 (vti.Mask srcvalue), 1251 VLOpFrag), 1252 vti.RegClass:$rd, 1253 (riscv_fneg_vl vti.RegClass:$rs2, 1254 (vti.Mask srcvalue), 1255 VLOpFrag), 1256 (vti.Mask V0), 1257 VLOpFrag)), 1258 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix #"_MASK") 1259 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1260 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1261 1262 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1263 (vti.Mask srcvalue), 1264 VLOpFrag), 1265 vti.RegClass:$rd, vti.RegClass:$rs2, 1266 (vti.Mask true_mask), 1267 VLOpFrag)), 1268 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 1269 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1270 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1271 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1272 (vti.Mask srcvalue), 1273 VLOpFrag), 1274 vti.RegClass:$rd, vti.RegClass:$rs2, 1275 (vti.Mask V0), 1276 VLOpFrag)), 1277 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix #"_MASK") 1278 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1279 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1280 1281 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 1282 // commutable. 1283 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1284 vti.RegClass:$rd, vti.RegClass:$rs2, 1285 (vti.Mask true_mask), 1286 VLOpFrag)), 1287 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1288 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1289 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1290 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1291 vti.RegClass:$rd, vti.RegClass:$rs2, 1292 (vti.Mask V0), 1293 VLOpFrag)), 1294 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1295 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1296 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 1297 1298 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1299 vti.RegClass:$rd, 1300 (riscv_fneg_vl vti.RegClass:$rs2, 1301 (vti.Mask srcvalue), 1302 VLOpFrag), 1303 (vti.Mask true_mask), 1304 VLOpFrag)), 1305 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1306 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1307 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1308 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1309 vti.RegClass:$rd, 1310 (riscv_fneg_vl vti.RegClass:$rs2, 1311 (vti.Mask srcvalue), 1312 VLOpFrag), 1313 (vti.Mask V0), 1314 VLOpFrag)), 1315 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1316 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1317 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1318 1319 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1320 (riscv_fneg_vl vti.RegClass:$rd, 1321 (vti.Mask srcvalue), 1322 VLOpFrag), 1323 (riscv_fneg_vl vti.RegClass:$rs2, 1324 (vti.Mask srcvalue), 1325 VLOpFrag), 1326 (vti.Mask true_mask), 1327 VLOpFrag)), 1328 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1329 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1330 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1331 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1332 (riscv_fneg_vl vti.RegClass:$rd, 1333 (vti.Mask srcvalue), 1334 VLOpFrag), 1335 (riscv_fneg_vl vti.RegClass:$rs2, 1336 (vti.Mask srcvalue), 1337 VLOpFrag), 1338 (vti.Mask V0), 1339 VLOpFrag)), 1340 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1341 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1342 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1343 1344 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1345 (riscv_fneg_vl vti.RegClass:$rd, 1346 (vti.Mask srcvalue), 1347 VLOpFrag), 1348 vti.RegClass:$rs2, 1349 (vti.Mask true_mask), 1350 VLOpFrag)), 1351 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1352 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1353 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1354 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1355 (riscv_fneg_vl vti.RegClass:$rd, 1356 (vti.Mask srcvalue), 1357 VLOpFrag), 1358 vti.RegClass:$rs2, 1359 (vti.Mask V0), 1360 VLOpFrag)), 1361 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1362 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1363 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1364 1365 // The splat might be negated. 1366 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1367 (vti.Mask srcvalue), 1368 VLOpFrag), 1369 vti.RegClass:$rd, 1370 (riscv_fneg_vl vti.RegClass:$rs2, 1371 (vti.Mask srcvalue), 1372 VLOpFrag), 1373 (vti.Mask true_mask), 1374 VLOpFrag)), 1375 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1376 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1377 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1378 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1379 (vti.Mask srcvalue), 1380 VLOpFrag), 1381 vti.RegClass:$rd, 1382 (riscv_fneg_vl vti.RegClass:$rs2, 1383 (vti.Mask srcvalue), 1384 VLOpFrag), 1385 (vti.Mask V0), 1386 VLOpFrag)), 1387 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1388 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1389 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1390 1391 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1392 (vti.Mask srcvalue), 1393 VLOpFrag), 1394 vti.RegClass:$rd, vti.RegClass:$rs2, 1395 (vti.Mask true_mask), 1396 VLOpFrag)), 1397 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1398 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1399 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1400 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1401 (vti.Mask srcvalue), 1402 VLOpFrag), 1403 vti.RegClass:$rd, vti.RegClass:$rs2, 1404 (vti.Mask V0), 1405 VLOpFrag)), 1406 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1407 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1408 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1409} 1410 1411// 14.11. Vector Floating-Point MIN/MAX Instructions 1412defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1413defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1414 1415// 14.13. Vector Floating-Point Compare Instructions 1416defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1417defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1418 1419defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1420defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1421 1422defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1423defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1424 1425defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1426defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1427 1428foreach vti = AllFloatVectors in { 1429 // 14.8. Vector Floating-Point Square-Root Instruction 1430 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1431 VLOpFrag), 1432 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1433 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1434 1435 // 14.12. Vector Floating-Point Sign-Injection Instructions 1436 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1437 VLOpFrag), 1438 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1439 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1440 // Handle fneg with VFSGNJN using the same input for both operands. 1441 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), 1442 VLOpFrag), 1443 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX #"_MASK") 1444 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs, 1445 vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 1446 TAIL_AGNOSTIC)>; 1447 1448 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1449 (vti.Vector vti.RegClass:$rs2), 1450 (vti.Mask true_mask), 1451 VLOpFrag), 1452 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1453 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1454 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1455 (riscv_fneg_vl vti.RegClass:$rs2, 1456 (vti.Mask true_mask), 1457 VLOpFrag), 1458 (vti.Mask true_mask), 1459 VLOpFrag), 1460 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1461 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1462 1463 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1464 (SplatFPOp vti.ScalarRegClass:$rs2), 1465 (vti.Mask true_mask), 1466 VLOpFrag), 1467 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1468 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1469} 1470 1471foreach fvti = AllFloatVectors in { 1472 // Floating-point vselects: 1473 // 12.15. Vector Integer Merge Instructions 1474 // 14.15. Vector Floating-Point Merge Instruction 1475 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1476 fvti.RegClass:$rs1, 1477 fvti.RegClass:$rs2, 1478 VLOpFrag)), 1479 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1480 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1481 GPR:$vl, fvti.Log2SEW)>; 1482 1483 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1484 (SplatFPOp fvti.ScalarRegClass:$rs1), 1485 fvti.RegClass:$rs2, 1486 VLOpFrag)), 1487 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1488 fvti.RegClass:$rs2, 1489 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1490 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1491 1492 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1493 (SplatFPOp (fvti.Scalar fpimm0)), 1494 fvti.RegClass:$rs2, 1495 VLOpFrag)), 1496 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1497 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1498 1499 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1500 fvti.RegClass:$rs1, 1501 fvti.RegClass:$rs2, 1502 VLOpFrag)), 1503 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX#"_TU") 1504 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1505 GPR:$vl, fvti.Log2SEW)>; 1506 1507 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1508 (SplatFPOp fvti.ScalarRegClass:$rs1), 1509 fvti.RegClass:$rs2, 1510 VLOpFrag)), 1511 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX#"_TU") 1512 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 1513 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1514 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1515 1516 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1517 (SplatFPOp (fvti.Scalar fpimm0)), 1518 fvti.RegClass:$rs2, 1519 VLOpFrag)), 1520 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") 1521 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), 1522 GPR:$vl, fvti.Log2SEW)>; 1523 1524 // 14.16. Vector Floating-Point Move Instruction 1525 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1526 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1527 (fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)), 1528 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1529 0, GPR:$vl, fvti.Log2SEW)>; 1530 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1531 fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)), 1532 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX#"_TU") 1533 $passthru, 0, GPR:$vl, fvti.Log2SEW)>; 1534 1535 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1536 (fvti.Vector undef), (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1537 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1538 fvti.LMul.MX) 1539 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1540 GPR:$vl, fvti.Log2SEW)>; 1541 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1542 fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1543 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1544 fvti.LMul.MX # "_TU") 1545 $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), 1546 GPR:$vl, fvti.Log2SEW)>; 1547 1548 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1549 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1550 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1551 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1552 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1553 1554 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1555 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1556 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1557 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1558 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1559 foreach fvtiToFWti = AllWidenableFloatVectors in { 1560 defvar fvti = fvtiToFWti.Vti; 1561 defvar fwti = fvtiToFWti.Wti; 1562 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1563 (fvti.Mask V0), 1564 VLOpFrag)), 1565 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK") 1566 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1567 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1568 } 1569 1570 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1571 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1572 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1573 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1574 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1575 foreach fvtiToFWti = AllWidenableFloatVectors in { 1576 defvar fvti = fvtiToFWti.Vti; 1577 defvar fwti = fvtiToFWti.Wti; 1578 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1579 (fwti.Mask V0), 1580 VLOpFrag)), 1581 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK") 1582 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1583 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1584 1585 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1586 (fwti.Mask V0), 1587 VLOpFrag)), 1588 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_MASK") 1589 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1590 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1591 } 1592} 1593 1594} // Predicates = [HasVInstructionsAnyF] 1595 1596let Predicates = [HasVInstructions] in { 1597 1598foreach mti = AllMasks in { 1599 // 16.1 Vector Mask-Register Logical Instructions 1600 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1601 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1602 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1603 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1604 1605 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1606 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1607 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1608 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1609 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1610 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1611 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1612 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1613 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1614 1615 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1616 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1617 VLOpFrag)), 1618 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 1619 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1620 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1621 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1622 VLOpFrag)), 1623 (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 1624 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1625 // XOR is associative so we need 2 patterns for VMXNOR. 1626 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1627 VLOpFrag), 1628 VR:$rs2, VLOpFrag)), 1629 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1630 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1631 1632 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1633 VLOpFrag), 1634 VLOpFrag)), 1635 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1636 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1637 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1638 VLOpFrag), 1639 VLOpFrag)), 1640 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1641 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1642 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1643 VLOpFrag), 1644 VLOpFrag)), 1645 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1646 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1647 1648 // Match the not idiom to the vmnot.m pseudo. 1649 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1650 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1651 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1652 1653 // 16.2 Vector count population in mask vcpop.m 1654 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1655 VLOpFrag)), 1656 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 1657 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1658 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 1659 VLOpFrag)), 1660 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 1661 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 1662} 1663 1664} // Predicates = [HasVInstructions] 1665 1666let Predicates = [HasVInstructions] in { 1667// 17.1. Integer Scalar Move Instructions 1668// 17.4. Vector Register Gather Instruction 1669foreach vti = AllIntegerVectors in { 1670 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1671 vti.ScalarRegClass:$rs1, 1672 VLOpFrag)), 1673 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1674 vti.RegClass:$merge, 1675 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1676 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1677 (vti.Vector vti.RegClass:$rs1), 1678 (vti.Mask true_mask), 1679 VLOpFrag)), 1680 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1681 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1682 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1683 (vti.Mask true_mask), 1684 VLOpFrag)), 1685 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1686 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1687 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1688 (vti.Mask true_mask), 1689 VLOpFrag)), 1690 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1691 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1692 1693 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1694 (riscv_vrgather_vv_vl 1695 vti.RegClass:$rs2, 1696 vti.RegClass:$rs1, 1697 (vti.Mask true_mask), 1698 VLOpFrag), 1699 vti.RegClass:$merge, 1700 VLOpFrag)), 1701 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1702 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1703 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1704 1705 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1706 (riscv_vrgather_vx_vl 1707 vti.RegClass:$rs2, 1708 uimm5:$imm, 1709 (vti.Mask true_mask), 1710 VLOpFrag), 1711 vti.RegClass:$merge, 1712 VLOpFrag)), 1713 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1714 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1715 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1716 1717 // emul = lmul * 16 / sew 1718 defvar vlmul = vti.LMul; 1719 defvar octuple_lmul = vlmul.octuple; 1720 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1721 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1722 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1723 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1724 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1725 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1726 (ivti.Vector ivti.RegClass:$rs1), 1727 (vti.Mask true_mask), 1728 VLOpFrag)), 1729 (!cast<Instruction>(inst) 1730 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1731 1732 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1733 (riscv_vrgatherei16_vv_vl 1734 vti.RegClass:$rs2, 1735 (ivti.Vector ivti.RegClass:$rs1), 1736 (vti.Mask true_mask), 1737 VLOpFrag), 1738 vti.RegClass:$merge, 1739 VLOpFrag)), 1740 (!cast<Instruction>(inst#"_MASK") 1741 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1742 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1743 } 1744} 1745 1746} // Predicates = [HasVInstructions] 1747 1748let Predicates = [HasVInstructionsAnyF] in { 1749 1750// 17.2. Floating-Point Scalar Move Instructions 1751foreach vti = AllFloatVectors in { 1752 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1753 (vti.Scalar (fpimm0)), 1754 VLOpFrag)), 1755 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1756 vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>; 1757 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1758 vti.ScalarRegClass:$rs1, 1759 VLOpFrag)), 1760 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1761 vti.RegClass:$merge, 1762 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1763 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1764 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1765 (ivti.Vector vti.RegClass:$rs1), 1766 (vti.Mask true_mask), 1767 VLOpFrag)), 1768 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1769 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1770 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1771 (vti.Mask true_mask), 1772 VLOpFrag)), 1773 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1774 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1775 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1776 (vti.Mask true_mask), 1777 VLOpFrag)), 1778 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1779 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1780 1781 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1782 (riscv_vrgather_vv_vl 1783 vti.RegClass:$rs2, 1784 (ivti.Vector vti.RegClass:$rs1), 1785 (vti.Mask true_mask), 1786 VLOpFrag), 1787 vti.RegClass:$merge, 1788 VLOpFrag)), 1789 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1790 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1791 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1792 1793 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1794 (riscv_vrgather_vx_vl 1795 vti.RegClass:$rs2, 1796 uimm5:$imm, 1797 (vti.Mask true_mask), 1798 VLOpFrag), 1799 vti.RegClass:$merge, 1800 VLOpFrag)), 1801 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1802 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1803 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1804 1805 defvar vlmul = vti.LMul; 1806 defvar octuple_lmul = vlmul.octuple; 1807 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1808 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1809 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1810 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1811 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1812 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1813 (ivti.Vector ivti.RegClass:$rs1), 1814 (vti.Mask true_mask), 1815 VLOpFrag)), 1816 (!cast<Instruction>(inst) 1817 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1818 1819 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1820 (riscv_vrgatherei16_vv_vl 1821 vti.RegClass:$rs2, 1822 (ivti.Vector ivti.RegClass:$rs1), 1823 (vti.Mask true_mask), 1824 VLOpFrag), 1825 vti.RegClass:$merge, 1826 VLOpFrag)), 1827 (!cast<Instruction>(inst#"_MASK") 1828 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1829 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1830 } 1831} 1832 1833} // Predicates = [HasVInstructionsAnyF] 1834 1835//===----------------------------------------------------------------------===// 1836// Miscellaneous RISCVISD SDNodes 1837//===----------------------------------------------------------------------===// 1838 1839def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1840 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1841 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1842 1843def SDTRVVSlide : SDTypeProfile<1, 5, [ 1844 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1845 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1846]>; 1847def SDTRVVSlide1 : SDTypeProfile<1, 5, [ 1848 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>, 1849 SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, 1850 SDTCisVT<5, XLenVT> 1851]>; 1852 1853def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1854def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1855def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1856def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 1857 1858let Predicates = [HasVInstructions] in { 1859 1860foreach vti = AllIntegerVectors in { 1861 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1862 VLOpFrag)), 1863 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 1864 1865 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef), 1866 (vti.Vector vti.RegClass:$rs1), 1867 GPR:$rs2, (vti.Mask true_mask), 1868 VLOpFrag)), 1869 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1870 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1871 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rd), 1872 (vti.Vector vti.RegClass:$rs1), 1873 GPR:$rs2, (vti.Mask true_mask), 1874 VLOpFrag)), 1875 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX#"_TU") 1876 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1877 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector undef), 1878 (vti.Vector vti.RegClass:$rs1), 1879 GPR:$rs2, (vti.Mask true_mask), 1880 VLOpFrag)), 1881 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 1882 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1883 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rd), 1884 (vti.Vector vti.RegClass:$rs1), 1885 GPR:$rs2, (vti.Mask true_mask), 1886 VLOpFrag)), 1887 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX#"_TU") 1888 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1889} 1890 1891foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1892 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1893 (vti.Vector vti.RegClass:$rs1), 1894 uimm5:$rs2, (vti.Mask true_mask), 1895 VLOpFrag)), 1896 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1897 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1898 GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 1899 1900 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1901 (vti.Vector vti.RegClass:$rs1), 1902 GPR:$rs2, (vti.Mask true_mask), 1903 VLOpFrag)), 1904 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1905 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1906 GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 1907 1908 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1909 (vti.Vector vti.RegClass:$rs1), 1910 uimm5:$rs2, (vti.Mask true_mask), 1911 VLOpFrag)), 1912 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1913 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1914 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1915 1916 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1917 (vti.Vector vti.RegClass:$rs1), 1918 GPR:$rs2, (vti.Mask true_mask), 1919 VLOpFrag)), 1920 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1921 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1922 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1923} 1924 1925} // Predicates = [HasVInstructions] 1926