1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// 0.10. This version is still experimental as the 'V' extension hasn't been 12/// ratified yet. 13/// 14/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 15/// 16/// Note: the patterns for RVV intrinsics are found in 17/// RISCVInstrInfoVPseudos.td. 18/// 19//===----------------------------------------------------------------------===// 20 21//===----------------------------------------------------------------------===// 22// Helpers to define the VL patterns. 23//===----------------------------------------------------------------------===// 24 25def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>, 26 SDTCisVT<2, XLenVT>]>; 27def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>, 28 SDTCisVT<2, XLenVT>]>; 29 30def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 31 SDTCisSameAs<0, 2>, 32 SDTCisVec<0>, SDTCisInt<0>, 33 SDTCVecEltisVT<3, i1>, 34 SDTCisSameNumEltsAs<0, 3>, 35 SDTCisVT<4, XLenVT>]>; 36 37def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<2, i1>, 40 SDTCisSameNumEltsAs<0, 2>, 41 SDTCisVT<3, XLenVT>]>; 42def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 43 SDTCisSameAs<0, 2>, 44 SDTCisVec<0>, SDTCisFP<0>, 45 SDTCVecEltisVT<3, i1>, 46 SDTCisSameNumEltsAs<0, 3>, 47 SDTCisVT<4, XLenVT>]>; 48 49def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 50 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 51 SDTCisVT<1, XLenVT>, 52 SDTCisVT<2, XLenVT>]>>; 53def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 54 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 55 SDTCisEltOfVec<1, 0>, 56 SDTCisVT<2, XLenVT>]>>; 57def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 59 SDTCisInt<0>, 60 SDTCisVT<2, XLenVT>, 61 SDTCisVT<3, XLenVT>]>>; 62def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 63 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 64 SDTCisFP<0>, 65 SDTCisEltOfVec<2, 0>, 66 SDTCisVT<3, XLenVT>]>>; 67 68def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL, 69 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 70def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL, 71 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 72 73def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 74def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 76def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 77def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 78def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 79def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 80def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 81def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 83def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 84def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 88def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 89def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 90def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 91def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 92 93def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 94def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 95def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 96def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 97 98def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 99def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 100def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 101def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 102def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 103def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 104def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 105def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 106def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 107def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 108 109def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 110 SDTCisSameAs<0, 2>, 111 SDTCisSameAs<0, 3>, 112 SDTCisVec<0>, SDTCisFP<0>, 113 SDTCVecEltisVT<4, i1>, 114 SDTCisSameNumEltsAs<0, 4>, 115 SDTCisVT<5, XLenVT>]>; 116def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 117 118def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 120 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 121]>; 122def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126 127def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 128def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 129def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 130 131def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 132 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 133 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 134]>; 135def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 136 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 137 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 138]>; 139 140def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 141def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 142def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 143def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 144 145def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 146 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 147 SDTCisVec<1>, 148 SDTCisSameNumEltsAs<0, 1>, 149 SDTCisSameAs<1, 2>, 150 SDTCisVT<3, OtherVT>, 151 SDTCisSameAs<0, 4>, 152 SDTCisVT<5, XLenVT>]>>; 153 154def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 155 SDTypeProfile<1, 4, [SDTCisVec<0>, 156 SDTCisSameAs<0, 1>, 157 SDTCisVT<2, XLenVT>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCisSameNumEltsAs<0, 2>, 166 SDTCisSameSizeAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 171 SDTypeProfile<1, 4, [SDTCisVec<0>, 172 SDTCisSameAs<0, 1>, 173 SDTCisInt<2>, 174 SDTCVecEltisVT<2, i16>, 175 SDTCisSameNumEltsAs<0, 2>, 176 SDTCVecEltisVT<3, i1>, 177 SDTCisSameNumEltsAs<0, 3>, 178 SDTCisVT<4, XLenVT>]>>; 179 180def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", 181 SDTypeProfile<1, 4, [SDTCisVec<0>, 182 SDTCisVec<1>, 183 SDTCisSameNumEltsAs<0, 1>, 184 SDTCVecEltisVT<1, i1>, 185 SDTCisSameAs<0, 2>, 186 SDTCisSameAs<2, 3>, 187 SDTCisVT<4, XLenVT>]>>; 188 189def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 190 SDTCisSameAs<0, 2>, 191 SDTCVecEltisVT<0, i1>, 192 SDTCisVT<3, XLenVT>]>; 193def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 194def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 195def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 196 197def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 198 199def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 200 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 201 202def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 203 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 204 SDTCisVec<1>, SDTCisInt<1>, 205 SDTCVecEltisVT<2, i1>, 206 SDTCisSameNumEltsAs<1, 2>, 207 SDTCisVT<3, XLenVT>]>>; 208 209def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 210 SDTCisSameNumEltsAs<0, 1>, 211 SDTCisSameNumEltsAs<1, 2>, 212 SDTCVecEltisVT<2, i1>, 213 SDTCisVT<3, XLenVT>]>; 214def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 215def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 216 217def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 218 SDTypeProfile<1, 3, [SDTCisVec<0>, 219 SDTCisVec<1>, 220 SDTCisSameNumEltsAs<0, 2>, 221 SDTCVecEltisVT<2, i1>, 222 SDTCisVT<3, XLenVT>]>>; 223 224def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 225 SDTCisSameNumEltsAs<0, 1>, 226 SDTCisSameAs<1, 2>, 227 SDTCisSameNumEltsAs<1, 3>, 228 SDTCVecEltisVT<3, i1>, 229 SDTCisVT<4, XLenVT>]>; 230def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 231def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 232def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 233 234def SDTRVVVecReduce : SDTypeProfile<1, 5, [ 235 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 236 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT> 237]>; 238 239def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 240 (riscv_mul_vl node:$A, node:$B, node:$C, 241 node:$D), [{ 242 return N->hasOneUse(); 243}]>; 244 245def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 246 (riscv_vwmul_vl node:$A, node:$B, node:$C, 247 node:$D), [{ 248 return N->hasOneUse(); 249}]>; 250 251def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 252 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 253 node:$D), [{ 254 return N->hasOneUse(); 255}]>; 256 257foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 258 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 259 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 260 261// Ignore the vl operand. 262def SplatFPOp : PatFrag<(ops node:$op), 263 (riscv_vfmv_v_f_vl node:$op, srcvalue)>; 264 265def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 266def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 267def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 268def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 269 270multiclass VPatBinaryVL_VV<SDNode vop, 271 string instruction_name, 272 ValueType result_type, 273 ValueType op_type, 274 ValueType mask_type, 275 int sew, 276 LMULInfo vlmul, 277 VReg op_reg_class> { 278 def : Pat<(result_type (vop 279 (op_type op_reg_class:$rs1), 280 (op_type op_reg_class:$rs2), 281 (mask_type true_mask), 282 VLOpFrag)), 283 (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX) 284 op_reg_class:$rs1, 285 op_reg_class:$rs2, 286 GPR:$vl, sew)>; 287 def : Pat<(result_type (vop 288 (op_type op_reg_class:$rs1), 289 (op_type op_reg_class:$rs2), 290 (mask_type V0), 291 VLOpFrag)), 292 (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_MASK") 293 (result_type (IMPLICIT_DEF)), 294 op_reg_class:$rs1, 295 op_reg_class:$rs2, 296 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 297} 298 299multiclass VPatBinaryVL_XI<SDNode vop, 300 string instruction_name, 301 string suffix, 302 ValueType result_type, 303 ValueType vop_type, 304 ValueType mask_type, 305 int sew, 306 LMULInfo vlmul, 307 VReg vop_reg_class, 308 ComplexPattern SplatPatKind, 309 DAGOperand xop_kind> { 310 def : Pat<(result_type (vop 311 (vop_type vop_reg_class:$rs1), 312 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))), 313 (mask_type true_mask), 314 VLOpFrag)), 315 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX) 316 vop_reg_class:$rs1, 317 xop_kind:$rs2, 318 GPR:$vl, sew)>; 319 def : Pat<(result_type (vop 320 (vop_type vop_reg_class:$rs1), 321 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))), 322 (mask_type V0), 323 VLOpFrag)), 324 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 325 (result_type (IMPLICIT_DEF)), 326 vop_reg_class:$rs1, 327 xop_kind:$rs2, 328 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 329} 330 331multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 332 foreach vti = AllIntegerVectors in { 333 defm : VPatBinaryVL_VV<vop, instruction_name, 334 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 335 vti.LMul, vti.RegClass>; 336 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 337 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 338 vti.LMul, vti.RegClass, SplatPat, GPR>; 339 } 340} 341 342multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 343 Operand ImmType = simm5> 344 : VPatBinaryVL_VV_VX<vop, instruction_name> { 345 foreach vti = AllIntegerVectors in { 346 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 347 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 348 vti.LMul, vti.RegClass, 349 !cast<ComplexPattern>(SplatPat#_#ImmType), 350 ImmType>; 351 } 352} 353 354multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 355 foreach VtiToWti = AllWidenableIntVectors in { 356 defvar vti = VtiToWti.Vti; 357 defvar wti = VtiToWti.Wti; 358 defm : VPatBinaryVL_VV<vop, instruction_name, 359 wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 360 vti.LMul, vti.RegClass>; 361 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 362 wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 363 vti.LMul, vti.RegClass, SplatPat, GPR>; 364 } 365} 366 367multiclass VPatBinaryVL_VF<SDNode vop, 368 string instruction_name, 369 ValueType result_type, 370 ValueType vop_type, 371 ValueType mask_type, 372 int sew, 373 LMULInfo vlmul, 374 VReg vop_reg_class, 375 RegisterClass scalar_reg_class> { 376 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 377 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 378 (mask_type true_mask), 379 VLOpFrag)), 380 (!cast<Instruction>(instruction_name#"_"#vlmul.MX) 381 vop_reg_class:$rs1, 382 scalar_reg_class:$rs2, 383 GPR:$vl, sew)>; 384 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 385 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 386 (mask_type V0), 387 VLOpFrag)), 388 (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_MASK") 389 (result_type (IMPLICIT_DEF)), 390 vop_reg_class:$rs1, 391 scalar_reg_class:$rs2, 392 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 393} 394 395multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 396 foreach vti = AllFloatVectors in { 397 defm : VPatBinaryVL_VV<vop, instruction_name, 398 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 399 vti.LMul, vti.RegClass>; 400 defm : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 401 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 402 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 403 } 404} 405 406multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 407 foreach fvti = AllFloatVectors in 408 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 409 fvti.RegClass:$rs1, 410 (fvti.Mask true_mask), 411 VLOpFrag)), 412 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 413 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 414 GPR:$vl, fvti.Log2SEW)>; 415} 416 417multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 418 CondCode cc> { 419 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 420 vti.RegClass:$rs2, cc, 421 (vti.Mask true_mask), 422 VLOpFrag)), 423 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 424 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 425 vti.Log2SEW)>; 426} 427 428// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 429multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 430 CondCode cc, CondCode invcc> : 431 VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 432 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 433 vti.RegClass:$rs1, invcc, 434 (vti.Mask true_mask), 435 VLOpFrag)), 436 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 437 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 438 vti.Log2SEW)>; 439} 440 441multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 442 CondCode cc, CondCode invcc> { 443 defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX); 444 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 445 (SplatPat (XLenVT GPR:$rs2)), cc, 446 (vti.Mask true_mask), 447 VLOpFrag)), 448 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 449 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 450 (vti.Vector vti.RegClass:$rs1), invcc, 451 (vti.Mask true_mask), 452 VLOpFrag)), 453 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 454} 455 456multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 457 CondCode cc, CondCode invcc> { 458 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 459 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 460 (SplatPat_simm5 simm5:$rs2), cc, 461 (vti.Mask true_mask), 462 VLOpFrag)), 463 (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.Log2SEW)>; 464 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 465 (vti.Vector vti.RegClass:$rs1), invcc, 466 (vti.Mask true_mask), 467 VLOpFrag)), 468 (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; 469} 470 471multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name, 472 CondCode cc, ComplexPattern splatpat_kind> { 473 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 474 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 475 (splatpat_kind simm5:$rs2), cc, 476 (vti.Mask true_mask), 477 VLOpFrag)), 478 (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), 479 GPR:$vl, vti.Log2SEW)>; 480} 481 482multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 483 string inst_name, 484 string swapped_op_inst_name> { 485 foreach fvti = AllFloatVectors in { 486 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 487 fvti.RegClass:$rs2, 488 cc, 489 (fvti.Mask true_mask), 490 VLOpFrag)), 491 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX) 492 fvti.RegClass:$rs1, fvti.RegClass:$rs2, GPR:$vl, fvti.Log2SEW)>; 493 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 494 (SplatFPOp fvti.ScalarRegClass:$rs2), 495 cc, 496 (fvti.Mask true_mask), 497 VLOpFrag)), 498 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 499 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 500 GPR:$vl, fvti.Log2SEW)>; 501 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 502 (fvti.Vector fvti.RegClass:$rs1), 503 cc, 504 (fvti.Mask true_mask), 505 VLOpFrag)), 506 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 507 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 508 GPR:$vl, fvti.Log2SEW)>; 509 } 510} 511 512multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 513 list <VTypeInfoToFraction> fraction_list> { 514 foreach vtiTofti = fraction_list in { 515 defvar vti = vtiTofti.Vti; 516 defvar fti = vtiTofti.Fti; 517 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 518 true_mask, VLOpFrag)), 519 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX) 520 fti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 521 } 522} 523 524multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 525 foreach fvti = AllFloatVectors in { 526 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 527 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 528 (fvti.Mask true_mask), 529 VLOpFrag)), 530 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 531 fvti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 532 } 533} 534 535multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 536 foreach fvti = AllFloatVectors in { 537 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 538 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 539 (ivti.Mask true_mask), 540 VLOpFrag)), 541 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 542 ivti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 543 } 544} 545 546multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 547 foreach fvtiToFWti = AllWidenableFloatVectors in { 548 defvar fvti = fvtiToFWti.Vti; 549 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 550 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 551 (fvti.Mask true_mask), 552 VLOpFrag)), 553 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 554 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 555 } 556} 557 558multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 559 foreach vtiToWti = AllWidenableIntToFloatVectors in { 560 defvar ivti = vtiToWti.Vti; 561 defvar fwti = vtiToWti.Wti; 562 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 563 (ivti.Mask true_mask), 564 VLOpFrag)), 565 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 566 ivti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 567 } 568} 569 570multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 571 foreach vtiToWti = AllWidenableIntToFloatVectors in { 572 defvar vti = vtiToWti.Vti; 573 defvar fwti = vtiToWti.Wti; 574 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 575 (fwti.Mask true_mask), 576 VLOpFrag)), 577 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX) 578 fwti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 579 } 580} 581 582multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 583 foreach fvtiToFWti = AllWidenableFloatVectors in { 584 defvar fvti = fvtiToFWti.Vti; 585 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 586 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 587 (iwti.Mask true_mask), 588 VLOpFrag)), 589 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 590 iwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 591 } 592} 593 594multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 595 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 596 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 597 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 598 (vti.Mask true_mask), 599 VLOpFrag)), 600 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 601 (vti_m1.Vector VR:$merge), 602 (vti.Vector vti.RegClass:$rs1), 603 (vti_m1.Vector VR:$rs2), 604 GPR:$vl, vti.Log2SEW)>; 605 606 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 607 (vti.Mask V0), VLOpFrag)), 608 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 609 (vti_m1.Vector VR:$merge), 610 (vti.Vector vti.RegClass:$rs1), 611 (vti_m1.Vector VR:$rs2), 612 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 613 } 614} 615 616multiclass VPatBinarySDNodeExt_V_WV<SDNode op, PatFrags extop, string instruction_name> { 617 foreach vti = AllWidenableIntVectors in { 618 def : Pat< 619 (vti.Vti.Vector 620 (riscv_trunc_vector_vl 621 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 622 (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), 623 (riscv_vmset_vl VLMax), 624 VLMax)), 625 (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX) 626 vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1, 627 vti.Vti.AVL, vti.Vti.Log2SEW)>; 628 } 629} 630 631multiclass VPatBinarySDNodeExt_V_WX<SDNode op, PatFrags extop, string instruction_name> { 632 foreach vti = AllWidenableIntVectors in { 633 def : Pat< 634 (vti.Vti.Vector 635 (riscv_trunc_vector_vl 636 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 637 (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))), 638 (riscv_vmset_vl VLMax), 639 VLMax)), 640 (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) 641 vti.Wti.RegClass:$rs2, GPR:$rs1, 642 vti.Vti.AVL, vti.Vti.Log2SEW)>; 643 } 644} 645 646 647multiclass VPatBinarySDNode_V_WV<SDNode op, string instruction_name> { 648 defm : VPatBinarySDNodeExt_V_WV<op, sext_oneuse, instruction_name>; 649 defm : VPatBinarySDNodeExt_V_WV<op, zext_oneuse, instruction_name>; 650} 651 652multiclass VPatBinarySDNode_V_WX<SDNode op, string instruction_name> { 653 defm : VPatBinarySDNodeExt_V_WX<op, sext_oneuse, instruction_name>; 654 defm : VPatBinarySDNodeExt_V_WX<op, zext_oneuse, instruction_name>; 655} 656 657//===----------------------------------------------------------------------===// 658// Patterns. 659//===----------------------------------------------------------------------===// 660 661let Predicates = [HasVInstructions] in { 662 663// 7.4. Vector Unit-Stride Instructions 664foreach vti = AllVectors in { 665 defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX); 666 defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX); 667 // Load 668 def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)), 669 (load_instr BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>; 670 // Store 671 def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1, 672 VLOpFrag), 673 (store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>; 674} 675 676foreach mti = AllMasks in { 677 defvar load_instr = !cast<Instruction>("PseudoVLM_V_"#mti.BX); 678 defvar store_instr = !cast<Instruction>("PseudoVSM_V_"#mti.BX); 679 def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)), 680 (load_instr BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>; 681 def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1, 682 VLOpFrag), 683 (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>; 684} 685 686// 12.1. Vector Single-Width Integer Add and Subtract 687defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 688defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 689// Handle VRSUB specially since it's the only integer binary op with reversed 690// pattern operands 691foreach vti = AllIntegerVectors in { 692 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 693 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 694 VLOpFrag), 695 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX) 696 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 697 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 698 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 699 VLOpFrag), 700 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 701 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 702 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 703 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 704 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 705 VLOpFrag), 706 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX) 707 vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; 708 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 709 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 710 VLOpFrag), 711 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 712 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 713 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 714} 715 716// 12.2. Vector Widening Integer Add/Subtract 717defm : VPatBinaryWVL_VV_VX<riscv_vwaddu_vl, "PseudoVWADDU">; 718 719// 12.3. Vector Integer Extension 720defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 721 AllFractionableVF2IntVectors>; 722defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 723 AllFractionableVF2IntVectors>; 724defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 725 AllFractionableVF4IntVectors>; 726defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 727 AllFractionableVF4IntVectors>; 728defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 729 AllFractionableVF8IntVectors>; 730defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 731 AllFractionableVF8IntVectors>; 732 733// 12.5. Vector Bitwise Logical Instructions 734defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 735defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 736defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 737 738// 12.6. Vector Single-Width Bit Shift Instructions 739defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 740defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 741defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 742 743foreach vti = AllIntegerVectors in { 744 // Emit shift by 1 as an add since it might be faster. 745 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 746 (riscv_vmv_v_x_vl 1, (XLenVT srcvalue)), 747 (vti.Mask true_mask), 748 VLOpFrag), 749 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 750 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 751} 752 753// 12.7. Vector Narrowing Integer Right Shift Instructions 754defm : VPatBinarySDNode_V_WV<srl, "PseudoVNSRL">; 755defm : VPatBinarySDNode_V_WX<srl, "PseudoVNSRL">; 756defm : VPatBinarySDNode_V_WV<sra, "PseudoVNSRA">; 757defm : VPatBinarySDNode_V_WX<sra, "PseudoVNSRA">; 758 759foreach vtiTowti = AllWidenableIntVectors in { 760 defvar vti = vtiTowti.Vti; 761 defvar wti = vtiTowti.Wti; 762 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 763 (vti.Mask true_mask), 764 VLOpFrag)), 765 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) 766 wti.RegClass:$rs1, 0, GPR:$vl, vti.Log2SEW)>; 767 768 def : Pat<(vti.Vector 769 (riscv_trunc_vector_vl 770 (wti.Vector 771 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 772 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 773 (!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX) 774 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 775 def : Pat<(vti.Vector 776 (riscv_trunc_vector_vl 777 (wti.Vector 778 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 779 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 780 (!cast<Instruction>("PseudoVNSRA_WI_"#vti.LMul.MX) 781 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 782 783 def : Pat<(vti.Vector 784 (riscv_trunc_vector_vl 785 (wti.Vector 786 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 787 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 788 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 789 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 790 def : Pat<(vti.Vector 791 (riscv_trunc_vector_vl 792 (wti.Vector 793 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 794 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 795 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) 796 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 797} 798 799// 12.8. Vector Integer Comparison Instructions 800foreach vti = AllIntegerVectors in { 801 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 802 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 803 804 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 805 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 806 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 807 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 808 809 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 810 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 811 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 812 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 813 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 814 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 815 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 816 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 817 // There is no VMSGE(U)_VX instruction 818 819 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 820 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 821 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 822 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 823 824 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT, 825 SplatPat_simm5_plus1>; 826 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT, 827 SplatPat_simm5_plus1_nonzero>; 828 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE, 829 SplatPat_simm5_plus1>; 830 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGTU", SETUGE, 831 SplatPat_simm5_plus1_nonzero>; 832} // foreach vti = AllIntegerVectors 833 834// 12.9. Vector Integer Min/Max Instructions 835defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 836defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 837defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 838defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 839 840// 12.10. Vector Single-Width Integer Multiply Instructions 841defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 842defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 843defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 844 845// 12.11. Vector Integer Divide Instructions 846defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 847defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 848defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 849defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 850 851// 12.12. Vector Widening Integer Multiply Instructions 852defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 853defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 854 855// 12.13 Vector Single-Width Integer Multiply-Add Instructions 856foreach vti = AllIntegerVectors in { 857 // NOTE: We choose VMADD because it has the most commuting freedom. So it 858 // works best with how TwoAddressInstructionPass tries commuting. 859 defvar suffix = vti.LMul.MX; 860 def : Pat<(vti.Vector 861 (riscv_add_vl vti.RegClass:$rs2, 862 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 863 vti.RegClass:$rd, 864 (vti.Mask true_mask), VLOpFrag), 865 (vti.Mask true_mask), VLOpFrag)), 866 (!cast<Instruction>("PseudoVMADD_VV_"# suffix) 867 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 868 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 869 def : Pat<(vti.Vector 870 (riscv_sub_vl vti.RegClass:$rs2, 871 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 872 vti.RegClass:$rd, 873 (vti.Mask true_mask), VLOpFrag), 874 (vti.Mask true_mask), VLOpFrag)), 875 (!cast<Instruction>("PseudoVNMSUB_VV_"# suffix) 876 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 877 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 878 879 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 880 // commutable. 881 def : Pat<(vti.Vector 882 (riscv_add_vl vti.RegClass:$rs2, 883 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 884 vti.RegClass:$rd, 885 (vti.Mask true_mask), VLOpFrag), 886 (vti.Mask true_mask), VLOpFrag)), 887 (!cast<Instruction>("PseudoVMADD_VX_" # suffix) 888 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 889 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 890 def : Pat<(vti.Vector 891 (riscv_sub_vl vti.RegClass:$rs2, 892 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 893 vti.RegClass:$rd, 894 (vti.Mask true_mask), 895 VLOpFrag), 896 (vti.Mask true_mask), VLOpFrag)), 897 (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix) 898 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 899 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 900} 901 902// 12.14. Vector Widening Integer Multiply-Add Instructions 903foreach vtiTowti = AllWidenableIntVectors in { 904 defvar vti = vtiTowti.Vti; 905 defvar wti = vtiTowti.Wti; 906 def : Pat<(wti.Vector 907 (riscv_add_vl wti.RegClass:$rd, 908 (riscv_vwmul_vl_oneuse vti.RegClass:$rs1, 909 (vti.Vector vti.RegClass:$rs2), 910 (vti.Mask true_mask), VLOpFrag), 911 (vti.Mask true_mask), VLOpFrag)), 912 (!cast<Instruction>("PseudoVWMACC_VV_" # vti.LMul.MX) 913 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 914 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 915 def : Pat<(wti.Vector 916 (riscv_add_vl wti.RegClass:$rd, 917 (riscv_vwmulu_vl_oneuse vti.RegClass:$rs1, 918 (vti.Vector vti.RegClass:$rs2), 919 (vti.Mask true_mask), VLOpFrag), 920 (vti.Mask true_mask), VLOpFrag)), 921 (!cast<Instruction>("PseudoVWMACCU_VV_" # vti.LMul.MX) 922 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 923 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 924 925 def : Pat<(wti.Vector 926 (riscv_add_vl wti.RegClass:$rd, 927 (riscv_vwmul_vl_oneuse (SplatPat XLenVT:$rs1), 928 (vti.Vector vti.RegClass:$rs2), 929 (vti.Mask true_mask), VLOpFrag), 930 (vti.Mask true_mask), VLOpFrag)), 931 (!cast<Instruction>("PseudoVWMACC_VX_" # vti.LMul.MX) 932 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 933 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 934 def : Pat<(wti.Vector 935 (riscv_add_vl wti.RegClass:$rd, 936 (riscv_vwmulu_vl_oneuse (SplatPat XLenVT:$rs1), 937 (vti.Vector vti.RegClass:$rs2), 938 (vti.Mask true_mask), VLOpFrag), 939 (vti.Mask true_mask), VLOpFrag)), 940 (!cast<Instruction>("PseudoVWMACCU_VX_" # vti.LMul.MX) 941 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 942 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 943} 944 945// 12.15. Vector Integer Merge Instructions 946foreach vti = AllIntegerVectors in { 947 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 948 vti.RegClass:$rs1, 949 vti.RegClass:$rs2, 950 VLOpFrag)), 951 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 952 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 953 GPR:$vl, vti.Log2SEW)>; 954 955 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 956 (SplatPat XLenVT:$rs1), 957 vti.RegClass:$rs2, 958 VLOpFrag)), 959 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 960 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 961 962 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 963 (SplatPat_simm5 simm5:$rs1), 964 vti.RegClass:$rs2, 965 VLOpFrag)), 966 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 967 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 968} 969 970// 12.16. Vector Integer Move Instructions 971foreach vti = AllIntegerVectors in { 972 def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, VLOpFrag)), 973 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 974 $rs2, GPR:$vl, vti.Log2SEW)>; 975 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 976 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (ImmPat XLenVT:$imm5), 977 VLOpFrag)), 978 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 979 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 980} 981 982// 12.1. Vector Single-Width Saturating Add and Subtract 983defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 984defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 985defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 986defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 987 988} // Predicates = [HasVInstructions] 989 990// 15.1. Vector Single-Width Integer Reduction Instructions 991let Predicates = [HasVInstructions] in { 992defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 993defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 994defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 995defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 996defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 997defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 998defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 999defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 1000} // Predicates = [HasVInstructions] 1001 1002// 15.3. Vector Single-Width Floating-Point Reduction Instructions 1003let Predicates = [HasVInstructionsAnyF] in { 1004defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 1005defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>; 1006defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 1007defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 1008} // Predicates = [HasVInstructionsAnyF] 1009 1010let Predicates = [HasVInstructionsAnyF] in { 1011 1012// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 1013defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 1014defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 1015defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 1016 1017// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 1018defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 1019defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 1020defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 1021 1022// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 1023foreach vti = AllFloatVectors in { 1024 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 1025 // works best with how TwoAddressInstructionPass tries commuting. 1026 defvar suffix = vti.LMul.MX; 1027 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1028 vti.RegClass:$rs2, (vti.Mask true_mask), 1029 VLOpFrag)), 1030 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 1031 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1032 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1033 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1034 (riscv_fneg_vl vti.RegClass:$rs2, 1035 (vti.Mask true_mask), 1036 VLOpFrag), 1037 (vti.Mask true_mask), 1038 VLOpFrag)), 1039 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 1040 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1041 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1042 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1043 (vti.Mask true_mask), 1044 VLOpFrag), 1045 vti.RegClass:$rd, 1046 (riscv_fneg_vl vti.RegClass:$rs2, 1047 (vti.Mask true_mask), 1048 VLOpFrag), 1049 (vti.Mask true_mask), 1050 VLOpFrag)), 1051 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 1052 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1053 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1054 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1055 (vti.Mask true_mask), 1056 VLOpFrag), 1057 vti.RegClass:$rd, vti.RegClass:$rs2, 1058 (vti.Mask true_mask), 1059 VLOpFrag)), 1060 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 1061 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1062 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1063 1064 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 1065 // commutable. 1066 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1067 vti.RegClass:$rd, vti.RegClass:$rs2, 1068 (vti.Mask true_mask), 1069 VLOpFrag)), 1070 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1071 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1072 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1073 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1074 vti.RegClass:$rd, 1075 (riscv_fneg_vl vti.RegClass:$rs2, 1076 (vti.Mask true_mask), 1077 VLOpFrag), 1078 (vti.Mask true_mask), 1079 VLOpFrag)), 1080 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1081 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1082 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1083 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1084 (riscv_fneg_vl vti.RegClass:$rd, 1085 (vti.Mask true_mask), 1086 VLOpFrag), 1087 (riscv_fneg_vl vti.RegClass:$rs2, 1088 (vti.Mask true_mask), 1089 VLOpFrag), 1090 (vti.Mask true_mask), 1091 VLOpFrag)), 1092 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1093 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1094 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1095 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1096 (riscv_fneg_vl vti.RegClass:$rd, 1097 (vti.Mask true_mask), 1098 VLOpFrag), 1099 vti.RegClass:$rs2, 1100 (vti.Mask true_mask), 1101 VLOpFrag)), 1102 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1103 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1104 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1105 1106 // The splat might be negated. 1107 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1108 (vti.Mask true_mask), 1109 VLOpFrag), 1110 vti.RegClass:$rd, 1111 (riscv_fneg_vl vti.RegClass:$rs2, 1112 (vti.Mask true_mask), 1113 VLOpFrag), 1114 (vti.Mask true_mask), 1115 VLOpFrag)), 1116 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1117 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1118 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1119 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1120 (vti.Mask true_mask), 1121 VLOpFrag), 1122 vti.RegClass:$rd, vti.RegClass:$rs2, 1123 (vti.Mask true_mask), 1124 VLOpFrag)), 1125 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1126 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1127 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1128} 1129 1130// 14.11. Vector Floating-Point MIN/MAX Instructions 1131defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1132defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1133 1134// 14.13. Vector Floating-Point Compare Instructions 1135defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1136defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1137 1138defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1139defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1140 1141defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1142defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1143 1144defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1145defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1146 1147foreach vti = AllFloatVectors in { 1148 // 14.8. Vector Floating-Point Square-Root Instruction 1149 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1150 VLOpFrag), 1151 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1152 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1153 1154 // 14.12. Vector Floating-Point Sign-Injection Instructions 1155 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1156 VLOpFrag), 1157 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1158 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1159 // Handle fneg with VFSGNJN using the same input for both operands. 1160 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1161 VLOpFrag), 1162 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1163 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1164 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1165 (vti.Vector vti.RegClass:$rs2), 1166 (vti.Mask true_mask), 1167 VLOpFrag), 1168 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1169 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1170 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1171 (riscv_fneg_vl vti.RegClass:$rs2, 1172 (vti.Mask true_mask), 1173 VLOpFrag), 1174 (vti.Mask true_mask), 1175 VLOpFrag), 1176 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1177 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1178 1179 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1180 (SplatFPOp vti.ScalarRegClass:$rs2), 1181 (vti.Mask true_mask), 1182 VLOpFrag), 1183 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1184 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1185} 1186 1187foreach fvti = AllFloatVectors in { 1188 // Floating-point vselects: 1189 // 12.15. Vector Integer Merge Instructions 1190 // 14.15. Vector Floating-Point Merge Instruction 1191 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1192 fvti.RegClass:$rs1, 1193 fvti.RegClass:$rs2, 1194 VLOpFrag)), 1195 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1196 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1197 GPR:$vl, fvti.Log2SEW)>; 1198 1199 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1200 (SplatFPOp fvti.ScalarRegClass:$rs1), 1201 fvti.RegClass:$rs2, 1202 VLOpFrag)), 1203 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1204 fvti.RegClass:$rs2, 1205 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1206 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1207 1208 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1209 (SplatFPOp (fvti.Scalar fpimm0)), 1210 fvti.RegClass:$rs2, 1211 VLOpFrag)), 1212 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1213 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1214 1215 // 14.16. Vector Floating-Point Move Instruction 1216 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1217 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1218 (fvti.Scalar (fpimm0)), VLOpFrag)), 1219 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1220 0, GPR:$vl, fvti.Log2SEW)>; 1221 1222 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1223 (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1224 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1225 fvti.LMul.MX) 1226 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1227 GPR:$vl, fvti.Log2SEW)>; 1228 1229 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1230 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1231 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1232 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1233 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1234 1235 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1236 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1237 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1238 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1239 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1240 foreach fvtiToFWti = AllWidenableFloatVectors in { 1241 defvar fvti = fvtiToFWti.Vti; 1242 defvar fwti = fvtiToFWti.Wti; 1243 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1244 (fvti.Mask true_mask), 1245 VLOpFrag)), 1246 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX) 1247 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1248 } 1249 1250 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1251 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1252 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1253 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1254 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1255 foreach fvtiToFWti = AllWidenableFloatVectors in { 1256 defvar fvti = fvtiToFWti.Vti; 1257 defvar fwti = fvtiToFWti.Wti; 1258 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1259 (fwti.Mask true_mask), 1260 VLOpFrag)), 1261 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX) 1262 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1263 1264 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1265 (fwti.Mask true_mask), 1266 VLOpFrag)), 1267 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX) 1268 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1269 } 1270} 1271 1272} // Predicates = [HasVInstructionsAnyF] 1273 1274let Predicates = [HasVInstructions] in { 1275 1276foreach mti = AllMasks in { 1277 // 16.1 Vector Mask-Register Logical Instructions 1278 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1279 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1280 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1281 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1282 1283 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1284 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1285 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1286 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1287 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1288 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1289 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1290 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1291 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1292 1293 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1294 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1295 VLOpFrag)), 1296 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 1297 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1298 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1299 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1300 VLOpFrag)), 1301 (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 1302 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1303 // XOR is associative so we need 2 patterns for VMXNOR. 1304 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1305 VLOpFrag), 1306 VR:$rs2, VLOpFrag)), 1307 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1308 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1309 1310 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1311 VLOpFrag), 1312 VLOpFrag)), 1313 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1314 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1315 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1316 VLOpFrag), 1317 VLOpFrag)), 1318 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1319 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1320 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1321 VLOpFrag), 1322 VLOpFrag)), 1323 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1324 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1325 1326 // Match the not idiom to the vmnot.m pseudo. 1327 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1328 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1329 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1330 1331 // 16.2 Vector count population in mask vcpop.m 1332 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1333 VLOpFrag)), 1334 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 1335 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1336 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 1337 VLOpFrag)), 1338 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 1339 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 1340} 1341 1342} // Predicates = [HasVInstructions] 1343 1344let Predicates = [HasVInstructions] in { 1345// 17.1. Integer Scalar Move Instructions 1346// 17.4. Vector Register Gather Instruction 1347foreach vti = AllIntegerVectors in { 1348 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1349 vti.ScalarRegClass:$rs1, 1350 VLOpFrag)), 1351 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1352 vti.RegClass:$merge, 1353 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1354 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1355 (vti.Vector vti.RegClass:$rs1), 1356 (vti.Mask true_mask), 1357 VLOpFrag)), 1358 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1359 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1360 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1361 (vti.Mask true_mask), 1362 VLOpFrag)), 1363 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1364 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1365 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1366 (vti.Mask true_mask), 1367 VLOpFrag)), 1368 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1369 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1370 1371 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1372 (riscv_vrgather_vv_vl 1373 vti.RegClass:$rs2, 1374 vti.RegClass:$rs1, 1375 (vti.Mask true_mask), 1376 VLOpFrag), 1377 vti.RegClass:$merge, 1378 VLOpFrag)), 1379 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1380 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1381 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1382 1383 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1384 (riscv_vrgather_vx_vl 1385 vti.RegClass:$rs2, 1386 uimm5:$imm, 1387 (vti.Mask true_mask), 1388 VLOpFrag), 1389 vti.RegClass:$merge, 1390 VLOpFrag)), 1391 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1392 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1393 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1394 1395 // emul = lmul * 16 / sew 1396 defvar vlmul = vti.LMul; 1397 defvar octuple_lmul = vlmul.octuple; 1398 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1399 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1400 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1401 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1402 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1403 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1404 (ivti.Vector ivti.RegClass:$rs1), 1405 (vti.Mask true_mask), 1406 VLOpFrag)), 1407 (!cast<Instruction>(inst) 1408 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1409 1410 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1411 (riscv_vrgatherei16_vv_vl 1412 vti.RegClass:$rs2, 1413 (ivti.Vector ivti.RegClass:$rs1), 1414 (vti.Mask true_mask), 1415 VLOpFrag), 1416 vti.RegClass:$merge, 1417 VLOpFrag)), 1418 (!cast<Instruction>(inst#"_MASK") 1419 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1420 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1421 } 1422} 1423 1424} // Predicates = [HasVInstructions] 1425 1426let Predicates = [HasVInstructionsAnyF] in { 1427 1428// 17.2. Floating-Point Scalar Move Instructions 1429foreach vti = AllFloatVectors in { 1430 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1431 (vti.Scalar (fpimm0)), 1432 VLOpFrag)), 1433 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1434 vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>; 1435 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1436 vti.ScalarRegClass:$rs1, 1437 VLOpFrag)), 1438 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1439 vti.RegClass:$merge, 1440 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1441 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1442 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1443 (ivti.Vector vti.RegClass:$rs1), 1444 (vti.Mask true_mask), 1445 VLOpFrag)), 1446 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1447 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1448 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1449 (vti.Mask true_mask), 1450 VLOpFrag)), 1451 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1452 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1453 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1454 (vti.Mask true_mask), 1455 VLOpFrag)), 1456 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1457 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1458 1459 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1460 (riscv_vrgather_vv_vl 1461 vti.RegClass:$rs2, 1462 (ivti.Vector vti.RegClass:$rs1), 1463 (vti.Mask true_mask), 1464 VLOpFrag), 1465 vti.RegClass:$merge, 1466 VLOpFrag)), 1467 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1468 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1469 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1470 1471 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1472 (riscv_vrgather_vx_vl 1473 vti.RegClass:$rs2, 1474 uimm5:$imm, 1475 (vti.Mask true_mask), 1476 VLOpFrag), 1477 vti.RegClass:$merge, 1478 VLOpFrag)), 1479 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1480 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1481 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1482 1483 defvar vlmul = vti.LMul; 1484 defvar octuple_lmul = vlmul.octuple; 1485 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1486 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1487 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1488 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1489 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1490 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1491 (ivti.Vector ivti.RegClass:$rs1), 1492 (vti.Mask true_mask), 1493 VLOpFrag)), 1494 (!cast<Instruction>(inst) 1495 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1496 1497 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1498 (riscv_vrgatherei16_vv_vl 1499 vti.RegClass:$rs2, 1500 (ivti.Vector ivti.RegClass:$rs1), 1501 (vti.Mask true_mask), 1502 VLOpFrag), 1503 vti.RegClass:$merge, 1504 VLOpFrag)), 1505 (!cast<Instruction>(inst#"_MASK") 1506 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1507 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1508 } 1509} 1510 1511} // Predicates = [HasVInstructionsAnyF] 1512 1513//===----------------------------------------------------------------------===// 1514// Miscellaneous RISCVISD SDNodes 1515//===----------------------------------------------------------------------===// 1516 1517def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1518 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1519 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1520 1521def SDTRVVSlide : SDTypeProfile<1, 5, [ 1522 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1523 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1524]>; 1525def SDTRVVSlide1 : SDTypeProfile<1, 4, [ 1526 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisInt<0>, SDTCisVT<2, XLenVT>, 1527 SDTCVecEltisVT<3, i1>, SDTCisSameNumEltsAs<0, 3>, SDTCisVT<4, XLenVT> 1528]>; 1529 1530def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1531def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1532def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1533def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 1534 1535let Predicates = [HasVInstructions] in { 1536 1537foreach vti = AllIntegerVectors in { 1538 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1539 VLOpFrag)), 1540 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 1541 1542 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rs1), 1543 GPR:$rs2, (vti.Mask true_mask), 1544 VLOpFrag)), 1545 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1546 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1547 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rs1), 1548 GPR:$rs2, (vti.Mask true_mask), 1549 VLOpFrag)), 1550 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 1551 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1552} 1553 1554foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1555 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1556 (vti.Vector vti.RegClass:$rs1), 1557 uimm5:$rs2, (vti.Mask true_mask), 1558 VLOpFrag)), 1559 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1560 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1561 GPR:$vl, vti.Log2SEW)>; 1562 1563 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1564 (vti.Vector vti.RegClass:$rs1), 1565 GPR:$rs2, (vti.Mask true_mask), 1566 VLOpFrag)), 1567 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1568 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1569 GPR:$vl, vti.Log2SEW)>; 1570 1571 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1572 (vti.Vector vti.RegClass:$rs1), 1573 uimm5:$rs2, (vti.Mask true_mask), 1574 VLOpFrag)), 1575 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1576 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1577 GPR:$vl, vti.Log2SEW)>; 1578 1579 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1580 (vti.Vector vti.RegClass:$rs1), 1581 GPR:$rs2, (vti.Mask true_mask), 1582 VLOpFrag)), 1583 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1584 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1585 GPR:$vl, vti.Log2SEW)>; 1586} 1587 1588} // Predicates = [HasVInstructions] 1589