1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// 0.10. This version is still experimental as the 'V' extension hasn't been 12/// ratified yet. 13/// 14/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 15/// 16/// Note: the patterns for RVV intrinsics are found in 17/// RISCVInstrInfoVPseudos.td. 18/// 19//===----------------------------------------------------------------------===// 20 21//===----------------------------------------------------------------------===// 22// Helpers to define the VL patterns. 23//===----------------------------------------------------------------------===// 24 25def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>, 26 SDTCisVT<2, XLenVT>]>; 27def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>, 28 SDTCisVT<2, XLenVT>]>; 29 30def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 31 SDTCisSameAs<0, 2>, 32 SDTCisVec<0>, SDTCisInt<0>, 33 SDTCVecEltisVT<3, i1>, 34 SDTCisSameNumEltsAs<0, 3>, 35 SDTCisVT<4, XLenVT>]>; 36 37def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<2, i1>, 40 SDTCisSameNumEltsAs<0, 2>, 41 SDTCisVT<3, XLenVT>]>; 42def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 43 SDTCisSameAs<0, 2>, 44 SDTCisVec<0>, SDTCisFP<0>, 45 SDTCVecEltisVT<3, i1>, 46 SDTCisSameNumEltsAs<0, 3>, 47 SDTCisVT<4, XLenVT>]>; 48 49def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 50 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 51 SDTCisVT<1, XLenVT>, 52 SDTCisVT<2, XLenVT>]>>; 53def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 54 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 55 SDTCisEltOfVec<1, 0>, 56 SDTCisVT<2, XLenVT>]>>; 57def riscv_vmv_s_xf_vl : SDNode<"RISCVISD::VMV_S_XF_VL", 58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 59 SDTCisVT<3, XLenVT>]>>; 60 61def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL, 62 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 63def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL, 64 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 65 66def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 67def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 68def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 69def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 70def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 71def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 72def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 73def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 74def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 76def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 77def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 78def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 79def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 80def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 81def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 83def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 84def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 86def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 87def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 88def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 89def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 90def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 91def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 92def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 93 94def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 95 SDTCisSameAs<0, 2>, 96 SDTCisSameAs<0, 3>, 97 SDTCisVec<0>, SDTCisFP<0>, 98 SDTCVecEltisVT<4, i1>, 99 SDTCisSameNumEltsAs<0, 4>, 100 SDTCisVT<5, XLenVT>]>; 101def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 102 103def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 104 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 105 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 106]>; 107def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 108 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 109 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 110]>; 111 112def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 113def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 114def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 115 116def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 117 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 118 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 119]>; 120def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 121 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 122 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 123]>; 124 125def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 126def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 127def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 128def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 129 130def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 131 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 132 SDTCisVec<1>, 133 SDTCisSameNumEltsAs<0, 1>, 134 SDTCisSameAs<1, 2>, 135 SDTCisVT<3, OtherVT>, 136 SDTCisSameAs<0, 4>, 137 SDTCisVT<5, XLenVT>]>>; 138 139def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 140 SDTypeProfile<1, 4, [SDTCisVec<0>, 141 SDTCisSameAs<0, 1>, 142 SDTCisVT<2, XLenVT>, 143 SDTCVecEltisVT<3, i1>, 144 SDTCisSameNumEltsAs<0, 3>, 145 SDTCisVT<4, XLenVT>]>>; 146def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 147 SDTypeProfile<1, 4, [SDTCisVec<0>, 148 SDTCisSameAs<0, 1>, 149 SDTCisInt<2>, 150 SDTCisSameNumEltsAs<0, 2>, 151 SDTCisSameSizeAs<0, 2>, 152 SDTCVecEltisVT<3, i1>, 153 SDTCisSameNumEltsAs<0, 3>, 154 SDTCisVT<4, XLenVT>]>>; 155def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 156 SDTypeProfile<1, 4, [SDTCisVec<0>, 157 SDTCisSameAs<0, 1>, 158 SDTCisInt<2>, 159 SDTCVecEltisVT<2, i16>, 160 SDTCisSameNumEltsAs<0, 2>, 161 SDTCVecEltisVT<3, i1>, 162 SDTCisSameNumEltsAs<0, 3>, 163 SDTCisVT<4, XLenVT>]>>; 164 165def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", 166 SDTypeProfile<1, 4, [SDTCisVec<0>, 167 SDTCisVec<1>, 168 SDTCisSameNumEltsAs<0, 1>, 169 SDTCVecEltisVT<1, i1>, 170 SDTCisSameAs<0, 2>, 171 SDTCisSameAs<2, 3>, 172 SDTCisVT<4, XLenVT>]>>; 173 174def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 175 SDTCisSameAs<0, 2>, 176 SDTCVecEltisVT<0, i1>, 177 SDTCisVT<3, XLenVT>]>; 178def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 179def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 180def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 181 182def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, 183 SDTCisVT<1, XLenVT>]>; 184def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; 185def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; 186 187def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 188 189def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 190 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 191 192def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 193 SDTCisSameNumEltsAs<0, 1>, 194 SDTCisSameNumEltsAs<1, 2>, 195 SDTCVecEltisVT<2, i1>, 196 SDTCisVT<3, XLenVT>]>; 197def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 198def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 199 200def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 201 SDTypeProfile<1, 3, [SDTCisVec<0>, 202 SDTCisVec<1>, 203 SDTCisSameNumEltsAs<0, 2>, 204 SDTCVecEltisVT<2, i1>, 205 SDTCisVT<3, XLenVT>]>>; 206 207def SDTRVVVecReduce : SDTypeProfile<1, 4, [ 208 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 209 SDTCisSameNumEltsAs<1, 3>, SDTCisVT<4, XLenVT> 210]>; 211 212foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 213 "FADD", "SEQ_FADD"] in 214 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 215 216// Ignore the vl operand. 217def SplatFPOp : PatFrag<(ops node:$op), 218 (riscv_vfmv_v_f_vl node:$op, srcvalue)>; 219 220def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 221def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 222def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 223def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 224 225def sew8uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<8>", []>; 226def sew16uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<16>", []>; 227def sew32uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<32>", []>; 228def sew64uimm5 : ComplexPattern<XLenVT, 1, "selectRVVUimm5<64>", []>; 229 230class VPatBinaryVL_VV<SDNode vop, 231 string instruction_name, 232 ValueType result_type, 233 ValueType op_type, 234 ValueType mask_type, 235 int sew, 236 LMULInfo vlmul, 237 VReg RetClass, 238 VReg op_reg_class> : 239 Pat<(result_type (vop 240 (op_type op_reg_class:$rs1), 241 (op_type op_reg_class:$rs2), 242 (mask_type true_mask), 243 (XLenVT (VLOp GPR:$vl)))), 244 (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX) 245 op_reg_class:$rs1, 246 op_reg_class:$rs2, 247 GPR:$vl, sew)>; 248 249class VPatBinaryVL_XI<SDNode vop, 250 string instruction_name, 251 string suffix, 252 ValueType result_type, 253 ValueType vop_type, 254 ValueType mask_type, 255 int sew, 256 LMULInfo vlmul, 257 VReg RetClass, 258 VReg vop_reg_class, 259 ComplexPattern SplatPatKind, 260 DAGOperand xop_kind> : 261 Pat<(result_type (vop 262 (vop_type vop_reg_class:$rs1), 263 (vop_type (SplatPatKind xop_kind:$rs2)), 264 (mask_type true_mask), 265 (XLenVT (VLOp GPR:$vl)))), 266 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX) 267 vop_reg_class:$rs1, 268 xop_kind:$rs2, 269 GPR:$vl, sew)>; 270 271multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 272 foreach vti = AllIntegerVectors in { 273 def : VPatBinaryVL_VV<vop, instruction_name, 274 vti.Vector, vti.Vector, vti.Mask, vti.SEW, 275 vti.LMul, vti.RegClass, vti.RegClass>; 276 def : VPatBinaryVL_XI<vop, instruction_name, "VX", 277 vti.Vector, vti.Vector, vti.Mask, vti.SEW, 278 vti.LMul, vti.RegClass, vti.RegClass, 279 SplatPat, GPR>; 280 } 281} 282 283multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 284 Operand ImmType = simm5> { 285 foreach vti = AllIntegerVectors in { 286 def : VPatBinaryVL_VV<vop, instruction_name, 287 vti.Vector, vti.Vector, vti.Mask, vti.SEW, 288 vti.LMul, vti.RegClass, vti.RegClass>; 289 def : VPatBinaryVL_XI<vop, instruction_name, "VX", 290 vti.Vector, vti.Vector, vti.Mask, vti.SEW, 291 vti.LMul, vti.RegClass, vti.RegClass, 292 SplatPat, GPR>; 293 def : VPatBinaryVL_XI<vop, instruction_name, "VI", 294 vti.Vector, vti.Vector, vti.Mask, vti.SEW, 295 vti.LMul, vti.RegClass, vti.RegClass, 296 !cast<ComplexPattern>(SplatPat#_#ImmType), 297 ImmType>; 298 } 299} 300 301class VPatBinaryVL_VF<SDNode vop, 302 string instruction_name, 303 ValueType result_type, 304 ValueType vop_type, 305 ValueType mask_type, 306 int sew, 307 LMULInfo vlmul, 308 VReg RetClass, 309 VReg vop_reg_class, 310 RegisterClass scalar_reg_class> : 311 Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 312 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 313 (mask_type true_mask), 314 (XLenVT (VLOp GPR:$vl)))), 315 (!cast<Instruction>(instruction_name#"_"#vlmul.MX) 316 vop_reg_class:$rs1, 317 scalar_reg_class:$rs2, 318 GPR:$vl, sew)>; 319 320multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 321 foreach vti = AllFloatVectors in { 322 def : VPatBinaryVL_VV<vop, instruction_name, 323 vti.Vector, vti.Vector, vti.Mask, vti.SEW, 324 vti.LMul, vti.RegClass, vti.RegClass>; 325 def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 326 vti.Vector, vti.Vector, vti.Mask, vti.SEW, 327 vti.LMul, vti.RegClass, vti.RegClass, 328 vti.ScalarRegClass>; 329 } 330} 331 332multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 333 foreach fvti = AllFloatVectors in 334 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 335 fvti.RegClass:$rs1, 336 (fvti.Mask true_mask), 337 (XLenVT (VLOp GPR:$vl)))), 338 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 339 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 340 GPR:$vl, fvti.SEW)>; 341} 342 343multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 344 CondCode cc> { 345 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 346 vti.RegClass:$rs2, cc, 347 (vti.Mask true_mask), 348 (XLenVT (VLOp GPR:$vl)))), 349 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 350 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 351 vti.SEW)>; 352} 353 354// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 355multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 356 CondCode cc, CondCode invcc> : 357 VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 358 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 359 vti.RegClass:$rs1, invcc, 360 (vti.Mask true_mask), 361 (XLenVT (VLOp GPR:$vl)))), 362 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 363 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 364 vti.SEW)>; 365} 366 367multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 368 CondCode cc, CondCode invcc> { 369 defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX); 370 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 371 (SplatPat GPR:$rs2), cc, 372 (vti.Mask true_mask), 373 (XLenVT (VLOp GPR:$vl)))), 374 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>; 375 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat GPR:$rs2), 376 (vti.Vector vti.RegClass:$rs1), invcc, 377 (vti.Mask true_mask), 378 (XLenVT (VLOp GPR:$vl)))), 379 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>; 380} 381 382multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 383 CondCode cc, CondCode invcc> { 384 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 385 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 386 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 387 (SplatPat_simm5 simm5:$rs2), cc, 388 (vti.Mask true_mask), 389 (XLenVT (VLOp GPR:$vl)))), 390 (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.SEW)>; 391 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 392 (vti.Vector vti.RegClass:$rs1), invcc, 393 (vti.Mask true_mask), 394 (XLenVT (VLOp GPR:$vl)))), 395 (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.SEW)>; 396} 397 398multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 399 string inst_name, 400 string swapped_op_inst_name> { 401 foreach fvti = AllFloatVectors in { 402 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 403 fvti.RegClass:$rs2, 404 cc, 405 (fvti.Mask true_mask), 406 (XLenVT (VLOp GPR:$vl)))), 407 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX) 408 fvti.RegClass:$rs1, fvti.RegClass:$rs2, GPR:$vl, fvti.SEW)>; 409 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 410 (SplatFPOp fvti.ScalarRegClass:$rs2), 411 cc, 412 (fvti.Mask true_mask), 413 (XLenVT (VLOp GPR:$vl)))), 414 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 415 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 416 GPR:$vl, fvti.SEW)>; 417 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 418 (fvti.Vector fvti.RegClass:$rs1), 419 cc, 420 (fvti.Mask true_mask), 421 (XLenVT (VLOp GPR:$vl)))), 422 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 423 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 424 GPR:$vl, fvti.SEW)>; 425 } 426} 427 428multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 429 list <VTypeInfoToFraction> fraction_list> { 430 foreach vtiTofti = fraction_list in { 431 defvar vti = vtiTofti.Vti; 432 defvar fti = vtiTofti.Fti; 433 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 434 true_mask, (XLenVT (VLOp GPR:$vl)))), 435 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX) 436 fti.RegClass:$rs2, GPR:$vl, vti.SEW)>; 437 } 438} 439 440multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 441 foreach fvti = AllFloatVectors in { 442 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 443 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 444 (fvti.Mask true_mask), 445 (XLenVT (VLOp GPR:$vl)))), 446 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 447 fvti.RegClass:$rs1, GPR:$vl, ivti.SEW)>; 448 } 449} 450 451multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 452 foreach fvti = AllFloatVectors in { 453 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 454 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 455 (ivti.Mask true_mask), 456 (XLenVT (VLOp GPR:$vl)))), 457 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 458 ivti.RegClass:$rs1, GPR:$vl, fvti.SEW)>; 459 } 460} 461 462multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 463 foreach fvtiToFWti = AllWidenableFloatVectors in { 464 defvar fvti = fvtiToFWti.Vti; 465 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 466 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 467 (fvti.Mask true_mask), 468 (XLenVT (VLOp GPR:$vl)))), 469 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 470 fvti.RegClass:$rs1, GPR:$vl, fvti.SEW)>; 471 } 472} 473 474multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 475 foreach vtiToWti = AllWidenableIntToFloatVectors in { 476 defvar ivti = vtiToWti.Vti; 477 defvar fwti = vtiToWti.Wti; 478 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 479 (ivti.Mask true_mask), 480 (XLenVT (VLOp GPR:$vl)))), 481 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 482 ivti.RegClass:$rs1, GPR:$vl, ivti.SEW)>; 483 } 484} 485 486multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 487 foreach vtiToWti = AllWidenableIntToFloatVectors in { 488 defvar vti = vtiToWti.Vti; 489 defvar fwti = vtiToWti.Wti; 490 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 491 (fwti.Mask true_mask), 492 (XLenVT (VLOp GPR:$vl)))), 493 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX) 494 fwti.RegClass:$rs1, GPR:$vl, vti.SEW)>; 495 } 496} 497 498multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 499 foreach fvtiToFWti = AllWidenableFloatVectors in { 500 defvar fvti = fvtiToFWti.Vti; 501 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 502 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 503 (iwti.Mask true_mask), 504 (XLenVT (VLOp GPR:$vl)))), 505 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 506 iwti.RegClass:$rs1, GPR:$vl, fvti.SEW)>; 507 } 508} 509 510multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 511 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 512 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 513 def: Pat<(vti_m1.Vector (vop (vti.Vector vti.RegClass:$rs1), VR:$rs2, 514 (vti.Mask true_mask), 515 (XLenVT (VLOp GPR:$vl)))), 516 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 517 (vti_m1.Vector (IMPLICIT_DEF)), 518 (vti.Vector vti.RegClass:$rs1), 519 (vti_m1.Vector VR:$rs2), 520 GPR:$vl, vti.SEW)>; 521 } 522} 523 524//===----------------------------------------------------------------------===// 525// Patterns. 526//===----------------------------------------------------------------------===// 527 528let Predicates = [HasStdExtV] in { 529 530// 7.4. Vector Unit-Stride Instructions 531foreach vti = AllVectors in { 532 defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX); 533 defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX); 534 // Load 535 def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))), 536 (load_instr BaseAddr:$rs1, GPR:$vl, vti.SEW)>; 537 // Store 538 def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1, 539 (XLenVT (VLOp GPR:$vl))), 540 (store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.SEW)>; 541} 542 543foreach mti = AllMasks in { 544 defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#mti.BX); 545 defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#mti.BX); 546 def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))), 547 (load_instr BaseAddr:$rs1, GPR:$vl, mti.SEW)>; 548 def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1, 549 (XLenVT (VLOp GPR:$vl))), 550 (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.SEW)>; 551} 552 553// 12.1. Vector Single-Width Integer Add and Subtract 554defm "" : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 555defm "" : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 556// Handle VRSUB specially since it's the only integer binary op with reversed 557// pattern operands 558foreach vti = AllIntegerVectors in { 559 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat GPR:$rs2)), 560 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 561 (XLenVT (VLOp GPR:$vl))), 562 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX) 563 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>; 564 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 565 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 566 (XLenVT (VLOp GPR:$vl))), 567 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX) 568 vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.SEW)>; 569} 570 571// 12.3. Vector Integer Extension 572defm "" : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 573 AllFractionableVF2IntVectors>; 574defm "" : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 575 AllFractionableVF2IntVectors>; 576defm "" : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 577 AllFractionableVF4IntVectors>; 578defm "" : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 579 AllFractionableVF4IntVectors>; 580defm "" : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 581 AllFractionableVF8IntVectors>; 582defm "" : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 583 AllFractionableVF8IntVectors>; 584 585// 12.5. Vector Bitwise Logical Instructions 586defm "" : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 587defm "" : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 588defm "" : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 589 590// 12.6. Vector Single-Width Bit Shift Instructions 591defm "" : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 592defm "" : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 593defm "" : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 594 595// 12.7. Vector Narrowing Integer Right Shift Instructions 596foreach vtiTofti = AllFractionableVF2IntVectors in { 597 defvar vti = vtiTofti.Vti; 598 defvar fti = vtiTofti.Fti; 599 def : Pat<(fti.Vector (riscv_trunc_vector_vl (vti.Vector vti.RegClass:$rs1), 600 (vti.Mask true_mask), 601 (XLenVT (VLOp GPR:$vl)))), 602 (!cast<Instruction>("PseudoVNSRL_WI_"#fti.LMul.MX) 603 vti.RegClass:$rs1, 0, GPR:$vl, fti.SEW)>; 604} 605 606// 12.8. Vector Integer Comparison Instructions 607foreach vti = AllIntegerVectors in { 608 defm "" : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 609 defm "" : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 610 611 defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 612 defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 613 defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 614 defm "" : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 615 616 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 617 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 618 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 619 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 620 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 621 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 622 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 623 defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 624 // There is no VMSGE(U)_VX instruction 625 626 // FIXME: Support immediate forms of these by choosing SGT and decrementing 627 // the immediate 628 defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 629 defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 630 defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 631 defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 632} // foreach vti = AllIntegerVectors 633 634// 12.9. Vector Integer Min/Max Instructions 635defm "" : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 636defm "" : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 637defm "" : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 638defm "" : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 639 640// 12.10. Vector Single-Width Integer Multiply Instructions 641defm "" : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 642defm "" : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 643defm "" : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 644 645// 12.11. Vector Integer Divide Instructions 646defm "" : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 647defm "" : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 648defm "" : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 649defm "" : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 650 651// 12.15. Vector Integer Merge Instructions 652foreach vti = AllIntegerVectors in { 653 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm), 654 vti.RegClass:$rs1, 655 vti.RegClass:$rs2, 656 (XLenVT (VLOp GPR:$vl)))), 657 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 658 vti.RegClass:$rs2, vti.RegClass:$rs1, VMV0:$vm, 659 GPR:$vl, vti.SEW)>; 660 661 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm), 662 (SplatPat XLenVT:$rs1), 663 vti.RegClass:$rs2, 664 (XLenVT (VLOp GPR:$vl)))), 665 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 666 vti.RegClass:$rs2, GPR:$rs1, VMV0:$vm, GPR:$vl, vti.SEW)>; 667 668 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm), 669 (SplatPat_simm5 simm5:$rs1), 670 vti.RegClass:$rs2, 671 (XLenVT (VLOp GPR:$vl)))), 672 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 673 vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, GPR:$vl, vti.SEW)>; 674} 675 676// 12.16. Vector Integer Move Instructions 677foreach vti = AllIntegerVectors in { 678 def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, (XLenVT (VLOp GPR:$vl)))), 679 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 680 $rs2, GPR:$vl, vti.SEW)>; 681 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 682 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (ImmPat XLenVT:$imm5), 683 (XLenVT (VLOp GPR:$vl)))), 684 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 685 XLenVT:$imm5, GPR:$vl, vti.SEW)>; 686} 687 688} // Predicates = [HasStdExtV] 689 690// 15.1. Vector Single-Width Integer Reduction Instructions 691let Predicates = [HasStdExtV] in { 692defm "" : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 693defm "" : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 694defm "" : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 695defm "" : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 696defm "" : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 697defm "" : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 698defm "" : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 699defm "" : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 700} // Predicates = [HasStdExtV] 701 702// 15.3. Vector Single-Width Floating-Point Reduction Instructions 703let Predicates = [HasStdExtV, HasStdExtF] in { 704defm "" : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 705defm "" : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDSUM", /*is_float*/1>; 706} // Predicates = [HasStdExtV, HasStdExtF] 707 708let Predicates = [HasStdExtV, HasStdExtF] in { 709 710// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 711defm "" : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 712defm "" : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 713defm "" : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 714 715// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 716defm "" : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 717defm "" : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 718defm "" : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 719 720// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 721foreach vti = AllFloatVectors in { 722 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 723 // works best with how TwoAddressInstructionPass tries commuting. 724 defvar suffix = vti.LMul.MX # "_COMMUTABLE"; 725 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 726 vti.RegClass:$rs2, (vti.Mask true_mask), 727 (XLenVT (VLOp GPR:$vl)))), 728 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 729 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 730 GPR:$vl, vti.SEW)>; 731 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 732 (riscv_fneg_vl vti.RegClass:$rs2, 733 (vti.Mask true_mask), 734 (XLenVT (VLOp GPR:$vl))), 735 (vti.Mask true_mask), 736 (XLenVT (VLOp GPR:$vl)))), 737 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 738 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 739 GPR:$vl, vti.SEW)>; 740 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 741 (vti.Mask true_mask), 742 (XLenVT (VLOp GPR:$vl))), 743 vti.RegClass:$rd, 744 (riscv_fneg_vl vti.RegClass:$rs2, 745 (vti.Mask true_mask), 746 (XLenVT (VLOp GPR:$vl))), 747 (vti.Mask true_mask), 748 (XLenVT (VLOp GPR:$vl)))), 749 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 750 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 751 GPR:$vl, vti.SEW)>; 752 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 753 (vti.Mask true_mask), 754 (XLenVT (VLOp GPR:$vl))), 755 vti.RegClass:$rd, vti.RegClass:$rs2, 756 (vti.Mask true_mask), 757 (XLenVT (VLOp GPR:$vl)))), 758 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 759 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 760 GPR:$vl, vti.SEW)>; 761 762 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 763 // commutable. 764 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 765 vti.RegClass:$rd, vti.RegClass:$rs2, 766 (vti.Mask true_mask), 767 (XLenVT (VLOp GPR:$vl)))), 768 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 769 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 770 GPR:$vl, vti.SEW)>; 771 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 772 vti.RegClass:$rd, 773 (riscv_fneg_vl vti.RegClass:$rs2, 774 (vti.Mask true_mask), 775 (XLenVT (VLOp GPR:$vl))), 776 (vti.Mask true_mask), 777 (XLenVT (VLOp GPR:$vl)))), 778 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 779 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 780 GPR:$vl, vti.SEW)>; 781 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 782 (riscv_fneg_vl vti.RegClass:$rd, 783 (vti.Mask true_mask), 784 (XLenVT (VLOp GPR:$vl))), 785 (riscv_fneg_vl vti.RegClass:$rs2, 786 (vti.Mask true_mask), 787 (XLenVT (VLOp GPR:$vl))), 788 (vti.Mask true_mask), 789 (XLenVT (VLOp GPR:$vl)))), 790 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 791 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 792 GPR:$vl, vti.SEW)>; 793 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 794 (riscv_fneg_vl vti.RegClass:$rd, 795 (vti.Mask true_mask), 796 (XLenVT (VLOp GPR:$vl))), 797 vti.RegClass:$rs2, 798 (vti.Mask true_mask), 799 (XLenVT (VLOp GPR:$vl)))), 800 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 801 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 802 GPR:$vl, vti.SEW)>; 803 804 // The splat might be negated. 805 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 806 (vti.Mask true_mask), 807 (XLenVT (VLOp GPR:$vl))), 808 vti.RegClass:$rd, 809 (riscv_fneg_vl vti.RegClass:$rs2, 810 (vti.Mask true_mask), 811 (XLenVT (VLOp GPR:$vl))), 812 (vti.Mask true_mask), 813 (XLenVT (VLOp GPR:$vl)))), 814 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 815 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 816 GPR:$vl, vti.SEW)>; 817 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 818 (vti.Mask true_mask), 819 (XLenVT (VLOp GPR:$vl))), 820 vti.RegClass:$rd, vti.RegClass:$rs2, 821 (vti.Mask true_mask), 822 (XLenVT (VLOp GPR:$vl)))), 823 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 824 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 825 GPR:$vl, vti.SEW)>; 826} 827 828// 14.13. Vector Floating-Point Compare Instructions 829defm "" : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 830defm "" : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 831 832defm "" : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 833defm "" : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 834 835defm "" : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 836defm "" : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 837 838defm "" : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 839defm "" : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 840 841foreach vti = AllFloatVectors in { 842 // 14.8. Vector Floating-Point Square-Root Instruction 843 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 844 (XLenVT (VLOp GPR:$vl))), 845 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 846 vti.RegClass:$rs2, GPR:$vl, vti.SEW)>; 847 848 // 14.12. Vector Floating-Point Sign-Injection Instructions 849 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 850 (XLenVT (VLOp GPR:$vl))), 851 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 852 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.SEW)>; 853 // Handle fneg with VFSGNJN using the same input for both operands. 854 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 855 (XLenVT (VLOp GPR:$vl))), 856 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 857 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.SEW)>; 858 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 859 (vti.Vector vti.RegClass:$rs2), 860 (vti.Mask true_mask), 861 (XLenVT (VLOp GPR:$vl))), 862 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 863 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.SEW)>; 864 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 865 (riscv_fneg_vl vti.RegClass:$rs2, 866 (vti.Mask true_mask), 867 (XLenVT (VLOp GPR:$vl))), 868 (vti.Mask true_mask), 869 (XLenVT (VLOp GPR:$vl))), 870 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 871 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.SEW)>; 872 873 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 874 (SplatFPOp vti.ScalarRegClass:$rs2), 875 (vti.Mask true_mask), 876 (XLenVT (VLOp GPR:$vl))), 877 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 878 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.SEW)>; 879} 880 881foreach fvti = AllFloatVectors in { 882 // Floating-point vselects: 883 // 12.15. Vector Integer Merge Instructions 884 // 14.15. Vector Floating-Point Merge Instruction 885 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm), 886 fvti.RegClass:$rs1, 887 fvti.RegClass:$rs2, 888 (XLenVT (VLOp GPR:$vl)))), 889 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 890 fvti.RegClass:$rs2, fvti.RegClass:$rs1, VMV0:$vm, 891 GPR:$vl, fvti.SEW)>; 892 893 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm), 894 (SplatFPOp fvti.ScalarRegClass:$rs1), 895 fvti.RegClass:$rs2, 896 (XLenVT (VLOp GPR:$vl)))), 897 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 898 fvti.RegClass:$rs2, 899 (fvti.Scalar fvti.ScalarRegClass:$rs1), 900 VMV0:$vm, GPR:$vl, fvti.SEW)>; 901 902 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm), 903 (SplatFPOp (fvti.Scalar fpimm0)), 904 fvti.RegClass:$rs2, 905 (XLenVT (VLOp GPR:$vl)))), 906 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 907 fvti.RegClass:$rs2, 0, VMV0:$vm, GPR:$vl, fvti.SEW)>; 908 909 // 14.16. Vector Floating-Point Move Instruction 910 // If we're splatting fpimm0, use vmv.v.x vd, x0. 911 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 912 (fvti.Scalar (fpimm0)), (XLenVT (VLOp GPR:$vl)))), 913 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 914 0, GPR:$vl, fvti.SEW)>; 915 916 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 917 (fvti.Scalar fvti.ScalarRegClass:$rs2), (XLenVT (VLOp GPR:$vl)))), 918 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 919 fvti.LMul.MX) 920 (fvti.Scalar fvti.ScalarRegClass:$rs2), 921 GPR:$vl, fvti.SEW)>; 922 923 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 924 defm "" : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 925 defm "" : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 926 defm "" : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 927 defm "" : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 928 929 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 930 defm "" : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 931 defm "" : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 932 defm "" : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 933 defm "" : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 934 foreach fvtiToFWti = AllWidenableFloatVectors in { 935 defvar fvti = fvtiToFWti.Vti; 936 defvar fwti = fvtiToFWti.Wti; 937 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 938 (fvti.Mask true_mask), 939 (XLenVT (VLOp GPR:$vl)))), 940 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX) 941 fvti.RegClass:$rs1, GPR:$vl, fvti.SEW)>; 942 } 943 944 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 945 defm "" : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 946 defm "" : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 947 defm "" : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 948 defm "" : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 949 foreach fvtiToFWti = AllWidenableFloatVectors in { 950 defvar fvti = fvtiToFWti.Vti; 951 defvar fwti = fvtiToFWti.Wti; 952 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 953 (fwti.Mask true_mask), 954 (XLenVT (VLOp GPR:$vl)))), 955 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX) 956 fwti.RegClass:$rs1, GPR:$vl, fvti.SEW)>; 957 958 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 959 (fwti.Mask true_mask), 960 (XLenVT (VLOp GPR:$vl)))), 961 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX) 962 fwti.RegClass:$rs1, GPR:$vl, fvti.SEW)>; 963 } 964} 965 966} // Predicates = [HasStdExtV, HasStdExtF] 967 968// 16.1 Vector Mask-Register Logical Instructions 969let Predicates = [HasStdExtV] in { 970 971foreach mti = AllMasks in { 972 def : Pat<(mti.Mask (riscv_vmset_vl (XLenVT (VLOp GPR:$vl)))), 973 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.SEW)>; 974 def : Pat<(mti.Mask (riscv_vmclr_vl (XLenVT (VLOp GPR:$vl)))), 975 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.SEW)>; 976 977 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))), 978 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 979 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 980 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))), 981 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 982 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 983 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))), 984 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 985 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 986 987 def : Pat<(mti.Mask (riscv_vmand_vl (riscv_vmnot_vl VR:$rs1, 988 (XLenVT (VLOp GPR:$vl))), 989 VR:$rs2, (XLenVT (VLOp GPR:$vl)))), 990 (!cast<Instruction>("PseudoVMANDNOT_MM_" # mti.LMul.MX) 991 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 992 def : Pat<(mti.Mask (riscv_vmor_vl (riscv_vmnot_vl VR:$rs1, 993 (XLenVT (VLOp GPR:$vl))), 994 VR:$rs2, (XLenVT (VLOp GPR:$vl)))), 995 (!cast<Instruction>("PseudoVMORNOT_MM_" # mti.LMul.MX) 996 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 997 // XOR is associative so we need 2 patterns for VMXNOR. 998 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 999 (XLenVT (VLOp GPR:$vl))), 1000 VR:$rs2, (XLenVT (VLOp GPR:$vl)))), 1001 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1002 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 1003 1004 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1005 (XLenVT (VLOp GPR:$vl))), 1006 (XLenVT (VLOp GPR:$vl)))), 1007 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1008 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 1009 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1010 (XLenVT (VLOp GPR:$vl))), 1011 (XLenVT (VLOp GPR:$vl)))), 1012 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1013 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 1014 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1015 (XLenVT (VLOp GPR:$vl))), 1016 (XLenVT (VLOp GPR:$vl)))), 1017 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1018 VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; 1019 1020 // Match the not idiom to the vnot.mm pseudo. 1021 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, (XLenVT (VLOp GPR:$vl)))), 1022 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1023 VR:$rs, VR:$rs, GPR:$vl, mti.SEW)>; 1024} 1025 1026} // Predicates = [HasStdExtV] 1027 1028let Predicates = [HasStdExtV] in { 1029// 17.1. Integer Scalar Move Instructions 1030// 17.4. Vector Register Gather Instruction 1031foreach vti = AllIntegerVectors in { 1032 def : Pat<(vti.Vector (riscv_vmv_s_xf_vl (vti.Vector vti.RegClass:$merge), 1033 (XLenVT vti.ScalarRegClass:$rs1), 1034 (XLenVT (VLOp GPR:$vl)))), 1035 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1036 vti.RegClass:$merge, 1037 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.SEW)>; 1038 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1039 (vti.Vector vti.RegClass:$rs1), 1040 (vti.Mask true_mask), 1041 (XLenVT (VLOp GPR:$vl)))), 1042 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1043 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.SEW)>; 1044 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1045 (vti.Mask true_mask), 1046 (XLenVT (VLOp GPR:$vl)))), 1047 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1048 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.SEW)>; 1049 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1050 (vti.Mask true_mask), 1051 (XLenVT (VLOp GPR:$vl)))), 1052 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1053 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>; 1054 1055 // emul = lmul * 16 / sew 1056 defvar vlmul = vti.LMul; 1057 defvar octuple_lmul = octuple_from_str<vlmul.MX>.ret; 1058 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), shift_amount<vti.SEW>.val); 1059 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1060 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1061 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1062 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1063 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1064 (ivti.Vector ivti.RegClass:$rs1), 1065 (vti.Mask true_mask), 1066 (XLenVT (VLOp GPR:$vl)))), 1067 (!cast<Instruction>(inst) 1068 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.SEW)>; 1069 } 1070} 1071 1072} // Predicates = [HasStdExtV] 1073 1074let Predicates = [HasStdExtV, HasStdExtF] in { 1075 1076// 17.2. Floating-Point Scalar Move Instructions 1077foreach vti = AllFloatVectors in { 1078 def : Pat<(vti.Vector (riscv_vmv_s_xf_vl (vti.Vector vti.RegClass:$merge), 1079 vti.ScalarRegClass:$rs1, 1080 (XLenVT (VLOp GPR:$vl)))), 1081 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1082 vti.RegClass:$merge, 1083 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.SEW)>; 1084 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1085 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1086 (ivti.Vector vti.RegClass:$rs1), 1087 (vti.Mask true_mask), 1088 (XLenVT (VLOp GPR:$vl)))), 1089 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1090 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.SEW)>; 1091 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1092 (vti.Mask true_mask), 1093 (XLenVT (VLOp GPR:$vl)))), 1094 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1095 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.SEW)>; 1096 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1097 (vti.Mask true_mask), 1098 (XLenVT (VLOp GPR:$vl)))), 1099 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1100 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>; 1101 1102 defvar vlmul = vti.LMul; 1103 defvar octuple_lmul = octuple_from_str<vlmul.MX>.ret; 1104 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), shift_amount<vti.SEW>.val); 1105 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1106 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1107 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1108 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1109 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1110 (ivti.Vector ivti.RegClass:$rs1), 1111 (vti.Mask true_mask), 1112 (XLenVT (VLOp GPR:$vl)))), 1113 (!cast<Instruction>(inst) 1114 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.SEW)>; 1115 } 1116} 1117 1118} // Predicates = [HasStdExtV, HasStdExtF] 1119 1120//===----------------------------------------------------------------------===// 1121// Miscellaneous RISCVISD SDNodes 1122//===----------------------------------------------------------------------===// 1123 1124def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1125 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1126 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1127 1128def SDTRVVSlide : SDTypeProfile<1, 5, [ 1129 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1130 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1131]>; 1132def SDTRVVSlide1 : SDTypeProfile<1, 4, [ 1133 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisVT<2, XLenVT>, 1134 SDTCVecEltisVT<3, i1>, SDTCisSameNumEltsAs<0, 3>, SDTCisVT<4, XLenVT> 1135]>; 1136 1137def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1138def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1139def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1140 1141let Predicates = [HasStdExtV] in { 1142 1143foreach vti = AllIntegerVectors in 1144 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1145 (XLenVT (VLOp GPR:$vl)))), 1146 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.SEW)>; 1147 1148foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1149 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1150 (vti.Vector vti.RegClass:$rs1), 1151 uimm5:$rs2, (vti.Mask true_mask), 1152 (XLenVT (VLOp GPR:$vl)))), 1153 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1154 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1155 GPR:$vl, vti.SEW)>; 1156 1157 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1158 (vti.Vector vti.RegClass:$rs1), 1159 GPR:$rs2, (vti.Mask true_mask), 1160 (XLenVT (VLOp GPR:$vl)))), 1161 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1162 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1163 GPR:$vl, vti.SEW)>; 1164 1165 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rs1), 1166 GPR:$rs2, (vti.Mask true_mask), 1167 (XLenVT (VLOp GPR:$vl)))), 1168 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1169 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>; 1170 1171 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1172 (vti.Vector vti.RegClass:$rs1), 1173 uimm5:$rs2, (vti.Mask true_mask), 1174 (XLenVT (VLOp GPR:$vl)))), 1175 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1176 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1177 GPR:$vl, vti.SEW)>; 1178 1179 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1180 (vti.Vector vti.RegClass:$rs1), 1181 GPR:$rs2, (vti.Mask true_mask), 1182 (XLenVT (VLOp GPR:$vl)))), 1183 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1184 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1185 GPR:$vl, vti.SEW)>; 1186} 1187 1188} // Predicates = [HasStdExtV] 1189