1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// version 1.0. 12/// 13/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 14/// 15/// Note: the patterns for RVV intrinsics are found in 16/// RISCVInstrInfoVPseudos.td. 17/// 18//===----------------------------------------------------------------------===// 19 20//===----------------------------------------------------------------------===// 21// Helpers to define the VL patterns. 22//===----------------------------------------------------------------------===// 23 24def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 25 SDTCisSameAs<0, 2>, 26 SDTCisVec<0>, SDTCisInt<0>, 27 SDTCVecEltisVT<3, i1>, 28 SDTCisSameNumEltsAs<0, 3>, 29 SDTCisVT<4, XLenVT>]>; 30 31def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 32 SDTCisVec<0>, SDTCisFP<0>, 33 SDTCVecEltisVT<2, i1>, 34 SDTCisSameNumEltsAs<0, 2>, 35 SDTCisVT<3, XLenVT>]>; 36def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<3, i1>, 40 SDTCisSameNumEltsAs<0, 3>, 41 SDTCisVT<4, XLenVT>]>; 42 43def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 44 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, 45 SDTCisSameAs<0, 1>, 46 SDTCisVT<2, XLenVT>, 47 SDTCisVT<3, XLenVT>]>>; 48def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 49 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 50 SDTCisSameAs<0, 1>, 51 SDTCisEltOfVec<2, 0>, 52 SDTCisVT<3, XLenVT>]>>; 53def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 54 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 55 SDTCisInt<0>, 56 SDTCisVT<2, XLenVT>, 57 SDTCisVT<3, XLenVT>]>>; 58def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 59 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 60 SDTCisFP<0>, 61 SDTCisEltOfVec<2, 0>, 62 SDTCisVT<3, XLenVT>]>>; 63 64def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 65def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 66def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 67def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 68def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 69def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 70def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 71def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 72def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 73def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 74def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 76def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 77def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 78def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 79def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 80def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 81def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 83 84def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 88 89def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 90def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 91def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 92def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 93def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 94def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 95def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 96def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 97def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 98def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 99 100def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 101 SDTCisSameAs<0, 2>, 102 SDTCisSameAs<0, 3>, 103 SDTCisVec<0>, SDTCisFP<0>, 104 SDTCVecEltisVT<4, i1>, 105 SDTCisSameNumEltsAs<0, 4>, 106 SDTCisVT<5, XLenVT>]>; 107def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 108 109def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 110 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 111 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 112]>; 113def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 114 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 115 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 116]>; 117 118def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 119def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 120def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 121 122def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 127 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 128 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 129]>; 130 131def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 132def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 133def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 134def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 135 136def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 137 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 138 SDTCisVec<1>, 139 SDTCisSameNumEltsAs<0, 1>, 140 SDTCisSameAs<1, 2>, 141 SDTCisVT<3, OtherVT>, 142 SDTCisSameAs<0, 4>, 143 SDTCisVT<5, XLenVT>]>>; 144 145def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 146 SDTypeProfile<1, 4, [SDTCisVec<0>, 147 SDTCisSameAs<0, 1>, 148 SDTCisVT<2, XLenVT>, 149 SDTCVecEltisVT<3, i1>, 150 SDTCisSameNumEltsAs<0, 3>, 151 SDTCisVT<4, XLenVT>]>>; 152def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 153 SDTypeProfile<1, 4, [SDTCisVec<0>, 154 SDTCisSameAs<0, 1>, 155 SDTCisInt<2>, 156 SDTCisSameNumEltsAs<0, 2>, 157 SDTCisSameSizeAs<0, 2>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCVecEltisVT<2, i16>, 166 SDTCisSameNumEltsAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170 171def SDT_RISCVSelect_VL : SDTypeProfile<1, 4, [ 172 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>, 173 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, XLenVT> 174]>; 175 176def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", SDT_RISCVSelect_VL>; 177def riscv_vp_merge_vl : SDNode<"RISCVISD::VP_MERGE_VL", SDT_RISCVSelect_VL>; 178 179def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, 180 SDTCisVT<1, XLenVT>]>; 181def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; 182def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; 183 184def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 185 SDTCisSameAs<0, 2>, 186 SDTCVecEltisVT<0, i1>, 187 SDTCisVT<3, XLenVT>]>; 188def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 189def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 190def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 191 192def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 193 194def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 195 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 196 197def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 198 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 199 SDTCisVec<1>, SDTCisInt<1>, 200 SDTCVecEltisVT<2, i1>, 201 SDTCisSameNumEltsAs<1, 2>, 202 SDTCisVT<3, XLenVT>]>>; 203 204def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 205 SDTCisSameNumEltsAs<0, 1>, 206 SDTCisSameNumEltsAs<1, 2>, 207 SDTCVecEltisVT<2, i1>, 208 SDTCisVT<3, XLenVT>]>; 209def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 210def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 211 212def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 213 SDTypeProfile<1, 3, [SDTCisVec<0>, 214 SDTCisSameNumEltsAs<0, 1>, 215 SDTCisSameNumEltsAs<0, 2>, 216 SDTCVecEltisVT<2, i1>, 217 SDTCisVT<3, XLenVT>]>>; 218 219def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 220 SDTCisSameNumEltsAs<0, 1>, 221 SDTCisSameAs<1, 2>, 222 SDTCisSameNumEltsAs<1, 3>, 223 SDTCVecEltisVT<3, i1>, 224 SDTCisVT<4, XLenVT>]>; 225def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 226def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 227def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>; 228def riscv_vwadd_vl : SDNode<"RISCVISD::VWADD_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 229def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 230def riscv_vwsub_vl : SDNode<"RISCVISD::VWSUB_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 231def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 232 233def SDT_RISCVVWBinOpW_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 234 SDTCisSameAs<0, 1>, 235 SDTCisSameNumEltsAs<1, 2>, 236 SDTCisOpSmallerThanOp<2, 1>, 237 SDTCisSameNumEltsAs<1, 3>, 238 SDTCVecEltisVT<3, i1>, 239 SDTCisVT<4, XLenVT>]>; 240def riscv_vwadd_w_vl : SDNode<"RISCVISD::VWADD_W_VL", SDT_RISCVVWBinOpW_VL>; 241def riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWBinOpW_VL>; 242def riscv_vwsub_w_vl : SDNode<"RISCVISD::VWSUB_W_VL", SDT_RISCVVWBinOpW_VL>; 243def riscv_vwsubu_w_vl : SDNode<"RISCVISD::VWSUBU_W_VL", SDT_RISCVVWBinOpW_VL>; 244 245def SDTRVVVecReduce : SDTypeProfile<1, 5, [ 246 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 247 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT> 248]>; 249 250def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 251 (riscv_mul_vl node:$A, node:$B, node:$C, 252 node:$D), [{ 253 return N->hasOneUse(); 254}]>; 255 256def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 257 (riscv_vwmul_vl node:$A, node:$B, node:$C, 258 node:$D), [{ 259 return N->hasOneUse(); 260}]>; 261 262def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 263 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 264 node:$D), [{ 265 return N->hasOneUse(); 266}]>; 267 268def riscv_vwmulsu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 269 (riscv_vwmulsu_vl node:$A, node:$B, node:$C, 270 node:$D), [{ 271 return N->hasOneUse(); 272}]>; 273 274def riscv_sext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 275 (riscv_sext_vl node:$A, node:$B, node:$C), [{ 276 return N->hasOneUse(); 277}]>; 278 279def riscv_zext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 280 (riscv_zext_vl node:$A, node:$B, node:$C), [{ 281 return N->hasOneUse(); 282}]>; 283 284def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 285 (riscv_fpextend_vl node:$A, node:$B, node:$C), [{ 286 return N->hasOneUse(); 287}]>; 288 289foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 290 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 291 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 292 293// Give explicit Complexity to prefer simm5/uimm5. 294def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; 295def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 2>; 296def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>; 297def SplatPat_simm5_plus1 298 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>; 299def SplatPat_simm5_plus1_nonzero 300 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>; 301 302// Ignore the vl operand. 303def SplatFPOp : PatFrag<(ops node:$op), 304 (riscv_vfmv_v_f_vl undef, node:$op, srcvalue)>; 305 306def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 307def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 308def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 309def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 310 311multiclass VPatBinaryVL_V<SDNode vop, 312 string instruction_name, 313 string suffix, 314 ValueType result_type, 315 ValueType op1_type, 316 ValueType op2_type, 317 ValueType mask_type, 318 int sew, 319 LMULInfo vlmul, 320 VReg op1_reg_class, 321 VReg op2_reg_class> { 322 def : Pat<(result_type (vop 323 (op1_type op1_reg_class:$rs1), 324 (op2_type op2_reg_class:$rs2), 325 (mask_type V0), 326 VLOpFrag)), 327 (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_MASK") 328 (result_type (IMPLICIT_DEF)), 329 op1_reg_class:$rs1, 330 op2_reg_class:$rs2, 331 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 332} 333 334multiclass VPatBinaryVL_XI<SDNode vop, 335 string instruction_name, 336 string suffix, 337 ValueType result_type, 338 ValueType vop1_type, 339 ValueType vop2_type, 340 ValueType mask_type, 341 int sew, 342 LMULInfo vlmul, 343 VReg vop_reg_class, 344 ComplexPattern SplatPatKind, 345 DAGOperand xop_kind> { 346 def : Pat<(result_type (vop 347 (vop1_type vop_reg_class:$rs1), 348 (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))), 349 (mask_type V0), 350 VLOpFrag)), 351 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 352 (result_type (IMPLICIT_DEF)), 353 vop_reg_class:$rs1, 354 xop_kind:$rs2, 355 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 356} 357 358multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 359 foreach vti = AllIntegerVectors in { 360 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 361 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 362 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 363 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 364 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 365 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 366 } 367} 368 369multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 370 Operand ImmType = simm5> 371 : VPatBinaryVL_VV_VX<vop, instruction_name> { 372 foreach vti = AllIntegerVectors in { 373 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 374 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 375 vti.Log2SEW, vti.LMul, vti.RegClass, 376 !cast<ComplexPattern>(SplatPat#_#ImmType), 377 ImmType>; 378 } 379} 380 381multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 382 foreach VtiToWti = AllWidenableIntVectors in { 383 defvar vti = VtiToWti.Vti; 384 defvar wti = VtiToWti.Wti; 385 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 386 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 387 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 388 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 389 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 390 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 391 } 392} 393multiclass VPatBinaryWVL_VV_VX_WV_WX<SDNode vop, SDNode vop_w, 394 string instruction_name> 395 : VPatBinaryWVL_VV_VX<vop, instruction_name> { 396 foreach VtiToWti = AllWidenableIntVectors in { 397 defvar vti = VtiToWti.Vti; 398 defvar wti = VtiToWti.Wti; 399 defm : VPatBinaryVL_V<vop_w, instruction_name, "WV", 400 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 401 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass>; 402 defm : VPatBinaryVL_XI<vop_w, instruction_name, "WX", 403 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 404 vti.Log2SEW, vti.LMul, wti.RegClass, SplatPat, GPR>; 405 } 406} 407 408multiclass VPatBinaryVL_VF<SDNode vop, 409 string instruction_name, 410 ValueType result_type, 411 ValueType vop_type, 412 ValueType mask_type, 413 int sew, 414 LMULInfo vlmul, 415 VReg vop_reg_class, 416 RegisterClass scalar_reg_class> { 417 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 418 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 419 (mask_type V0), 420 VLOpFrag)), 421 (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_MASK") 422 (result_type (IMPLICIT_DEF)), 423 vop_reg_class:$rs1, 424 scalar_reg_class:$rs2, 425 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 426} 427 428multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 429 foreach vti = AllFloatVectors in { 430 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 431 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 432 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 433 defm : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 434 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 435 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 436 } 437} 438 439multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 440 foreach fvti = AllFloatVectors in { 441 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 442 fvti.RegClass:$rs1, 443 (fvti.Mask V0), 444 VLOpFrag)), 445 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 446 (fvti.Vector (IMPLICIT_DEF)), 447 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 448 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 449 } 450} 451 452multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 453 CondCode cc> { 454 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 455 vti.RegClass:$rs2, cc, 456 (vti.Mask V0), 457 VLOpFrag)), 458 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 459 (vti.Mask (IMPLICIT_DEF)), 460 vti.RegClass:$rs1, 461 vti.RegClass:$rs2, 462 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 463} 464 465// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 466multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 467 CondCode cc, CondCode invcc> 468 : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 469 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 470 vti.RegClass:$rs1, invcc, 471 (vti.Mask V0), 472 VLOpFrag)), 473 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 474 (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 475 vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 476} 477 478multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 479 CondCode cc, CondCode invcc> { 480 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); 481 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 482 (SplatPat (XLenVT GPR:$rs2)), cc, 483 (vti.Mask V0), 484 VLOpFrag)), 485 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 486 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 487 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 488 (vti.Vector vti.RegClass:$rs1), invcc, 489 (vti.Mask V0), 490 VLOpFrag)), 491 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 492 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 493} 494 495multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 496 CondCode cc, CondCode invcc> { 497 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 498 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 499 (SplatPat_simm5 simm5:$rs2), cc, 500 (vti.Mask V0), 501 VLOpFrag)), 502 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 503 XLenVT:$rs2, (vti.Mask V0), GPR:$vl, 504 vti.Log2SEW)>; 505 506 // FIXME: Can do some canonicalization to remove these patterns. 507 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 508 (vti.Vector vti.RegClass:$rs1), invcc, 509 (vti.Mask V0), 510 VLOpFrag)), 511 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 512 simm5:$rs2, (vti.Mask V0), GPR:$vl, 513 vti.Log2SEW)>; 514} 515 516multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti, 517 string instruction_name, 518 CondCode cc, CondCode invcc, 519 ComplexPattern splatpat_kind> { 520 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 521 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 522 (splatpat_kind simm5:$rs2), cc, 523 (vti.Mask V0), 524 VLOpFrag)), 525 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 526 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 527 vti.Log2SEW)>; 528 529 // FIXME: Can do some canonicalization to remove these patterns. 530 def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), 531 (vti.Vector vti.RegClass:$rs1), invcc, 532 (vti.Mask V0), 533 VLOpFrag)), 534 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 535 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 536 vti.Log2SEW)>; 537} 538 539multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 540 string inst_name, 541 string swapped_op_inst_name> { 542 foreach fvti = AllFloatVectors in { 543 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 544 fvti.RegClass:$rs2, 545 cc, 546 (fvti.Mask V0), 547 VLOpFrag)), 548 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX#"_MASK") 549 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 550 fvti.RegClass:$rs2, (fvti.Mask V0), 551 GPR:$vl, fvti.Log2SEW)>; 552 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 553 (SplatFPOp fvti.ScalarRegClass:$rs2), 554 cc, 555 (fvti.Mask V0), 556 VLOpFrag)), 557 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 558 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 559 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 560 GPR:$vl, fvti.Log2SEW)>; 561 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 562 (fvti.Vector fvti.RegClass:$rs1), 563 cc, 564 (fvti.Mask V0), 565 VLOpFrag)), 566 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 567 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 568 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 569 GPR:$vl, fvti.Log2SEW)>; 570 } 571} 572 573multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 574 list <VTypeInfoToFraction> fraction_list> { 575 foreach vtiTofti = fraction_list in { 576 defvar vti = vtiTofti.Vti; 577 defvar fti = vtiTofti.Fti; 578 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 579 (fti.Mask V0), VLOpFrag)), 580 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK") 581 (vti.Vector (IMPLICIT_DEF)), 582 fti.RegClass:$rs2, 583 (fti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 584 } 585} 586 587multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 588 foreach fvti = AllFloatVectors in { 589 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 590 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 591 (fvti.Mask V0), 592 VLOpFrag)), 593 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 594 (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 595 (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 596 } 597} 598 599multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 600 foreach fvti = AllFloatVectors in { 601 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 602 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 603 (ivti.Mask V0), 604 VLOpFrag)), 605 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 606 (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 607 (ivti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 608 } 609} 610 611multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 612 foreach fvtiToFWti = AllWidenableFloatVectors in { 613 defvar fvti = fvtiToFWti.Vti; 614 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 615 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 616 (fvti.Mask V0), 617 VLOpFrag)), 618 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 619 (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 620 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 621 } 622} 623 624multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 625 foreach vtiToWti = AllWidenableIntToFloatVectors in { 626 defvar ivti = vtiToWti.Vti; 627 defvar fwti = vtiToWti.Wti; 628 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 629 (ivti.Mask V0), 630 VLOpFrag)), 631 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 632 (fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 633 (ivti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 634 } 635} 636 637multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 638 foreach vtiToWti = AllWidenableIntToFloatVectors in { 639 defvar vti = vtiToWti.Vti; 640 defvar fwti = vtiToWti.Wti; 641 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 642 (fwti.Mask V0), 643 VLOpFrag)), 644 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK") 645 (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 646 (fwti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 647 } 648} 649 650multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 651 foreach fvtiToFWti = AllWidenableFloatVectors in { 652 defvar fvti = fvtiToFWti.Vti; 653 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 654 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 655 (iwti.Mask V0), 656 VLOpFrag)), 657 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 658 (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1, 659 (iwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 660 } 661} 662 663multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 664 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 665 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 666 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 667 (vti.Mask true_mask), 668 VLOpFrag)), 669 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 670 (vti_m1.Vector VR:$merge), 671 (vti.Vector vti.RegClass:$rs1), 672 (vti_m1.Vector VR:$rs2), 673 GPR:$vl, vti.Log2SEW)>; 674 675 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 676 (vti.Mask V0), VLOpFrag)), 677 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 678 (vti_m1.Vector VR:$merge), 679 (vti.Vector vti.RegClass:$rs1), 680 (vti_m1.Vector VR:$rs2), 681 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 682 } 683} 684 685multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> { 686 foreach vtiToWti = AllWidenableIntVectors in { 687 defvar vti = vtiToWti.Vti; 688 defvar wti = vtiToWti.Wti; 689 def : Pat< 690 (vti.Vector 691 (riscv_trunc_vector_vl 692 (op (wti.Vector wti.RegClass:$rs2), 693 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))), 694 (riscv_vmset_vl VLOpFrag), 695 VLOpFrag)), 696 (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX) 697 wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; 698 def : Pat< 699 (vti.Vector 700 (riscv_trunc_vector_vl 701 (op (wti.Vector wti.RegClass:$rs2), 702 (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))), 703 (riscv_vmset_vl VLOpFrag), 704 VLOpFrag)), 705 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 706 wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; 707 } 708} 709 710multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> { 711 defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>; 712 defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>; 713 foreach vtiToWti = AllWidenableIntVectors in { 714 defvar vti = vtiToWti.Vti; 715 defvar wti = vtiToWti.Wti; 716 def : Pat< 717 (vti.Vector 718 (riscv_trunc_vector_vl 719 (op (wti.Vector wti.RegClass:$rs2), 720 (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), 721 (riscv_vmset_vl VLOpFrag), 722 VLOpFrag)), 723 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 724 wti.RegClass:$rs2, uimm5:$rs1, vti.AVL, vti.Log2SEW)>; 725 } 726} 727 728multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 729 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 730 defvar vti = vtiToWti.Vti; 731 defvar wti = vtiToWti.Wti; 732 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 733 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 734 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 735 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 736 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 737 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 738 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 739 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 740 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 741 VR:$rs2, (vti.Mask V0), VLOpFrag)), 742 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 743 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 744 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 745 } 746} 747 748multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 749 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 750 defvar vti = vtiToWti.Vti; 751 defvar wti = vtiToWti.Wti; 752 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 753 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 754 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 755 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 756 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 757 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 758 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 759 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 760 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 761 VR:$rs2, (vti.Mask V0), VLOpFrag)), 762 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 763 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 764 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 765 } 766} 767 768multiclass VPatWidenBinaryFPVL_VV_VF<SDNode op, PatFrags extop, string instruction_name> { 769 foreach fvtiToFWti = AllWidenableFloatVectors in { 770 defvar fvti = fvtiToFWti.Vti; 771 defvar fwti = fvtiToFWti.Wti; 772 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 773 (fvti.Mask true_mask), VLOpFrag)), 774 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 775 (fvti.Mask true_mask), VLOpFrag)), 776 (fwti.Mask true_mask), VLOpFrag)), 777 (!cast<Instruction>(instruction_name#"_VV_"#fvti.LMul.MX) 778 fvti.RegClass:$rs2, fvti.RegClass:$rs1, 779 GPR:$vl, fvti.Log2SEW)>; 780 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 781 (fvti.Mask true_mask), VLOpFrag)), 782 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 783 (fvti.Mask true_mask), VLOpFrag)), 784 (fwti.Mask true_mask), VLOpFrag)), 785 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 786 fvti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 787 GPR:$vl, fvti.Log2SEW)>; 788 } 789} 790 791multiclass VPatWidenBinaryFPVL_WV_WF<SDNode op, PatFrags extop, string instruction_name> { 792 foreach fvtiToFWti = AllWidenableFloatVectors in { 793 defvar fvti = fvtiToFWti.Vti; 794 defvar fwti = fvtiToFWti.Wti; 795 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 796 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 797 (fvti.Mask true_mask), VLOpFrag)), 798 (fwti.Mask true_mask), VLOpFrag)), 799 (!cast<Instruction>(instruction_name#"_WV_"#fvti.LMul.MX) 800 fwti.RegClass:$rs2, fvti.RegClass:$rs1, 801 GPR:$vl, fvti.Log2SEW)>; 802 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 803 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 804 (fvti.Mask true_mask), VLOpFrag)), 805 (fwti.Mask true_mask), VLOpFrag)), 806 (!cast<Instruction>(instruction_name#"_W"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 807 fwti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 808 GPR:$vl, fvti.Log2SEW)>; 809 } 810} 811 812multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> { 813 defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>; 814 defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>; 815} 816 817multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> { 818 foreach vtiToWti = AllWidenableIntVectors in { 819 defvar vti = vtiToWti.Vti; 820 defvar wti = vtiToWti.Wti; 821 def : Pat< 822 (vti.Vector 823 (riscv_trunc_vector_vl 824 (op (wti.Vector wti.RegClass:$rs2), 825 (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1)), 826 (vti.Mask true_mask), VLOpFrag)), 827 (wti.Mask true_mask), VLOpFrag), 828 (vti.Mask true_mask), VLOpFrag)), 829 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 830 wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; 831 } 832} 833 834multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> { 835 foreach vti = AllIntegerVectors in { 836 defvar suffix = vti.LMul.MX; 837 // NOTE: We choose VMADD because it has the most commuting freedom. So it 838 // works best with how TwoAddressInstructionPass tries commuting. 839 def : Pat<(vti.Vector 840 (op vti.RegClass:$rs2, 841 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 842 vti.RegClass:$rd, 843 (vti.Mask true_mask), VLOpFrag), 844 (vti.Mask true_mask), VLOpFrag)), 845 (!cast<Instruction>(instruction_name#"_VV_"# suffix) 846 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 847 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 848 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 849 // commutable. 850 def : Pat<(vti.Vector 851 (op vti.RegClass:$rs2, 852 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 853 vti.RegClass:$rd, 854 (vti.Mask true_mask), VLOpFrag), 855 (vti.Mask true_mask), VLOpFrag)), 856 (!cast<Instruction>(instruction_name#"_VX_" # suffix) 857 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 858 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 859 } 860} 861 862multiclass VPatWidenMultiplyAddVL_VV_VX<PatFrag op1, string instruction_name> { 863 foreach vtiTowti = AllWidenableIntVectors in { 864 defvar vti = vtiTowti.Vti; 865 defvar wti = vtiTowti.Wti; 866 def : Pat<(wti.Vector 867 (riscv_add_vl wti.RegClass:$rd, 868 (op1 vti.RegClass:$rs1, 869 (vti.Vector vti.RegClass:$rs2), 870 (vti.Mask true_mask), VLOpFrag), 871 (vti.Mask true_mask), VLOpFrag)), 872 (!cast<Instruction>(instruction_name#"_VV_" # vti.LMul.MX) 873 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 874 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 875 def : Pat<(wti.Vector 876 (riscv_add_vl wti.RegClass:$rd, 877 (op1 (SplatPat XLenVT:$rs1), 878 (vti.Vector vti.RegClass:$rs2), 879 (vti.Mask true_mask), VLOpFrag), 880 (vti.Mask true_mask), VLOpFrag)), 881 (!cast<Instruction>(instruction_name#"_VX_" # vti.LMul.MX) 882 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 883 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 884 } 885} 886 887multiclass VPatNarrowShiftSplat_WX_WI<SDNode op, string instruction_name> { 888 foreach vtiTowti = AllWidenableIntVectors in { 889 defvar vti = vtiTowti.Vti; 890 defvar wti = vtiTowti.Wti; 891 def : Pat<(vti.Vector (riscv_trunc_vector_vl 892 (wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 893 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 894 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 895 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 896 def : Pat<(vti.Vector (riscv_trunc_vector_vl 897 (wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 898 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 899 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 900 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 901 } 902} 903 904//===----------------------------------------------------------------------===// 905// Patterns. 906//===----------------------------------------------------------------------===// 907 908let Predicates = [HasVInstructions] in { 909 910// 12.1. Vector Single-Width Integer Add and Subtract 911defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 912defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 913// Handle VRSUB specially since it's the only integer binary op with reversed 914// pattern operands 915foreach vti = AllIntegerVectors in { 916 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 917 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 918 VLOpFrag), 919 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 920 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 921 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 922 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 923 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 924 VLOpFrag), 925 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 926 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 927 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 928} 929 930// 12.2. Vector Widening Integer Add/Subtract 931defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwadd_vl, riscv_vwadd_w_vl, "PseudoVWADD">; 932defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWADDU">; 933defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">; 934defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">; 935 936// 12.3. Vector Integer Extension 937defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 938 AllFractionableVF2IntVectors>; 939defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 940 AllFractionableVF2IntVectors>; 941defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 942 AllFractionableVF4IntVectors>; 943defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 944 AllFractionableVF4IntVectors>; 945defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 946 AllFractionableVF8IntVectors>; 947defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 948 AllFractionableVF8IntVectors>; 949 950// 12.5. Vector Bitwise Logical Instructions 951defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 952defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 953defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 954 955// 12.6. Vector Single-Width Bit Shift Instructions 956defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 957defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 958defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 959 960foreach vti = AllIntegerVectors in { 961 // Emit shift by 1 as an add since it might be faster. 962 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 963 (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)), 964 (vti.Mask true_mask), 965 VLOpFrag), 966 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 967 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 968} 969 970// 12.7. Vector Narrowing Integer Right Shift Instructions 971defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">; 972defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">; 973 974defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">; 975defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">; 976defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">; 977defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">; 978defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">; 979defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">; 980 981foreach vtiTowti = AllWidenableIntVectors in { 982 defvar vti = vtiTowti.Vti; 983 defvar wti = vtiTowti.Wti; 984 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 985 (vti.Mask true_mask), 986 VLOpFrag)), 987 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 988 wti.RegClass:$rs1, X0, GPR:$vl, vti.Log2SEW)>; 989 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 990 (vti.Mask V0), 991 VLOpFrag)), 992 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX#"_MASK") 993 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, X0, 994 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 995} 996 997// 12.8. Vector Integer Comparison Instructions 998foreach vti = AllIntegerVectors in { 999 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 1000 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 1001 1002 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 1003 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 1004 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1005 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1006 1007 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 1008 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 1009 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 1010 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 1011 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1012 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1013 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 1014 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 1015 // There is no VMSGE(U)_VX instruction 1016 1017 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 1018 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 1019 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1020 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1021 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 1022 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 1023 1024 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT, 1025 SplatPat_simm5_plus1_nonzero>; 1026 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT, 1027 SplatPat_simm5_plus1_nonzero>; 1028 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE, 1029 SplatPat_simm5_plus1>; 1030 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE, 1031 SplatPat_simm5_plus1_nonzero>; 1032} // foreach vti = AllIntegerVectors 1033 1034// 12.9. Vector Integer Min/Max Instructions 1035defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 1036defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 1037defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 1038defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 1039 1040// 12.10. Vector Single-Width Integer Multiply Instructions 1041defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 1042defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 1043defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 1044 1045// 12.11. Vector Integer Divide Instructions 1046defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 1047defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 1048defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 1049defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 1050 1051// 12.12. Vector Widening Integer Multiply Instructions 1052defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 1053defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 1054defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; 1055 1056// 12.13 Vector Single-Width Integer Multiply-Add Instructions 1057defm : VPatMultiplyAddVL_VV_VX<riscv_add_vl, "PseudoVMADD">; 1058defm : VPatMultiplyAddVL_VV_VX<riscv_sub_vl, "PseudoVNMSUB">; 1059 1060// 12.14. Vector Widening Integer Multiply-Add Instructions 1061defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmul_vl_oneuse, "PseudoVWMACC">; 1062defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulu_vl_oneuse, "PseudoVWMACCU">; 1063defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulsu_vl_oneuse, "PseudoVWMACCSU">; 1064foreach vtiTowti = AllWidenableIntVectors in { 1065 defvar vti = vtiTowti.Vti; 1066 defvar wti = vtiTowti.Wti; 1067 def : Pat<(wti.Vector 1068 (riscv_add_vl wti.RegClass:$rd, 1069 (riscv_vwmulsu_vl_oneuse (vti.Vector vti.RegClass:$rs1), 1070 (SplatPat XLenVT:$rs2), 1071 (vti.Mask true_mask), VLOpFrag), 1072 (vti.Mask true_mask), VLOpFrag)), 1073 (!cast<Instruction>("PseudoVWMACCUS_VX_" # vti.LMul.MX) 1074 wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1, 1075 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1076} 1077 1078// 12.15. Vector Integer Merge Instructions 1079foreach vti = AllIntegerVectors in { 1080 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1081 vti.RegClass:$rs1, 1082 vti.RegClass:$rs2, 1083 VLOpFrag)), 1084 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 1085 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 1086 GPR:$vl, vti.Log2SEW)>; 1087 1088 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1089 (SplatPat XLenVT:$rs1), 1090 vti.RegClass:$rs2, 1091 VLOpFrag)), 1092 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 1093 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1094 1095 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1096 (SplatPat_simm5 simm5:$rs1), 1097 vti.RegClass:$rs2, 1098 VLOpFrag)), 1099 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 1100 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1101 1102 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1103 vti.RegClass:$rs1, 1104 vti.RegClass:$rs2, 1105 VLOpFrag)), 1106 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX#"_TU") 1107 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1, 1108 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1109 1110 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1111 (SplatPat XLenVT:$rs1), 1112 vti.RegClass:$rs2, 1113 VLOpFrag)), 1114 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX#"_TU") 1115 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1, 1116 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1117 1118 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1119 (SplatPat_simm5 simm5:$rs1), 1120 vti.RegClass:$rs2, 1121 VLOpFrag)), 1122 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU") 1123 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, 1124 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1125} 1126 1127// 12.16. Vector Integer Move Instructions 1128foreach vti = AllIntegerVectors in { 1129 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)), 1130 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 1131 $rs2, GPR:$vl, vti.Log2SEW)>; 1132 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, GPR:$rs2, VLOpFrag)), 1133 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX#"_TU") 1134 $passthru, $rs2, GPR:$vl, vti.Log2SEW)>; 1135 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 1136 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat XLenVT:$imm5), 1137 VLOpFrag)), 1138 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 1139 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1140 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, (ImmPat XLenVT:$imm5), 1141 VLOpFrag)), 1142 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX#"_TU") 1143 $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1144} 1145 1146// 12.1. Vector Single-Width Saturating Add and Subtract 1147defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 1148defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 1149defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 1150defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 1151 1152} // Predicates = [HasVInstructions] 1153 1154// 15.1. Vector Single-Width Integer Reduction Instructions 1155let Predicates = [HasVInstructions] in { 1156defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 1157defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 1158defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 1159defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 1160defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 1161defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 1162defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 1163defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 1164 1165// 15.2. Vector Widening Integer Reduction Instructions 1166defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1167defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1168defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1169defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1170defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1171} // Predicates = [HasVInstructions] 1172 1173// 15.3. Vector Single-Width Floating-Point Reduction Instructions 1174let Predicates = [HasVInstructionsAnyF] in { 1175defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 1176defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>; 1177defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 1178defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 1179 1180// 15.4. Vector Widening Floating-Point Reduction Instructions 1181defm : VPatWidenReductionVL<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1182defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_SEQ_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1183defm : VPatWidenReductionVL<rvv_vecreduce_FADD_vl, fpext_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1184defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1185} // Predicates = [HasVInstructionsAnyF] 1186 1187let Predicates = [HasVInstructionsAnyF] in { 1188 1189// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 1190defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 1191defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 1192defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 1193 1194// 14.3. Vector Widening Floating-Point Add/Subtract Instructions 1195defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fadd_vl, "PseudoVFWADD">; 1196defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fsub_vl, "PseudoVFWSUB">; 1197 1198// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 1199defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 1200defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 1201defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 1202 1203// 14.5. Vector Widening Floating-Point Multiply Instructions 1204defm : VPatWidenBinaryFPVL_VV_VF<riscv_fmul_vl, riscv_fpextend_vl_oneuse, "PseudoVFWMUL">; 1205 1206// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 1207foreach vti = AllFloatVectors in { 1208 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 1209 // works best with how TwoAddressInstructionPass tries commuting. 1210 defvar suffix = vti.LMul.MX; 1211 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1212 vti.RegClass:$rs2, (vti.Mask true_mask), 1213 VLOpFrag)), 1214 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 1215 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1216 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1217 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1218 vti.RegClass:$rs2, (vti.Mask V0), 1219 VLOpFrag)), 1220 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix #"_MASK") 1221 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1222 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>; 1223 1224 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1225 (riscv_fneg_vl vti.RegClass:$rs2, 1226 (vti.Mask true_mask), 1227 VLOpFrag), 1228 (vti.Mask true_mask), 1229 VLOpFrag)), 1230 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 1231 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1232 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1233 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1234 (riscv_fneg_vl vti.RegClass:$rs2, 1235 (vti.Mask srcvalue), 1236 VLOpFrag), 1237 (vti.Mask V0), 1238 VLOpFrag)), 1239 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix #"_MASK") 1240 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1241 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1242 1243 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1244 (vti.Mask srcvalue), 1245 VLOpFrag), 1246 vti.RegClass:$rd, 1247 (riscv_fneg_vl vti.RegClass:$rs2, 1248 (vti.Mask srcvalue), 1249 VLOpFrag), 1250 (vti.Mask true_mask), 1251 VLOpFrag)), 1252 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 1253 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1254 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1255 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1256 (vti.Mask srcvalue), 1257 VLOpFrag), 1258 vti.RegClass:$rd, 1259 (riscv_fneg_vl vti.RegClass:$rs2, 1260 (vti.Mask srcvalue), 1261 VLOpFrag), 1262 (vti.Mask V0), 1263 VLOpFrag)), 1264 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix #"_MASK") 1265 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1266 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1267 1268 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1269 (vti.Mask srcvalue), 1270 VLOpFrag), 1271 vti.RegClass:$rd, vti.RegClass:$rs2, 1272 (vti.Mask true_mask), 1273 VLOpFrag)), 1274 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 1275 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1276 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1277 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1278 (vti.Mask srcvalue), 1279 VLOpFrag), 1280 vti.RegClass:$rd, vti.RegClass:$rs2, 1281 (vti.Mask V0), 1282 VLOpFrag)), 1283 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix #"_MASK") 1284 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1285 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1286 1287 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 1288 // commutable. 1289 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1290 vti.RegClass:$rd, vti.RegClass:$rs2, 1291 (vti.Mask true_mask), 1292 VLOpFrag)), 1293 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1294 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1295 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1296 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1297 vti.RegClass:$rd, vti.RegClass:$rs2, 1298 (vti.Mask V0), 1299 VLOpFrag)), 1300 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1301 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1302 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>; 1303 1304 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1305 vti.RegClass:$rd, 1306 (riscv_fneg_vl vti.RegClass:$rs2, 1307 (vti.Mask srcvalue), 1308 VLOpFrag), 1309 (vti.Mask true_mask), 1310 VLOpFrag)), 1311 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1312 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1313 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1314 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1315 vti.RegClass:$rd, 1316 (riscv_fneg_vl vti.RegClass:$rs2, 1317 (vti.Mask srcvalue), 1318 VLOpFrag), 1319 (vti.Mask V0), 1320 VLOpFrag)), 1321 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1322 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1323 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1324 1325 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1326 (riscv_fneg_vl vti.RegClass:$rd, 1327 (vti.Mask srcvalue), 1328 VLOpFrag), 1329 (riscv_fneg_vl vti.RegClass:$rs2, 1330 (vti.Mask srcvalue), 1331 VLOpFrag), 1332 (vti.Mask true_mask), 1333 VLOpFrag)), 1334 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1335 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1336 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1337 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1338 (riscv_fneg_vl vti.RegClass:$rd, 1339 (vti.Mask srcvalue), 1340 VLOpFrag), 1341 (riscv_fneg_vl vti.RegClass:$rs2, 1342 (vti.Mask srcvalue), 1343 VLOpFrag), 1344 (vti.Mask V0), 1345 VLOpFrag)), 1346 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1347 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1348 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1349 1350 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1351 (riscv_fneg_vl vti.RegClass:$rd, 1352 (vti.Mask srcvalue), 1353 VLOpFrag), 1354 vti.RegClass:$rs2, 1355 (vti.Mask true_mask), 1356 VLOpFrag)), 1357 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1358 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1359 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1360 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1361 (riscv_fneg_vl vti.RegClass:$rd, 1362 (vti.Mask srcvalue), 1363 VLOpFrag), 1364 vti.RegClass:$rs2, 1365 (vti.Mask V0), 1366 VLOpFrag)), 1367 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1368 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1369 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1370 1371 // The splat might be negated. 1372 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1373 (vti.Mask srcvalue), 1374 VLOpFrag), 1375 vti.RegClass:$rd, 1376 (riscv_fneg_vl vti.RegClass:$rs2, 1377 (vti.Mask srcvalue), 1378 VLOpFrag), 1379 (vti.Mask true_mask), 1380 VLOpFrag)), 1381 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1382 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1383 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1384 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1385 (vti.Mask srcvalue), 1386 VLOpFrag), 1387 vti.RegClass:$rd, 1388 (riscv_fneg_vl vti.RegClass:$rs2, 1389 (vti.Mask srcvalue), 1390 VLOpFrag), 1391 (vti.Mask V0), 1392 VLOpFrag)), 1393 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1394 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1395 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1396 1397 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1398 (vti.Mask srcvalue), 1399 VLOpFrag), 1400 vti.RegClass:$rd, vti.RegClass:$rs2, 1401 (vti.Mask true_mask), 1402 VLOpFrag)), 1403 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1404 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1405 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1406 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1407 (vti.Mask srcvalue), 1408 VLOpFrag), 1409 vti.RegClass:$rd, vti.RegClass:$rs2, 1410 (vti.Mask V0), 1411 VLOpFrag)), 1412 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1413 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1414 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1415} 1416 1417// 14.11. Vector Floating-Point MIN/MAX Instructions 1418defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1419defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1420 1421// 14.13. Vector Floating-Point Compare Instructions 1422defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1423defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1424 1425defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1426defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1427 1428defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1429defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1430 1431defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1432defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1433 1434foreach vti = AllFloatVectors in { 1435 // 14.8. Vector Floating-Point Square-Root Instruction 1436 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1437 VLOpFrag), 1438 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1439 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1440 1441 // 14.12. Vector Floating-Point Sign-Injection Instructions 1442 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1443 VLOpFrag), 1444 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1445 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1446 // Handle fneg with VFSGNJN using the same input for both operands. 1447 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), 1448 VLOpFrag), 1449 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX #"_MASK") 1450 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs, 1451 vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 1452 TAIL_AGNOSTIC)>; 1453 1454 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1455 (vti.Vector vti.RegClass:$rs2), 1456 (vti.Mask true_mask), 1457 VLOpFrag), 1458 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1459 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1460 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1461 (riscv_fneg_vl vti.RegClass:$rs2, 1462 (vti.Mask true_mask), 1463 VLOpFrag), 1464 (vti.Mask true_mask), 1465 VLOpFrag), 1466 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1467 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1468 1469 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1470 (SplatFPOp vti.ScalarRegClass:$rs2), 1471 (vti.Mask true_mask), 1472 VLOpFrag), 1473 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1474 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1475} 1476 1477foreach fvti = AllFloatVectors in { 1478 // Floating-point vselects: 1479 // 12.15. Vector Integer Merge Instructions 1480 // 14.15. Vector Floating-Point Merge Instruction 1481 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1482 fvti.RegClass:$rs1, 1483 fvti.RegClass:$rs2, 1484 VLOpFrag)), 1485 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1486 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1487 GPR:$vl, fvti.Log2SEW)>; 1488 1489 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1490 (SplatFPOp fvti.ScalarRegClass:$rs1), 1491 fvti.RegClass:$rs2, 1492 VLOpFrag)), 1493 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1494 fvti.RegClass:$rs2, 1495 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1496 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1497 1498 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1499 (SplatFPOp (fvti.Scalar fpimm0)), 1500 fvti.RegClass:$rs2, 1501 VLOpFrag)), 1502 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1503 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1504 1505 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1506 fvti.RegClass:$rs1, 1507 fvti.RegClass:$rs2, 1508 VLOpFrag)), 1509 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX#"_TU") 1510 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1511 GPR:$vl, fvti.Log2SEW)>; 1512 1513 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1514 (SplatFPOp fvti.ScalarRegClass:$rs1), 1515 fvti.RegClass:$rs2, 1516 VLOpFrag)), 1517 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX#"_TU") 1518 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 1519 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1520 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1521 1522 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1523 (SplatFPOp (fvti.Scalar fpimm0)), 1524 fvti.RegClass:$rs2, 1525 VLOpFrag)), 1526 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") 1527 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), 1528 GPR:$vl, fvti.Log2SEW)>; 1529 1530 // 14.16. Vector Floating-Point Move Instruction 1531 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1532 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1533 (fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)), 1534 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1535 0, GPR:$vl, fvti.Log2SEW)>; 1536 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1537 fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)), 1538 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX#"_TU") 1539 $passthru, 0, GPR:$vl, fvti.Log2SEW)>; 1540 1541 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1542 (fvti.Vector undef), (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1543 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1544 fvti.LMul.MX) 1545 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1546 GPR:$vl, fvti.Log2SEW)>; 1547 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1548 fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1549 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1550 fvti.LMul.MX # "_TU") 1551 $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), 1552 GPR:$vl, fvti.Log2SEW)>; 1553 1554 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1555 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1556 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1557 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1558 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1559 1560 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1561 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1562 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1563 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1564 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1565 foreach fvtiToFWti = AllWidenableFloatVectors in { 1566 defvar fvti = fvtiToFWti.Vti; 1567 defvar fwti = fvtiToFWti.Wti; 1568 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1569 (fvti.Mask V0), 1570 VLOpFrag)), 1571 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK") 1572 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1573 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1574 } 1575 1576 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1577 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1578 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1579 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1580 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1581 foreach fvtiToFWti = AllWidenableFloatVectors in { 1582 defvar fvti = fvtiToFWti.Vti; 1583 defvar fwti = fvtiToFWti.Wti; 1584 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1585 (fwti.Mask V0), 1586 VLOpFrag)), 1587 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK") 1588 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1589 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1590 1591 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1592 (fwti.Mask true_mask), 1593 VLOpFrag)), 1594 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX) 1595 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1596 1597 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1598 (fwti.Mask V0), 1599 VLOpFrag)), 1600 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_MASK") 1601 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1602 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1603 } 1604} 1605 1606} // Predicates = [HasVInstructionsAnyF] 1607 1608let Predicates = [HasVInstructions] in { 1609 1610foreach mti = AllMasks in { 1611 // 16.1 Vector Mask-Register Logical Instructions 1612 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1613 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1614 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1615 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1616 1617 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1618 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1619 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1620 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1621 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1622 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1623 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1624 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1625 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1626 1627 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1628 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1629 VLOpFrag)), 1630 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 1631 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1632 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1633 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1634 VLOpFrag)), 1635 (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 1636 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1637 // XOR is associative so we need 2 patterns for VMXNOR. 1638 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1639 VLOpFrag), 1640 VR:$rs2, VLOpFrag)), 1641 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1642 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1643 1644 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1645 VLOpFrag), 1646 VLOpFrag)), 1647 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1648 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1649 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1650 VLOpFrag), 1651 VLOpFrag)), 1652 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1653 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1654 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1655 VLOpFrag), 1656 VLOpFrag)), 1657 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1658 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1659 1660 // Match the not idiom to the vmnot.m pseudo. 1661 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1662 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1663 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1664 1665 // 16.2 Vector count population in mask vcpop.m 1666 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1667 VLOpFrag)), 1668 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 1669 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1670 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 1671 VLOpFrag)), 1672 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 1673 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 1674} 1675 1676} // Predicates = [HasVInstructions] 1677 1678let Predicates = [HasVInstructions] in { 1679// 17.1. Integer Scalar Move Instructions 1680// 17.4. Vector Register Gather Instruction 1681foreach vti = AllIntegerVectors in { 1682 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1683 vti.ScalarRegClass:$rs1, 1684 VLOpFrag)), 1685 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1686 vti.RegClass:$merge, 1687 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1688 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1689 (vti.Vector vti.RegClass:$rs1), 1690 (vti.Mask true_mask), 1691 VLOpFrag)), 1692 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1693 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1694 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1695 (vti.Mask true_mask), 1696 VLOpFrag)), 1697 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1698 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1699 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1700 (vti.Mask true_mask), 1701 VLOpFrag)), 1702 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1703 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1704 1705 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1706 (riscv_vrgather_vv_vl 1707 vti.RegClass:$rs2, 1708 vti.RegClass:$rs1, 1709 (vti.Mask true_mask), 1710 VLOpFrag), 1711 vti.RegClass:$merge, 1712 VLOpFrag)), 1713 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1714 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1715 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1716 1717 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1718 (riscv_vrgather_vx_vl 1719 vti.RegClass:$rs2, 1720 uimm5:$imm, 1721 (vti.Mask true_mask), 1722 VLOpFrag), 1723 vti.RegClass:$merge, 1724 VLOpFrag)), 1725 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1726 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1727 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1728 1729 // emul = lmul * 16 / sew 1730 defvar vlmul = vti.LMul; 1731 defvar octuple_lmul = vlmul.octuple; 1732 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1733 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1734 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1735 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1736 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1737 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1738 (ivti.Vector ivti.RegClass:$rs1), 1739 (vti.Mask true_mask), 1740 VLOpFrag)), 1741 (!cast<Instruction>(inst) 1742 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1743 1744 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1745 (riscv_vrgatherei16_vv_vl 1746 vti.RegClass:$rs2, 1747 (ivti.Vector ivti.RegClass:$rs1), 1748 (vti.Mask true_mask), 1749 VLOpFrag), 1750 vti.RegClass:$merge, 1751 VLOpFrag)), 1752 (!cast<Instruction>(inst#"_MASK") 1753 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1754 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1755 } 1756} 1757 1758} // Predicates = [HasVInstructions] 1759 1760let Predicates = [HasVInstructionsAnyF] in { 1761 1762// 17.2. Floating-Point Scalar Move Instructions 1763foreach vti = AllFloatVectors in { 1764 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1765 (vti.Scalar (fpimm0)), 1766 VLOpFrag)), 1767 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1768 vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>; 1769 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1770 vti.ScalarRegClass:$rs1, 1771 VLOpFrag)), 1772 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1773 vti.RegClass:$merge, 1774 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1775 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1776 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1777 (ivti.Vector vti.RegClass:$rs1), 1778 (vti.Mask true_mask), 1779 VLOpFrag)), 1780 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1781 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1782 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1783 (vti.Mask true_mask), 1784 VLOpFrag)), 1785 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1786 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1787 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1788 (vti.Mask true_mask), 1789 VLOpFrag)), 1790 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1791 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1792 1793 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1794 (riscv_vrgather_vv_vl 1795 vti.RegClass:$rs2, 1796 (ivti.Vector vti.RegClass:$rs1), 1797 (vti.Mask true_mask), 1798 VLOpFrag), 1799 vti.RegClass:$merge, 1800 VLOpFrag)), 1801 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1802 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1803 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1804 1805 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1806 (riscv_vrgather_vx_vl 1807 vti.RegClass:$rs2, 1808 uimm5:$imm, 1809 (vti.Mask true_mask), 1810 VLOpFrag), 1811 vti.RegClass:$merge, 1812 VLOpFrag)), 1813 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1814 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1815 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1816 1817 defvar vlmul = vti.LMul; 1818 defvar octuple_lmul = vlmul.octuple; 1819 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1820 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1821 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1822 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1823 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1824 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1825 (ivti.Vector ivti.RegClass:$rs1), 1826 (vti.Mask true_mask), 1827 VLOpFrag)), 1828 (!cast<Instruction>(inst) 1829 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1830 1831 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1832 (riscv_vrgatherei16_vv_vl 1833 vti.RegClass:$rs2, 1834 (ivti.Vector ivti.RegClass:$rs1), 1835 (vti.Mask true_mask), 1836 VLOpFrag), 1837 vti.RegClass:$merge, 1838 VLOpFrag)), 1839 (!cast<Instruction>(inst#"_MASK") 1840 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1841 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1842 } 1843} 1844 1845} // Predicates = [HasVInstructionsAnyF] 1846 1847//===----------------------------------------------------------------------===// 1848// Miscellaneous RISCVISD SDNodes 1849//===----------------------------------------------------------------------===// 1850 1851def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1852 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1853 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1854 1855def SDTRVVSlide : SDTypeProfile<1, 5, [ 1856 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1857 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1858]>; 1859def SDTRVVSlide1 : SDTypeProfile<1, 5, [ 1860 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>, 1861 SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, 1862 SDTCisVT<5, XLenVT> 1863]>; 1864 1865def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1866def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1867def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1868def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 1869 1870let Predicates = [HasVInstructions] in { 1871 1872foreach vti = AllIntegerVectors in { 1873 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1874 VLOpFrag)), 1875 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 1876 1877 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef), 1878 (vti.Vector vti.RegClass:$rs1), 1879 GPR:$rs2, (vti.Mask true_mask), 1880 VLOpFrag)), 1881 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1882 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1883 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rd), 1884 (vti.Vector vti.RegClass:$rs1), 1885 GPR:$rs2, (vti.Mask true_mask), 1886 VLOpFrag)), 1887 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX#"_TU") 1888 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1889 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector undef), 1890 (vti.Vector vti.RegClass:$rs1), 1891 GPR:$rs2, (vti.Mask true_mask), 1892 VLOpFrag)), 1893 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 1894 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1895 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rd), 1896 (vti.Vector vti.RegClass:$rs1), 1897 GPR:$rs2, (vti.Mask true_mask), 1898 VLOpFrag)), 1899 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX#"_TU") 1900 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1901} 1902 1903foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1904 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1905 (vti.Vector vti.RegClass:$rs1), 1906 uimm5:$rs2, (vti.Mask true_mask), 1907 VLOpFrag)), 1908 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1909 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1910 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1911 1912 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1913 (vti.Vector vti.RegClass:$rs1), 1914 GPR:$rs2, (vti.Mask true_mask), 1915 VLOpFrag)), 1916 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1917 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1918 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1919 1920 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1921 (vti.Vector vti.RegClass:$rs1), 1922 uimm5:$rs2, (vti.Mask true_mask), 1923 VLOpFrag)), 1924 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1925 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1926 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1927 1928 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1929 (vti.Vector vti.RegClass:$rs1), 1930 GPR:$rs2, (vti.Mask true_mask), 1931 VLOpFrag)), 1932 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1933 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1934 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1935} 1936 1937} // Predicates = [HasVInstructions] 1938