1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// 0.10. This version is still experimental as the 'V' extension hasn't been 12/// ratified yet. 13/// 14/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 15/// 16/// Note: the patterns for RVV intrinsics are found in 17/// RISCVInstrInfoVPseudos.td. 18/// 19//===----------------------------------------------------------------------===// 20 21//===----------------------------------------------------------------------===// 22// Helpers to define the VL patterns. 23//===----------------------------------------------------------------------===// 24 25def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>, 26 SDTCisVT<2, XLenVT>]>; 27def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>, 28 SDTCisVT<2, XLenVT>]>; 29 30def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 31 SDTCisSameAs<0, 2>, 32 SDTCisVec<0>, SDTCisInt<0>, 33 SDTCVecEltisVT<3, i1>, 34 SDTCisSameNumEltsAs<0, 3>, 35 SDTCisVT<4, XLenVT>]>; 36 37def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<2, i1>, 40 SDTCisSameNumEltsAs<0, 2>, 41 SDTCisVT<3, XLenVT>]>; 42def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 43 SDTCisSameAs<0, 2>, 44 SDTCisVec<0>, SDTCisFP<0>, 45 SDTCVecEltisVT<3, i1>, 46 SDTCisSameNumEltsAs<0, 3>, 47 SDTCisVT<4, XLenVT>]>; 48 49def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 50 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<0>, 51 SDTCisVT<1, XLenVT>, 52 SDTCisVT<2, XLenVT>]>>; 53def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 54 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisFP<0>, 55 SDTCisEltOfVec<1, 0>, 56 SDTCisVT<2, XLenVT>]>>; 57def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 58 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 59 SDTCisInt<0>, 60 SDTCisVT<2, XLenVT>, 61 SDTCisVT<3, XLenVT>]>>; 62def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 63 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 64 SDTCisFP<0>, 65 SDTCisEltOfVec<2, 0>, 66 SDTCisVT<3, XLenVT>]>>; 67 68def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL, 69 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 70def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL, 71 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 72 73def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 74def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 76def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 77def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 78def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 79def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 80def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 81def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 83def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 84def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 88def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 89def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 90def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 91def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 92 93def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 94def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 95def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 96def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 97 98def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 99def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 100def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 101def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 102def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 103def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 104def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 105def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 106def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 107def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 108 109def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 110 SDTCisSameAs<0, 2>, 111 SDTCisSameAs<0, 3>, 112 SDTCisVec<0>, SDTCisFP<0>, 113 SDTCVecEltisVT<4, i1>, 114 SDTCisSameNumEltsAs<0, 4>, 115 SDTCisVT<5, XLenVT>]>; 116def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 117 118def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 119 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 120 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 121]>; 122def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126 127def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 128def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 129def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 130 131def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 132 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 133 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 134]>; 135def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 136 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 137 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 138]>; 139 140def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 141def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 142def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 143def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 144 145def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 146 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 147 SDTCisVec<1>, 148 SDTCisSameNumEltsAs<0, 1>, 149 SDTCisSameAs<1, 2>, 150 SDTCisVT<3, OtherVT>, 151 SDTCisSameAs<0, 4>, 152 SDTCisVT<5, XLenVT>]>>; 153 154def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 155 SDTypeProfile<1, 4, [SDTCisVec<0>, 156 SDTCisSameAs<0, 1>, 157 SDTCisVT<2, XLenVT>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCisSameNumEltsAs<0, 2>, 166 SDTCisSameSizeAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 171 SDTypeProfile<1, 4, [SDTCisVec<0>, 172 SDTCisSameAs<0, 1>, 173 SDTCisInt<2>, 174 SDTCVecEltisVT<2, i16>, 175 SDTCisSameNumEltsAs<0, 2>, 176 SDTCVecEltisVT<3, i1>, 177 SDTCisSameNumEltsAs<0, 3>, 178 SDTCisVT<4, XLenVT>]>>; 179 180def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", 181 SDTypeProfile<1, 4, [SDTCisVec<0>, 182 SDTCisVec<1>, 183 SDTCisSameNumEltsAs<0, 1>, 184 SDTCVecEltisVT<1, i1>, 185 SDTCisSameAs<0, 2>, 186 SDTCisSameAs<2, 3>, 187 SDTCisVT<4, XLenVT>]>>; 188 189def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 190 SDTCisSameAs<0, 2>, 191 SDTCVecEltisVT<0, i1>, 192 SDTCisVT<3, XLenVT>]>; 193def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 194def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 195def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 196 197def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 198 199def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 200 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 201 202def riscv_vpopc_vl : SDNode<"RISCVISD::VPOPC_VL", 203 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 204 SDTCisVec<1>, SDTCisInt<1>, 205 SDTCVecEltisVT<2, i1>, 206 SDTCisSameNumEltsAs<1, 2>, 207 SDTCisVT<3, XLenVT>]>>; 208 209def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 210 SDTCisSameNumEltsAs<0, 1>, 211 SDTCisSameNumEltsAs<1, 2>, 212 SDTCVecEltisVT<2, i1>, 213 SDTCisVT<3, XLenVT>]>; 214def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 215def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 216 217def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 218 SDTypeProfile<1, 3, [SDTCisVec<0>, 219 SDTCisVec<1>, 220 SDTCisSameNumEltsAs<0, 2>, 221 SDTCVecEltisVT<2, i1>, 222 SDTCisVT<3, XLenVT>]>>; 223 224def SDT_RISCVVWMUL_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 225 SDTCisSameNumEltsAs<0, 1>, 226 SDTCisSameAs<1, 2>, 227 SDTCisSameNumEltsAs<1, 3>, 228 SDTCVecEltisVT<3, i1>, 229 SDTCisVT<4, XLenVT>]>; 230def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWMUL_VL, [SDNPCommutative]>; 231def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWMUL_VL, [SDNPCommutative]>; 232 233def SDTRVVVecReduce : SDTypeProfile<1, 4, [ 234 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCVecEltisVT<3, i1>, 235 SDTCisSameNumEltsAs<1, 3>, SDTCisVT<4, XLenVT> 236]>; 237 238def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 239 (riscv_mul_vl node:$A, node:$B, node:$C, 240 node:$D), [{ 241 return N->hasOneUse(); 242}]>; 243 244def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 245 (riscv_vwmul_vl node:$A, node:$B, node:$C, 246 node:$D), [{ 247 return N->hasOneUse(); 248}]>; 249 250def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 251 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 252 node:$D), [{ 253 return N->hasOneUse(); 254}]>; 255 256foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 257 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 258 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 259 260// Ignore the vl operand. 261def SplatFPOp : PatFrag<(ops node:$op), 262 (riscv_vfmv_v_f_vl node:$op, srcvalue)>; 263 264def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 265def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 266def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 267def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 268 269multiclass VPatBinaryVL_VV<SDNode vop, 270 string instruction_name, 271 ValueType result_type, 272 ValueType op_type, 273 ValueType mask_type, 274 int sew, 275 LMULInfo vlmul, 276 VReg op_reg_class> { 277 def : Pat<(result_type (vop 278 (op_type op_reg_class:$rs1), 279 (op_type op_reg_class:$rs2), 280 (mask_type true_mask), 281 VLOpFrag)), 282 (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX) 283 op_reg_class:$rs1, 284 op_reg_class:$rs2, 285 GPR:$vl, sew)>; 286 def : Pat<(result_type (vop 287 (op_type op_reg_class:$rs1), 288 (op_type op_reg_class:$rs2), 289 (mask_type V0), 290 VLOpFrag)), 291 (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_MASK") 292 (result_type (IMPLICIT_DEF)), 293 op_reg_class:$rs1, 294 op_reg_class:$rs2, 295 (mask_type V0), GPR:$vl, sew)>; 296} 297 298multiclass VPatBinaryVL_XI<SDNode vop, 299 string instruction_name, 300 string suffix, 301 ValueType result_type, 302 ValueType vop_type, 303 ValueType mask_type, 304 int sew, 305 LMULInfo vlmul, 306 VReg vop_reg_class, 307 ComplexPattern SplatPatKind, 308 DAGOperand xop_kind> { 309 def : Pat<(result_type (vop 310 (vop_type vop_reg_class:$rs1), 311 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))), 312 (mask_type true_mask), 313 VLOpFrag)), 314 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX) 315 vop_reg_class:$rs1, 316 xop_kind:$rs2, 317 GPR:$vl, sew)>; 318 def : Pat<(result_type (vop 319 (vop_type vop_reg_class:$rs1), 320 (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))), 321 (mask_type V0), 322 VLOpFrag)), 323 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 324 (result_type (IMPLICIT_DEF)), 325 vop_reg_class:$rs1, 326 xop_kind:$rs2, 327 (mask_type V0), GPR:$vl, sew)>; 328} 329 330multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 331 foreach vti = AllIntegerVectors in { 332 defm : VPatBinaryVL_VV<vop, instruction_name, 333 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 334 vti.LMul, vti.RegClass>; 335 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 336 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 337 vti.LMul, vti.RegClass, SplatPat, GPR>; 338 } 339} 340 341multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 342 Operand ImmType = simm5> 343 : VPatBinaryVL_VV_VX<vop, instruction_name> { 344 foreach vti = AllIntegerVectors in { 345 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 346 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 347 vti.LMul, vti.RegClass, 348 !cast<ComplexPattern>(SplatPat#_#ImmType), 349 ImmType>; 350 } 351} 352 353multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 354 foreach VtiToWti = AllWidenableIntVectors in { 355 defvar vti = VtiToWti.Vti; 356 defvar wti = VtiToWti.Wti; 357 defm : VPatBinaryVL_VV<vop, instruction_name, 358 wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 359 vti.LMul, vti.RegClass>; 360 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 361 wti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 362 vti.LMul, vti.RegClass, SplatPat, GPR>; 363 } 364} 365 366class VPatBinaryVL_VF<SDNode vop, 367 string instruction_name, 368 ValueType result_type, 369 ValueType vop_type, 370 ValueType mask_type, 371 int sew, 372 LMULInfo vlmul, 373 VReg vop_reg_class, 374 RegisterClass scalar_reg_class> : 375 Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 376 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 377 (mask_type true_mask), 378 VLOpFrag)), 379 (!cast<Instruction>(instruction_name#"_"#vlmul.MX) 380 vop_reg_class:$rs1, 381 scalar_reg_class:$rs2, 382 GPR:$vl, sew)>; 383 384multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 385 foreach vti = AllFloatVectors in { 386 defm : VPatBinaryVL_VV<vop, instruction_name, 387 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 388 vti.LMul, vti.RegClass>; 389 def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 390 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 391 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 392 } 393} 394 395multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 396 foreach fvti = AllFloatVectors in 397 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 398 fvti.RegClass:$rs1, 399 (fvti.Mask true_mask), 400 VLOpFrag)), 401 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 402 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 403 GPR:$vl, fvti.Log2SEW)>; 404} 405 406multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 407 CondCode cc> { 408 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 409 vti.RegClass:$rs2, cc, 410 (vti.Mask true_mask), 411 VLOpFrag)), 412 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 413 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 414 vti.Log2SEW)>; 415} 416 417// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 418multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 419 CondCode cc, CondCode invcc> : 420 VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 421 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 422 vti.RegClass:$rs1, invcc, 423 (vti.Mask true_mask), 424 VLOpFrag)), 425 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 426 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 427 vti.Log2SEW)>; 428} 429 430multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 431 CondCode cc, CondCode invcc> { 432 defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX); 433 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 434 (SplatPat (XLenVT GPR:$rs2)), cc, 435 (vti.Mask true_mask), 436 VLOpFrag)), 437 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 438 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 439 (vti.Vector vti.RegClass:$rs1), invcc, 440 (vti.Mask true_mask), 441 VLOpFrag)), 442 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 443} 444 445multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 446 CondCode cc, CondCode invcc> { 447 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 448 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 449 (SplatPat_simm5 simm5:$rs2), cc, 450 (vti.Mask true_mask), 451 VLOpFrag)), 452 (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.Log2SEW)>; 453 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 454 (vti.Vector vti.RegClass:$rs1), invcc, 455 (vti.Mask true_mask), 456 VLOpFrag)), 457 (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; 458} 459 460multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name, 461 CondCode cc, ComplexPattern splatpat_kind> { 462 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 463 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 464 (splatpat_kind simm5:$rs2), cc, 465 (vti.Mask true_mask), 466 VLOpFrag)), 467 (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), 468 GPR:$vl, vti.Log2SEW)>; 469} 470 471multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 472 string inst_name, 473 string swapped_op_inst_name> { 474 foreach fvti = AllFloatVectors in { 475 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 476 fvti.RegClass:$rs2, 477 cc, 478 (fvti.Mask true_mask), 479 VLOpFrag)), 480 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX) 481 fvti.RegClass:$rs1, fvti.RegClass:$rs2, GPR:$vl, fvti.Log2SEW)>; 482 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 483 (SplatFPOp fvti.ScalarRegClass:$rs2), 484 cc, 485 (fvti.Mask true_mask), 486 VLOpFrag)), 487 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 488 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 489 GPR:$vl, fvti.Log2SEW)>; 490 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 491 (fvti.Vector fvti.RegClass:$rs1), 492 cc, 493 (fvti.Mask true_mask), 494 VLOpFrag)), 495 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 496 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 497 GPR:$vl, fvti.Log2SEW)>; 498 } 499} 500 501multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 502 list <VTypeInfoToFraction> fraction_list> { 503 foreach vtiTofti = fraction_list in { 504 defvar vti = vtiTofti.Vti; 505 defvar fti = vtiTofti.Fti; 506 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 507 true_mask, VLOpFrag)), 508 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX) 509 fti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 510 } 511} 512 513multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 514 foreach fvti = AllFloatVectors in { 515 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 516 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 517 (fvti.Mask true_mask), 518 VLOpFrag)), 519 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 520 fvti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 521 } 522} 523 524multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 525 foreach fvti = AllFloatVectors in { 526 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 527 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 528 (ivti.Mask true_mask), 529 VLOpFrag)), 530 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 531 ivti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 532 } 533} 534 535multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 536 foreach fvtiToFWti = AllWidenableFloatVectors in { 537 defvar fvti = fvtiToFWti.Vti; 538 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 539 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 540 (fvti.Mask true_mask), 541 VLOpFrag)), 542 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 543 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 544 } 545} 546 547multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 548 foreach vtiToWti = AllWidenableIntToFloatVectors in { 549 defvar ivti = vtiToWti.Vti; 550 defvar fwti = vtiToWti.Wti; 551 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 552 (ivti.Mask true_mask), 553 VLOpFrag)), 554 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 555 ivti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 556 } 557} 558 559multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 560 foreach vtiToWti = AllWidenableIntToFloatVectors in { 561 defvar vti = vtiToWti.Vti; 562 defvar fwti = vtiToWti.Wti; 563 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 564 (fwti.Mask true_mask), 565 VLOpFrag)), 566 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX) 567 fwti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 568 } 569} 570 571multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 572 foreach fvtiToFWti = AllWidenableFloatVectors in { 573 defvar fvti = fvtiToFWti.Vti; 574 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 575 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 576 (iwti.Mask true_mask), 577 VLOpFrag)), 578 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 579 iwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 580 } 581} 582 583multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 584 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 585 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 586 def: Pat<(vti_m1.Vector (vop (vti.Vector vti.RegClass:$rs1), VR:$rs2, 587 (vti.Mask true_mask), 588 VLOpFrag)), 589 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 590 (vti_m1.Vector (IMPLICIT_DEF)), 591 (vti.Vector vti.RegClass:$rs1), 592 (vti_m1.Vector VR:$rs2), 593 GPR:$vl, vti.Log2SEW)>; 594 } 595} 596 597//===----------------------------------------------------------------------===// 598// Patterns. 599//===----------------------------------------------------------------------===// 600 601let Predicates = [HasStdExtV] in { 602 603// 7.4. Vector Unit-Stride Instructions 604foreach vti = AllVectors in { 605 defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX); 606 defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX); 607 // Load 608 def : Pat<(vti.Vector (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)), 609 (load_instr BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>; 610 // Store 611 def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), BaseAddr:$rs1, 612 VLOpFrag), 613 (store_instr vti.RegClass:$rs2, BaseAddr:$rs1, GPR:$vl, vti.Log2SEW)>; 614} 615 616foreach mti = AllMasks in { 617 defvar load_instr = !cast<Instruction>("PseudoVLE1_V_"#mti.BX); 618 defvar store_instr = !cast<Instruction>("PseudoVSE1_V_"#mti.BX); 619 def : Pat<(mti.Mask (riscv_vle_vl BaseAddr:$rs1, VLOpFrag)), 620 (load_instr BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>; 621 def : Pat<(riscv_vse_vl (mti.Mask VR:$rs2), BaseAddr:$rs1, 622 VLOpFrag), 623 (store_instr VR:$rs2, BaseAddr:$rs1, GPR:$vl, mti.Log2SEW)>; 624} 625 626// 12.1. Vector Single-Width Integer Add and Subtract 627defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 628defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 629// Handle VRSUB specially since it's the only integer binary op with reversed 630// pattern operands 631foreach vti = AllIntegerVectors in { 632 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 633 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 634 VLOpFrag), 635 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX) 636 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 637 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 638 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 639 VLOpFrag), 640 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 641 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 642 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 643 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 644 (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), 645 VLOpFrag), 646 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX) 647 vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; 648 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 649 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 650 VLOpFrag), 651 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 652 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 653 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 654} 655 656// 12.3. Vector Integer Extension 657defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 658 AllFractionableVF2IntVectors>; 659defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 660 AllFractionableVF2IntVectors>; 661defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 662 AllFractionableVF4IntVectors>; 663defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 664 AllFractionableVF4IntVectors>; 665defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 666 AllFractionableVF8IntVectors>; 667defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 668 AllFractionableVF8IntVectors>; 669 670// 12.5. Vector Bitwise Logical Instructions 671defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 672defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 673defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 674 675// 12.6. Vector Single-Width Bit Shift Instructions 676defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 677defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 678defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 679 680foreach vti = AllIntegerVectors in { 681 // Emit shift by 1 as an add since it might be faster. 682 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 683 (riscv_vmv_v_x_vl 1, (XLenVT srcvalue)), 684 (vti.Mask true_mask), 685 VLOpFrag), 686 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 687 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 688} 689 690// 12.7. Vector Narrowing Integer Right Shift Instructions 691foreach vtiTowti = AllWidenableIntVectors in { 692 defvar vti = vtiTowti.Vti; 693 defvar wti = vtiTowti.Wti; 694 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 695 (vti.Mask true_mask), 696 VLOpFrag)), 697 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) 698 wti.RegClass:$rs1, 0, GPR:$vl, vti.Log2SEW)>; 699 700 def : Pat<(vti.Vector 701 (riscv_trunc_vector_vl 702 (wti.Vector 703 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 704 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 705 (!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX) 706 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 707 def : Pat<(vti.Vector 708 (riscv_trunc_vector_vl 709 (wti.Vector 710 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 711 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 712 (!cast<Instruction>("PseudoVNSRA_WI_"#vti.LMul.MX) 713 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 714 715 def : Pat<(vti.Vector 716 (riscv_trunc_vector_vl 717 (wti.Vector 718 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 719 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 720 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 721 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 722 def : Pat<(vti.Vector 723 (riscv_trunc_vector_vl 724 (wti.Vector 725 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 726 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 727 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) 728 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 729} 730 731// 12.8. Vector Integer Comparison Instructions 732foreach vti = AllIntegerVectors in { 733 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 734 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 735 736 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 737 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 738 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 739 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 740 741 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 742 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 743 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 744 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 745 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 746 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 747 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 748 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 749 // There is no VMSGE(U)_VX instruction 750 751 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 752 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 753 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 754 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 755 756 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT, 757 SplatPat_simm5_plus1>; 758 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT, 759 SplatPat_simm5_plus1_nonzero>; 760 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE, 761 SplatPat_simm5_plus1>; 762 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGTU", SETUGE, 763 SplatPat_simm5_plus1_nonzero>; 764} // foreach vti = AllIntegerVectors 765 766// 12.9. Vector Integer Min/Max Instructions 767defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 768defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 769defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 770defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 771 772// 12.10. Vector Single-Width Integer Multiply Instructions 773defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 774defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 775defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 776 777// 12.11. Vector Integer Divide Instructions 778defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 779defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 780defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 781defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 782 783// 12.12. Vector Widening Integer Multiply Instructions 784defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 785defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 786 787// 12.13 Vector Single-Width Integer Multiply-Add Instructions 788foreach vti = AllIntegerVectors in { 789 // NOTE: We choose VMADD because it has the most commuting freedom. So it 790 // works best with how TwoAddressInstructionPass tries commuting. 791 defvar suffix = vti.LMul.MX; 792 def : Pat<(vti.Vector 793 (riscv_add_vl vti.RegClass:$rs2, 794 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 795 vti.RegClass:$rd, 796 (vti.Mask true_mask), VLOpFrag), 797 (vti.Mask true_mask), VLOpFrag)), 798 (!cast<Instruction>("PseudoVMADD_VV_"# suffix) 799 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 800 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 801 def : Pat<(vti.Vector 802 (riscv_sub_vl vti.RegClass:$rs2, 803 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 804 vti.RegClass:$rd, 805 (vti.Mask true_mask), VLOpFrag), 806 (vti.Mask true_mask), VLOpFrag)), 807 (!cast<Instruction>("PseudoVNMSUB_VV_"# suffix) 808 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 809 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 810 811 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 812 // commutable. 813 def : Pat<(vti.Vector 814 (riscv_add_vl vti.RegClass:$rs2, 815 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 816 vti.RegClass:$rd, 817 (vti.Mask true_mask), VLOpFrag), 818 (vti.Mask true_mask), VLOpFrag)), 819 (!cast<Instruction>("PseudoVMADD_VX_" # suffix) 820 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 821 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 822 def : Pat<(vti.Vector 823 (riscv_sub_vl vti.RegClass:$rs2, 824 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 825 vti.RegClass:$rd, 826 (vti.Mask true_mask), 827 VLOpFrag), 828 (vti.Mask true_mask), VLOpFrag)), 829 (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix) 830 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 831 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 832} 833 834// 12.14. Vector Widening Integer Multiply-Add Instructions 835foreach vtiTowti = AllWidenableIntVectors in { 836 defvar vti = vtiTowti.Vti; 837 defvar wti = vtiTowti.Wti; 838 def : Pat<(wti.Vector 839 (riscv_add_vl wti.RegClass:$rd, 840 (riscv_vwmul_vl_oneuse vti.RegClass:$rs1, 841 (vti.Vector vti.RegClass:$rs2), 842 (vti.Mask true_mask), VLOpFrag), 843 (vti.Mask true_mask), VLOpFrag)), 844 (!cast<Instruction>("PseudoVWMACC_VV_" # vti.LMul.MX) 845 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 846 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 847 def : Pat<(wti.Vector 848 (riscv_add_vl wti.RegClass:$rd, 849 (riscv_vwmulu_vl_oneuse vti.RegClass:$rs1, 850 (vti.Vector vti.RegClass:$rs2), 851 (vti.Mask true_mask), VLOpFrag), 852 (vti.Mask true_mask), VLOpFrag)), 853 (!cast<Instruction>("PseudoVWMACCU_VV_" # vti.LMul.MX) 854 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 855 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 856 857 def : Pat<(wti.Vector 858 (riscv_add_vl wti.RegClass:$rd, 859 (riscv_vwmul_vl_oneuse (SplatPat XLenVT:$rs1), 860 (vti.Vector vti.RegClass:$rs2), 861 (vti.Mask true_mask), VLOpFrag), 862 (vti.Mask true_mask), VLOpFrag)), 863 (!cast<Instruction>("PseudoVWMACC_VX_" # vti.LMul.MX) 864 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 865 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 866 def : Pat<(wti.Vector 867 (riscv_add_vl wti.RegClass:$rd, 868 (riscv_vwmulu_vl_oneuse (SplatPat XLenVT:$rs1), 869 (vti.Vector vti.RegClass:$rs2), 870 (vti.Mask true_mask), VLOpFrag), 871 (vti.Mask true_mask), VLOpFrag)), 872 (!cast<Instruction>("PseudoVWMACCU_VX_" # vti.LMul.MX) 873 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 874 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 875} 876 877// 12.15. Vector Integer Merge Instructions 878foreach vti = AllIntegerVectors in { 879 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 880 vti.RegClass:$rs1, 881 vti.RegClass:$rs2, 882 VLOpFrag)), 883 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 884 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 885 GPR:$vl, vti.Log2SEW)>; 886 887 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 888 (SplatPat XLenVT:$rs1), 889 vti.RegClass:$rs2, 890 VLOpFrag)), 891 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 892 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 893 894 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 895 (SplatPat_simm5 simm5:$rs1), 896 vti.RegClass:$rs2, 897 VLOpFrag)), 898 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 899 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 900} 901 902// 12.16. Vector Integer Move Instructions 903foreach vti = AllIntegerVectors in { 904 def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, VLOpFrag)), 905 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 906 $rs2, GPR:$vl, vti.Log2SEW)>; 907 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 908 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (ImmPat XLenVT:$imm5), 909 VLOpFrag)), 910 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 911 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 912} 913 914// 12.1. Vector Single-Width Saturating Add and Subtract 915defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 916defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 917defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 918defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 919 920} // Predicates = [HasStdExtV] 921 922// 15.1. Vector Single-Width Integer Reduction Instructions 923let Predicates = [HasStdExtV] in { 924defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 925defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 926defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 927defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 928defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 929defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 930defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 931defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 932} // Predicates = [HasStdExtV] 933 934// 15.3. Vector Single-Width Floating-Point Reduction Instructions 935let Predicates = [HasStdExtV, HasStdExtF] in { 936defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 937defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDSUM", /*is_float*/1>; 938defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 939defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 940} // Predicates = [HasStdExtV, HasStdExtF] 941 942let Predicates = [HasStdExtV, HasStdExtF] in { 943 944// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 945defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 946defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 947defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 948 949// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 950defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 951defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 952defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 953 954// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 955foreach vti = AllFloatVectors in { 956 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 957 // works best with how TwoAddressInstructionPass tries commuting. 958 defvar suffix = vti.LMul.MX; 959 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 960 vti.RegClass:$rs2, (vti.Mask true_mask), 961 VLOpFrag)), 962 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 963 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 964 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 965 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 966 (riscv_fneg_vl vti.RegClass:$rs2, 967 (vti.Mask true_mask), 968 VLOpFrag), 969 (vti.Mask true_mask), 970 VLOpFrag)), 971 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 972 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 973 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 974 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 975 (vti.Mask true_mask), 976 VLOpFrag), 977 vti.RegClass:$rd, 978 (riscv_fneg_vl vti.RegClass:$rs2, 979 (vti.Mask true_mask), 980 VLOpFrag), 981 (vti.Mask true_mask), 982 VLOpFrag)), 983 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 984 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 985 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 986 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 987 (vti.Mask true_mask), 988 VLOpFrag), 989 vti.RegClass:$rd, vti.RegClass:$rs2, 990 (vti.Mask true_mask), 991 VLOpFrag)), 992 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 993 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 994 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 995 996 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 997 // commutable. 998 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 999 vti.RegClass:$rd, vti.RegClass:$rs2, 1000 (vti.Mask true_mask), 1001 VLOpFrag)), 1002 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1003 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1004 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1005 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1006 vti.RegClass:$rd, 1007 (riscv_fneg_vl vti.RegClass:$rs2, 1008 (vti.Mask true_mask), 1009 VLOpFrag), 1010 (vti.Mask true_mask), 1011 VLOpFrag)), 1012 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1013 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1014 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1015 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1016 (riscv_fneg_vl vti.RegClass:$rd, 1017 (vti.Mask true_mask), 1018 VLOpFrag), 1019 (riscv_fneg_vl vti.RegClass:$rs2, 1020 (vti.Mask true_mask), 1021 VLOpFrag), 1022 (vti.Mask true_mask), 1023 VLOpFrag)), 1024 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1025 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1026 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1027 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1028 (riscv_fneg_vl vti.RegClass:$rd, 1029 (vti.Mask true_mask), 1030 VLOpFrag), 1031 vti.RegClass:$rs2, 1032 (vti.Mask true_mask), 1033 VLOpFrag)), 1034 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1035 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1036 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1037 1038 // The splat might be negated. 1039 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1040 (vti.Mask true_mask), 1041 VLOpFrag), 1042 vti.RegClass:$rd, 1043 (riscv_fneg_vl vti.RegClass:$rs2, 1044 (vti.Mask true_mask), 1045 VLOpFrag), 1046 (vti.Mask true_mask), 1047 VLOpFrag)), 1048 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1049 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1050 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1051 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1052 (vti.Mask true_mask), 1053 VLOpFrag), 1054 vti.RegClass:$rd, vti.RegClass:$rs2, 1055 (vti.Mask true_mask), 1056 VLOpFrag)), 1057 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1058 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1059 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1060} 1061 1062// 14.11. Vector Floating-Point MIN/MAX Instructions 1063defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1064defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1065 1066// 14.13. Vector Floating-Point Compare Instructions 1067defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1068defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1069 1070defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1071defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1072 1073defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1074defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1075 1076defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1077defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1078 1079foreach vti = AllFloatVectors in { 1080 // 14.8. Vector Floating-Point Square-Root Instruction 1081 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1082 VLOpFrag), 1083 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1084 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1085 1086 // 14.12. Vector Floating-Point Sign-Injection Instructions 1087 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1088 VLOpFrag), 1089 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1090 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1091 // Handle fneg with VFSGNJN using the same input for both operands. 1092 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1093 VLOpFrag), 1094 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1095 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1096 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1097 (vti.Vector vti.RegClass:$rs2), 1098 (vti.Mask true_mask), 1099 VLOpFrag), 1100 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1101 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1102 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1103 (riscv_fneg_vl vti.RegClass:$rs2, 1104 (vti.Mask true_mask), 1105 VLOpFrag), 1106 (vti.Mask true_mask), 1107 VLOpFrag), 1108 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1109 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1110 1111 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1112 (SplatFPOp vti.ScalarRegClass:$rs2), 1113 (vti.Mask true_mask), 1114 VLOpFrag), 1115 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1116 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1117} 1118 1119foreach fvti = AllFloatVectors in { 1120 // Floating-point vselects: 1121 // 12.15. Vector Integer Merge Instructions 1122 // 14.15. Vector Floating-Point Merge Instruction 1123 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1124 fvti.RegClass:$rs1, 1125 fvti.RegClass:$rs2, 1126 VLOpFrag)), 1127 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1128 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1129 GPR:$vl, fvti.Log2SEW)>; 1130 1131 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1132 (SplatFPOp fvti.ScalarRegClass:$rs1), 1133 fvti.RegClass:$rs2, 1134 VLOpFrag)), 1135 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1136 fvti.RegClass:$rs2, 1137 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1138 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1139 1140 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1141 (SplatFPOp (fvti.Scalar fpimm0)), 1142 fvti.RegClass:$rs2, 1143 VLOpFrag)), 1144 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1145 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1146 1147 // 14.16. Vector Floating-Point Move Instruction 1148 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1149 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1150 (fvti.Scalar (fpimm0)), VLOpFrag)), 1151 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1152 0, GPR:$vl, fvti.Log2SEW)>; 1153 1154 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1155 (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1156 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1157 fvti.LMul.MX) 1158 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1159 GPR:$vl, fvti.Log2SEW)>; 1160 1161 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1162 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1163 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1164 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1165 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1166 1167 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1168 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1169 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1170 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1171 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1172 foreach fvtiToFWti = AllWidenableFloatVectors in { 1173 defvar fvti = fvtiToFWti.Vti; 1174 defvar fwti = fvtiToFWti.Wti; 1175 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1176 (fvti.Mask true_mask), 1177 VLOpFrag)), 1178 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX) 1179 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1180 } 1181 1182 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1183 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1184 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1185 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1186 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1187 foreach fvtiToFWti = AllWidenableFloatVectors in { 1188 defvar fvti = fvtiToFWti.Vti; 1189 defvar fwti = fvtiToFWti.Wti; 1190 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1191 (fwti.Mask true_mask), 1192 VLOpFrag)), 1193 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX) 1194 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1195 1196 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1197 (fwti.Mask true_mask), 1198 VLOpFrag)), 1199 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX) 1200 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1201 } 1202} 1203 1204} // Predicates = [HasStdExtV, HasStdExtF] 1205 1206let Predicates = [HasStdExtV] in { 1207 1208foreach mti = AllMasks in { 1209 // 16.1 Vector Mask-Register Logical Instructions 1210 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1211 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1212 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1213 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1214 1215 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1216 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1217 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1218 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1219 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1220 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1221 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1222 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1223 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1224 1225 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1226 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1227 VLOpFrag)), 1228 (!cast<Instruction>("PseudoVMANDNOT_MM_" # mti.LMul.MX) 1229 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1230 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1231 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1232 VLOpFrag)), 1233 (!cast<Instruction>("PseudoVMORNOT_MM_" # mti.LMul.MX) 1234 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1235 // XOR is associative so we need 2 patterns for VMXNOR. 1236 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1237 VLOpFrag), 1238 VR:$rs2, VLOpFrag)), 1239 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1240 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1241 1242 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1243 VLOpFrag), 1244 VLOpFrag)), 1245 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1246 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1247 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1248 VLOpFrag), 1249 VLOpFrag)), 1250 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1251 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1252 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1253 VLOpFrag), 1254 VLOpFrag)), 1255 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1256 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1257 1258 // Match the not idiom to the vmnot.m pseudo. 1259 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1260 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1261 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1262 1263 // 16.2 Vector Mask Population Count vpopc 1264 def : Pat<(XLenVT (riscv_vpopc_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1265 VLOpFrag)), 1266 (!cast<Instruction>("PseudoVPOPC_M_" # mti.BX) 1267 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1268} 1269 1270} // Predicates = [HasStdExtV] 1271 1272let Predicates = [HasStdExtV] in { 1273// 17.1. Integer Scalar Move Instructions 1274// 17.4. Vector Register Gather Instruction 1275foreach vti = AllIntegerVectors in { 1276 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1277 vti.ScalarRegClass:$rs1, 1278 VLOpFrag)), 1279 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1280 vti.RegClass:$merge, 1281 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1282 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1283 (vti.Vector vti.RegClass:$rs1), 1284 (vti.Mask true_mask), 1285 VLOpFrag)), 1286 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1287 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1288 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1289 (vti.Mask true_mask), 1290 VLOpFrag)), 1291 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1292 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1293 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1294 (vti.Mask true_mask), 1295 VLOpFrag)), 1296 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1297 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1298 1299 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1300 (riscv_vrgather_vv_vl 1301 vti.RegClass:$rs2, 1302 vti.RegClass:$rs1, 1303 (vti.Mask true_mask), 1304 VLOpFrag), 1305 vti.RegClass:$merge, 1306 VLOpFrag)), 1307 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1308 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1309 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1310 1311 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1312 (riscv_vrgather_vx_vl 1313 vti.RegClass:$rs2, 1314 uimm5:$imm, 1315 (vti.Mask true_mask), 1316 VLOpFrag), 1317 vti.RegClass:$merge, 1318 VLOpFrag)), 1319 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1320 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1321 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1322 1323 // emul = lmul * 16 / sew 1324 defvar vlmul = vti.LMul; 1325 defvar octuple_lmul = vlmul.octuple; 1326 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1327 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1328 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1329 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1330 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1331 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1332 (ivti.Vector ivti.RegClass:$rs1), 1333 (vti.Mask true_mask), 1334 VLOpFrag)), 1335 (!cast<Instruction>(inst) 1336 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1337 1338 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1339 (riscv_vrgatherei16_vv_vl 1340 vti.RegClass:$rs2, 1341 (ivti.Vector ivti.RegClass:$rs1), 1342 (vti.Mask true_mask), 1343 VLOpFrag), 1344 vti.RegClass:$merge, 1345 VLOpFrag)), 1346 (!cast<Instruction>(inst#"_MASK") 1347 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1348 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1349 } 1350} 1351 1352} // Predicates = [HasStdExtV] 1353 1354let Predicates = [HasStdExtV, HasStdExtF] in { 1355 1356// 17.2. Floating-Point Scalar Move Instructions 1357foreach vti = AllFloatVectors in { 1358 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1359 vti.ScalarRegClass:$rs1, 1360 VLOpFrag)), 1361 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1362 vti.RegClass:$merge, 1363 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1364 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1365 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1366 (ivti.Vector vti.RegClass:$rs1), 1367 (vti.Mask true_mask), 1368 VLOpFrag)), 1369 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1370 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1371 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1372 (vti.Mask true_mask), 1373 VLOpFrag)), 1374 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1375 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1376 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1377 (vti.Mask true_mask), 1378 VLOpFrag)), 1379 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1380 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1381 1382 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1383 (riscv_vrgather_vv_vl 1384 vti.RegClass:$rs2, 1385 (ivti.Vector vti.RegClass:$rs1), 1386 (vti.Mask true_mask), 1387 VLOpFrag), 1388 vti.RegClass:$merge, 1389 VLOpFrag)), 1390 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1391 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1392 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1393 1394 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1395 (riscv_vrgather_vx_vl 1396 vti.RegClass:$rs2, 1397 uimm5:$imm, 1398 (vti.Mask true_mask), 1399 VLOpFrag), 1400 vti.RegClass:$merge, 1401 VLOpFrag)), 1402 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1403 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1404 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1405 1406 defvar vlmul = vti.LMul; 1407 defvar octuple_lmul = vlmul.octuple; 1408 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1409 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1410 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1411 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1412 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1413 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1414 (ivti.Vector ivti.RegClass:$rs1), 1415 (vti.Mask true_mask), 1416 VLOpFrag)), 1417 (!cast<Instruction>(inst) 1418 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1419 1420 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1421 (riscv_vrgatherei16_vv_vl 1422 vti.RegClass:$rs2, 1423 (ivti.Vector ivti.RegClass:$rs1), 1424 (vti.Mask true_mask), 1425 VLOpFrag), 1426 vti.RegClass:$merge, 1427 VLOpFrag)), 1428 (!cast<Instruction>(inst#"_MASK") 1429 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1430 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1431 } 1432} 1433 1434} // Predicates = [HasStdExtV, HasStdExtF] 1435 1436//===----------------------------------------------------------------------===// 1437// Miscellaneous RISCVISD SDNodes 1438//===----------------------------------------------------------------------===// 1439 1440def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1441 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1442 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1443 1444def SDTRVVSlide : SDTypeProfile<1, 5, [ 1445 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1446 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1447]>; 1448def SDTRVVSlide1 : SDTypeProfile<1, 4, [ 1449 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisInt<0>, SDTCisVT<2, XLenVT>, 1450 SDTCVecEltisVT<3, i1>, SDTCisSameNumEltsAs<0, 3>, SDTCisVT<4, XLenVT> 1451]>; 1452 1453def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1454def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1455def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1456def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 1457 1458let Predicates = [HasStdExtV] in { 1459 1460foreach vti = AllIntegerVectors in { 1461 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1462 VLOpFrag)), 1463 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 1464 1465 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rs1), 1466 GPR:$rs2, (vti.Mask true_mask), 1467 VLOpFrag)), 1468 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1469 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1470 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rs1), 1471 GPR:$rs2, (vti.Mask true_mask), 1472 VLOpFrag)), 1473 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 1474 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1475} 1476 1477foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1478 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1479 (vti.Vector vti.RegClass:$rs1), 1480 uimm5:$rs2, (vti.Mask true_mask), 1481 VLOpFrag)), 1482 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1483 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1484 GPR:$vl, vti.Log2SEW)>; 1485 1486 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1487 (vti.Vector vti.RegClass:$rs1), 1488 GPR:$rs2, (vti.Mask true_mask), 1489 VLOpFrag)), 1490 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1491 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1492 GPR:$vl, vti.Log2SEW)>; 1493 1494 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1495 (vti.Vector vti.RegClass:$rs1), 1496 uimm5:$rs2, (vti.Mask true_mask), 1497 VLOpFrag)), 1498 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1499 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1500 GPR:$vl, vti.Log2SEW)>; 1501 1502 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1503 (vti.Vector vti.RegClass:$rs1), 1504 GPR:$rs2, (vti.Mask true_mask), 1505 VLOpFrag)), 1506 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1507 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1508 GPR:$vl, vti.Log2SEW)>; 1509} 1510 1511} // Predicates = [HasStdExtV] 1512