1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// version 1.0. 12/// 13/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 14/// 15/// Note: the patterns for RVV intrinsics are found in 16/// RISCVInstrInfoVPseudos.td. 17/// 18//===----------------------------------------------------------------------===// 19 20//===----------------------------------------------------------------------===// 21// Helpers to define the VL patterns. 22//===----------------------------------------------------------------------===// 23 24def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 25 SDTCisSameAs<0, 2>, 26 SDTCisVec<0>, SDTCisInt<0>, 27 SDTCVecEltisVT<3, i1>, 28 SDTCisSameNumEltsAs<0, 3>, 29 SDTCisVT<4, XLenVT>]>; 30 31def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 32 SDTCisVec<0>, SDTCisFP<0>, 33 SDTCVecEltisVT<2, i1>, 34 SDTCisSameNumEltsAs<0, 2>, 35 SDTCisVT<3, XLenVT>]>; 36def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<3, i1>, 40 SDTCisSameNumEltsAs<0, 3>, 41 SDTCisVT<4, XLenVT>]>; 42 43def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 44 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, 45 SDTCisSameAs<0, 1>, 46 SDTCisVT<2, XLenVT>, 47 SDTCisVT<3, XLenVT>]>>; 48def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 49 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 50 SDTCisSameAs<0, 1>, 51 SDTCisEltOfVec<2, 0>, 52 SDTCisVT<3, XLenVT>]>>; 53def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 54 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 55 SDTCisInt<0>, 56 SDTCisVT<2, XLenVT>, 57 SDTCisVT<3, XLenVT>]>>; 58def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 59 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 60 SDTCisFP<0>, 61 SDTCisEltOfVec<2, 0>, 62 SDTCisVT<3, XLenVT>]>>; 63 64def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 65def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 66def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 67def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 68def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 69def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 70def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 71def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 72def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 73def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 74def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 76def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 77def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 78def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 79def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 80def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 81def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 83 84def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 88 89def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 90def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 91def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 92def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 93def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 94def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 95def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 96def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 97def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 98def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 99 100def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 101 SDTCisSameAs<0, 2>, 102 SDTCisSameAs<0, 3>, 103 SDTCisVec<0>, SDTCisFP<0>, 104 SDTCVecEltisVT<4, i1>, 105 SDTCisSameNumEltsAs<0, 4>, 106 SDTCisVT<5, XLenVT>]>; 107def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 108 109def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 110 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 111 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 112]>; 113def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 114 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 115 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 116]>; 117 118def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 119def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 120def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 121 122def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 127 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 128 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 129]>; 130 131def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 132def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 133def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 134def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 135 136def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 137 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 138 SDTCisVec<1>, 139 SDTCisSameNumEltsAs<0, 1>, 140 SDTCisSameAs<1, 2>, 141 SDTCisVT<3, OtherVT>, 142 SDTCisSameAs<0, 4>, 143 SDTCisVT<5, XLenVT>]>>; 144 145def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 146 SDTypeProfile<1, 4, [SDTCisVec<0>, 147 SDTCisSameAs<0, 1>, 148 SDTCisVT<2, XLenVT>, 149 SDTCVecEltisVT<3, i1>, 150 SDTCisSameNumEltsAs<0, 3>, 151 SDTCisVT<4, XLenVT>]>>; 152def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 153 SDTypeProfile<1, 4, [SDTCisVec<0>, 154 SDTCisSameAs<0, 1>, 155 SDTCisInt<2>, 156 SDTCisSameNumEltsAs<0, 2>, 157 SDTCisSameSizeAs<0, 2>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCVecEltisVT<2, i16>, 166 SDTCisSameNumEltsAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170 171def SDT_RISCVSelect_VL : SDTypeProfile<1, 4, [ 172 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>, 173 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, XLenVT> 174]>; 175 176def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", SDT_RISCVSelect_VL>; 177def riscv_vp_merge_vl : SDNode<"RISCVISD::VP_MERGE_VL", SDT_RISCVSelect_VL>; 178 179def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, 180 SDTCisVT<1, XLenVT>]>; 181def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; 182def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; 183 184def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 185 SDTCisSameAs<0, 2>, 186 SDTCVecEltisVT<0, i1>, 187 SDTCisVT<3, XLenVT>]>; 188def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 189def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 190def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 191 192def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 193 194def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 195 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 196 197def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 198 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 199 SDTCisVec<1>, SDTCisInt<1>, 200 SDTCVecEltisVT<2, i1>, 201 SDTCisSameNumEltsAs<1, 2>, 202 SDTCisVT<3, XLenVT>]>>; 203 204def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 205 SDTCisSameNumEltsAs<0, 1>, 206 SDTCisSameNumEltsAs<1, 2>, 207 SDTCVecEltisVT<2, i1>, 208 SDTCisVT<3, XLenVT>]>; 209def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 210def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 211 212def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 213 SDTypeProfile<1, 3, [SDTCisVec<0>, 214 SDTCisSameNumEltsAs<0, 1>, 215 SDTCisSameNumEltsAs<0, 2>, 216 SDTCVecEltisVT<2, i1>, 217 SDTCisVT<3, XLenVT>]>>; 218 219def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 220 SDTCisSameNumEltsAs<0, 1>, 221 SDTCisSameAs<1, 2>, 222 SDTCisSameNumEltsAs<1, 3>, 223 SDTCVecEltisVT<3, i1>, 224 SDTCisVT<4, XLenVT>]>; 225def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 226def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 227def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>; 228def riscv_vwadd_vl : SDNode<"RISCVISD::VWADD_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 229def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 230def riscv_vwsub_vl : SDNode<"RISCVISD::VWSUB_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 231def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 232 233def SDT_RISCVVWBinOpW_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 234 SDTCisSameAs<0, 1>, 235 SDTCisSameNumEltsAs<1, 2>, 236 SDTCisOpSmallerThanOp<2, 1>, 237 SDTCisSameNumEltsAs<1, 3>, 238 SDTCVecEltisVT<3, i1>, 239 SDTCisVT<4, XLenVT>]>; 240def riscv_vwadd_w_vl : SDNode<"RISCVISD::VWADD_W_VL", SDT_RISCVVWBinOpW_VL>; 241def riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWBinOpW_VL>; 242def riscv_vwsub_w_vl : SDNode<"RISCVISD::VWSUB_W_VL", SDT_RISCVVWBinOpW_VL>; 243def riscv_vwsubu_w_vl : SDNode<"RISCVISD::VWSUBU_W_VL", SDT_RISCVVWBinOpW_VL>; 244 245def SDTRVVVecReduce : SDTypeProfile<1, 5, [ 246 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 247 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT> 248]>; 249 250def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 251 (riscv_mul_vl node:$A, node:$B, node:$C, 252 node:$D), [{ 253 return N->hasOneUse(); 254}]>; 255 256def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 257 (riscv_vwmul_vl node:$A, node:$B, node:$C, 258 node:$D), [{ 259 return N->hasOneUse(); 260}]>; 261 262def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 263 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 264 node:$D), [{ 265 return N->hasOneUse(); 266}]>; 267 268def riscv_vwmulsu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 269 (riscv_vwmulsu_vl node:$A, node:$B, node:$C, 270 node:$D), [{ 271 return N->hasOneUse(); 272}]>; 273 274def riscv_sext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 275 (riscv_sext_vl node:$A, node:$B, node:$C), [{ 276 return N->hasOneUse(); 277}]>; 278 279def riscv_zext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 280 (riscv_zext_vl node:$A, node:$B, node:$C), [{ 281 return N->hasOneUse(); 282}]>; 283 284def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 285 (riscv_fpextend_vl node:$A, node:$B, node:$C), [{ 286 return N->hasOneUse(); 287}]>; 288 289foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 290 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 291 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 292 293// Give explicit Complexity to prefer simm5/uimm5. 294def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; 295def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 2>; 296def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>; 297def SplatPat_simm5_plus1 298 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>; 299def SplatPat_simm5_plus1_nonzero 300 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>; 301 302// Ignore the vl operand. 303def SplatFPOp : PatFrag<(ops node:$op), 304 (riscv_vfmv_v_f_vl undef, node:$op, srcvalue)>; 305 306def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 307def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 308def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 309def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 310 311multiclass VPatBinaryVL_V<SDNode vop, 312 string instruction_name, 313 string suffix, 314 ValueType result_type, 315 ValueType op1_type, 316 ValueType op2_type, 317 ValueType mask_type, 318 int sew, 319 LMULInfo vlmul, 320 VReg op1_reg_class, 321 VReg op2_reg_class> { 322 def : Pat<(result_type (vop 323 (op1_type op1_reg_class:$rs1), 324 (op2_type op2_reg_class:$rs2), 325 (mask_type V0), 326 VLOpFrag)), 327 (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_MASK") 328 (result_type (IMPLICIT_DEF)), 329 op1_reg_class:$rs1, 330 op2_reg_class:$rs2, 331 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 332} 333 334multiclass VPatBinaryVL_XI<SDNode vop, 335 string instruction_name, 336 string suffix, 337 ValueType result_type, 338 ValueType vop1_type, 339 ValueType vop2_type, 340 ValueType mask_type, 341 int sew, 342 LMULInfo vlmul, 343 VReg vop_reg_class, 344 ComplexPattern SplatPatKind, 345 DAGOperand xop_kind> { 346 def : Pat<(result_type (vop 347 (vop1_type vop_reg_class:$rs1), 348 (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))), 349 (mask_type V0), 350 VLOpFrag)), 351 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 352 (result_type (IMPLICIT_DEF)), 353 vop_reg_class:$rs1, 354 xop_kind:$rs2, 355 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 356} 357 358multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 359 foreach vti = AllIntegerVectors in { 360 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 361 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 362 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 363 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 364 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 365 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 366 } 367} 368 369multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 370 Operand ImmType = simm5> 371 : VPatBinaryVL_VV_VX<vop, instruction_name> { 372 foreach vti = AllIntegerVectors in { 373 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 374 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 375 vti.Log2SEW, vti.LMul, vti.RegClass, 376 !cast<ComplexPattern>(SplatPat#_#ImmType), 377 ImmType>; 378 } 379} 380 381multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 382 foreach VtiToWti = AllWidenableIntVectors in { 383 defvar vti = VtiToWti.Vti; 384 defvar wti = VtiToWti.Wti; 385 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 386 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 387 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 388 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 389 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 390 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 391 } 392} 393multiclass VPatBinaryWVL_VV_VX_WV_WX<SDNode vop, SDNode vop_w, 394 string instruction_name> 395 : VPatBinaryWVL_VV_VX<vop, instruction_name> { 396 foreach VtiToWti = AllWidenableIntVectors in { 397 defvar vti = VtiToWti.Vti; 398 defvar wti = VtiToWti.Wti; 399 defm : VPatBinaryVL_V<vop_w, instruction_name, "WV", 400 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 401 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass>; 402 defm : VPatBinaryVL_XI<vop_w, instruction_name, "WX", 403 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 404 vti.Log2SEW, vti.LMul, wti.RegClass, SplatPat, GPR>; 405 } 406} 407 408multiclass VPatBinaryVL_VF<SDNode vop, 409 string instruction_name, 410 ValueType result_type, 411 ValueType vop_type, 412 ValueType mask_type, 413 int sew, 414 LMULInfo vlmul, 415 VReg vop_reg_class, 416 RegisterClass scalar_reg_class> { 417 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 418 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 419 (mask_type V0), 420 VLOpFrag)), 421 (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_MASK") 422 (result_type (IMPLICIT_DEF)), 423 vop_reg_class:$rs1, 424 scalar_reg_class:$rs2, 425 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 426} 427 428multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 429 foreach vti = AllFloatVectors in { 430 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 431 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 432 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 433 defm : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 434 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 435 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 436 } 437} 438 439multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 440 foreach fvti = AllFloatVectors in { 441 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 442 fvti.RegClass:$rs1, 443 (fvti.Mask V0), 444 VLOpFrag)), 445 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 446 (fvti.Vector (IMPLICIT_DEF)), 447 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 448 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 449 } 450} 451 452multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 453 CondCode cc> { 454 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 455 vti.RegClass:$rs2, cc, 456 (vti.Mask V0), 457 VLOpFrag)), 458 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 459 (vti.Mask (IMPLICIT_DEF)), 460 vti.RegClass:$rs1, 461 vti.RegClass:$rs2, 462 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 463} 464 465// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 466multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 467 CondCode cc, CondCode invcc> 468 : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 469 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 470 vti.RegClass:$rs1, invcc, 471 (vti.Mask V0), 472 VLOpFrag)), 473 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 474 (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 475 vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 476} 477 478multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 479 CondCode cc, CondCode invcc> { 480 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); 481 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 482 (SplatPat (XLenVT GPR:$rs2)), cc, 483 (vti.Mask V0), 484 VLOpFrag)), 485 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 486 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 487 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 488 (vti.Vector vti.RegClass:$rs1), invcc, 489 (vti.Mask V0), 490 VLOpFrag)), 491 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 492 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 493} 494 495multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 496 CondCode cc, CondCode invcc> { 497 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 498 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 499 (SplatPat_simm5 simm5:$rs2), cc, 500 (vti.Mask V0), 501 VLOpFrag)), 502 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 503 XLenVT:$rs2, (vti.Mask V0), GPR:$vl, 504 vti.Log2SEW)>; 505 506 // FIXME: Can do some canonicalization to remove these patterns. 507 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 508 (vti.Vector vti.RegClass:$rs1), invcc, 509 (vti.Mask V0), 510 VLOpFrag)), 511 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 512 simm5:$rs2, (vti.Mask V0), GPR:$vl, 513 vti.Log2SEW)>; 514} 515 516multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti, 517 string instruction_name, 518 CondCode cc, CondCode invcc, 519 ComplexPattern splatpat_kind> { 520 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 521 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 522 (splatpat_kind simm5:$rs2), cc, 523 (vti.Mask V0), 524 VLOpFrag)), 525 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 526 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 527 vti.Log2SEW)>; 528 529 // FIXME: Can do some canonicalization to remove these patterns. 530 def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), 531 (vti.Vector vti.RegClass:$rs1), invcc, 532 (vti.Mask V0), 533 VLOpFrag)), 534 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 535 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 536 vti.Log2SEW)>; 537} 538 539multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 540 string inst_name, 541 string swapped_op_inst_name> { 542 foreach fvti = AllFloatVectors in { 543 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 544 fvti.RegClass:$rs2, 545 cc, 546 (fvti.Mask V0), 547 VLOpFrag)), 548 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX#"_MASK") 549 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 550 fvti.RegClass:$rs2, (fvti.Mask V0), 551 GPR:$vl, fvti.Log2SEW)>; 552 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 553 (SplatFPOp fvti.ScalarRegClass:$rs2), 554 cc, 555 (fvti.Mask V0), 556 VLOpFrag)), 557 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 558 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 559 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 560 GPR:$vl, fvti.Log2SEW)>; 561 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 562 (fvti.Vector fvti.RegClass:$rs1), 563 cc, 564 (fvti.Mask V0), 565 VLOpFrag)), 566 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 567 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 568 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 569 GPR:$vl, fvti.Log2SEW)>; 570 } 571} 572 573multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 574 list <VTypeInfoToFraction> fraction_list> { 575 foreach vtiTofti = fraction_list in { 576 defvar vti = vtiTofti.Vti; 577 defvar fti = vtiTofti.Fti; 578 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 579 (fti.Mask V0), VLOpFrag)), 580 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK") 581 (vti.Vector (IMPLICIT_DEF)), 582 fti.RegClass:$rs2, 583 (fti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 584 } 585} 586 587multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 588 foreach fvti = AllFloatVectors in { 589 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 590 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 591 (fvti.Mask V0), 592 VLOpFrag)), 593 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 594 (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 595 (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 596 } 597} 598 599multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 600 foreach fvti = AllFloatVectors in { 601 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 602 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 603 (ivti.Mask V0), 604 VLOpFrag)), 605 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 606 (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 607 (ivti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 608 } 609} 610 611multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 612 foreach fvtiToFWti = AllWidenableFloatVectors in { 613 defvar fvti = fvtiToFWti.Vti; 614 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 615 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 616 (fvti.Mask V0), 617 VLOpFrag)), 618 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 619 (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 620 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 621 } 622} 623 624multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 625 foreach vtiToWti = AllWidenableIntToFloatVectors in { 626 defvar ivti = vtiToWti.Vti; 627 defvar fwti = vtiToWti.Wti; 628 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 629 (ivti.Mask V0), 630 VLOpFrag)), 631 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 632 (fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 633 (ivti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 634 } 635} 636 637multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 638 foreach vtiToWti = AllWidenableIntToFloatVectors in { 639 defvar vti = vtiToWti.Vti; 640 defvar fwti = vtiToWti.Wti; 641 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 642 (fwti.Mask V0), 643 VLOpFrag)), 644 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK") 645 (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 646 (fwti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 647 } 648} 649 650multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 651 foreach fvtiToFWti = AllWidenableFloatVectors in { 652 defvar fvti = fvtiToFWti.Vti; 653 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 654 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 655 (iwti.Mask V0), 656 VLOpFrag)), 657 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 658 (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1, 659 (iwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 660 } 661} 662 663multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 664 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 665 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 666 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 667 (vti.Mask true_mask), 668 VLOpFrag)), 669 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 670 (vti_m1.Vector VR:$merge), 671 (vti.Vector vti.RegClass:$rs1), 672 (vti_m1.Vector VR:$rs2), 673 GPR:$vl, vti.Log2SEW)>; 674 675 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 676 (vti.Mask V0), VLOpFrag)), 677 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 678 (vti_m1.Vector VR:$merge), 679 (vti.Vector vti.RegClass:$rs1), 680 (vti_m1.Vector VR:$rs2), 681 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 682 } 683} 684 685multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> { 686 foreach vtiToWti = AllWidenableIntVectors in { 687 defvar vti = vtiToWti.Vti; 688 defvar wti = vtiToWti.Wti; 689 def : Pat< 690 (vti.Vector 691 (riscv_trunc_vector_vl 692 (op (wti.Vector wti.RegClass:$rs2), 693 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))), 694 (vti.Mask true_mask), 695 VLOpFrag)), 696 (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX) 697 wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 698 def : Pat< 699 (vti.Vector 700 (riscv_trunc_vector_vl 701 (op (wti.Vector wti.RegClass:$rs2), 702 (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1))))), 703 (vti.Mask true_mask), 704 VLOpFrag)), 705 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 706 wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 707 } 708} 709 710multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> { 711 defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>; 712 defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>; 713 foreach vtiToWti = AllWidenableIntVectors in { 714 defvar vti = vtiToWti.Vti; 715 defvar wti = vtiToWti.Wti; 716 def : Pat< 717 (vti.Vector 718 (riscv_trunc_vector_vl 719 (op (wti.Vector wti.RegClass:$rs2), 720 (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask), 721 VLOpFrag)), 722 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 723 wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW)>; 724 } 725} 726 727multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 728 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 729 defvar vti = vtiToWti.Vti; 730 defvar wti = vtiToWti.Wti; 731 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 732 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 733 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 734 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 735 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 736 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 737 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 738 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 739 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 740 VR:$rs2, (vti.Mask V0), VLOpFrag)), 741 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 742 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 743 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 744 } 745} 746 747multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 748 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 749 defvar vti = vtiToWti.Vti; 750 defvar wti = vtiToWti.Wti; 751 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 752 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 753 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 754 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 755 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 756 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 757 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 758 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 759 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 760 VR:$rs2, (vti.Mask V0), VLOpFrag)), 761 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 762 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 763 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 764 } 765} 766 767multiclass VPatWidenBinaryFPVL_VV_VF<SDNode op, PatFrags extop, string instruction_name> { 768 foreach fvtiToFWti = AllWidenableFloatVectors in { 769 defvar fvti = fvtiToFWti.Vti; 770 defvar fwti = fvtiToFWti.Wti; 771 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 772 (fvti.Mask true_mask), VLOpFrag)), 773 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 774 (fvti.Mask true_mask), VLOpFrag)), 775 (fwti.Mask true_mask), VLOpFrag)), 776 (!cast<Instruction>(instruction_name#"_VV_"#fvti.LMul.MX) 777 fvti.RegClass:$rs2, fvti.RegClass:$rs1, 778 GPR:$vl, fvti.Log2SEW)>; 779 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 780 (fvti.Mask true_mask), VLOpFrag)), 781 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 782 (fvti.Mask true_mask), VLOpFrag)), 783 (fwti.Mask true_mask), VLOpFrag)), 784 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 785 fvti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 786 GPR:$vl, fvti.Log2SEW)>; 787 } 788} 789 790multiclass VPatWidenBinaryFPVL_WV_WF<SDNode op, PatFrags extop, string instruction_name> { 791 foreach fvtiToFWti = AllWidenableFloatVectors in { 792 defvar fvti = fvtiToFWti.Vti; 793 defvar fwti = fvtiToFWti.Wti; 794 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 795 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 796 (fvti.Mask true_mask), VLOpFrag)), 797 (fwti.Mask true_mask), VLOpFrag)), 798 (!cast<Instruction>(instruction_name#"_WV_"#fvti.LMul.MX) 799 fwti.RegClass:$rs2, fvti.RegClass:$rs1, 800 GPR:$vl, fvti.Log2SEW)>; 801 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 802 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 803 (fvti.Mask true_mask), VLOpFrag)), 804 (fwti.Mask true_mask), VLOpFrag)), 805 (!cast<Instruction>(instruction_name#"_W"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 806 fwti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 807 GPR:$vl, fvti.Log2SEW)>; 808 } 809} 810 811multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> { 812 defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>; 813 defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>; 814} 815 816multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> { 817 foreach vtiToWti = AllWidenableIntVectors in { 818 defvar vti = vtiToWti.Vti; 819 defvar wti = vtiToWti.Wti; 820 def : Pat< 821 (vti.Vector 822 (riscv_trunc_vector_vl 823 (op (wti.Vector wti.RegClass:$rs2), 824 (wti.Vector (extop (vti.Vector (SplatPat GPR:$rs1)), 825 (vti.Mask true_mask), VLOpFrag)), 826 (wti.Mask true_mask), VLOpFrag), 827 (vti.Mask true_mask), VLOpFrag)), 828 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 829 wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 830 } 831} 832 833multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> { 834 foreach vti = AllIntegerVectors in { 835 defvar suffix = vti.LMul.MX; 836 // NOTE: We choose VMADD because it has the most commuting freedom. So it 837 // works best with how TwoAddressInstructionPass tries commuting. 838 def : Pat<(vti.Vector 839 (op vti.RegClass:$rs2, 840 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 841 vti.RegClass:$rd, 842 (vti.Mask true_mask), VLOpFrag), 843 (vti.Mask true_mask), VLOpFrag)), 844 (!cast<Instruction>(instruction_name#"_VV_"# suffix) 845 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 846 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 847 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 848 // commutable. 849 def : Pat<(vti.Vector 850 (op vti.RegClass:$rs2, 851 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 852 vti.RegClass:$rd, 853 (vti.Mask true_mask), VLOpFrag), 854 (vti.Mask true_mask), VLOpFrag)), 855 (!cast<Instruction>(instruction_name#"_VX_" # suffix) 856 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 857 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 858 } 859} 860 861multiclass VPatWidenMultiplyAddVL_VV_VX<PatFrag op1, string instruction_name> { 862 foreach vtiTowti = AllWidenableIntVectors in { 863 defvar vti = vtiTowti.Vti; 864 defvar wti = vtiTowti.Wti; 865 def : Pat<(wti.Vector 866 (riscv_add_vl wti.RegClass:$rd, 867 (op1 vti.RegClass:$rs1, 868 (vti.Vector vti.RegClass:$rs2), 869 (vti.Mask true_mask), VLOpFrag), 870 (vti.Mask true_mask), VLOpFrag)), 871 (!cast<Instruction>(instruction_name#"_VV_" # vti.LMul.MX) 872 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 873 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 874 def : Pat<(wti.Vector 875 (riscv_add_vl wti.RegClass:$rd, 876 (op1 (SplatPat XLenVT:$rs1), 877 (vti.Vector vti.RegClass:$rs2), 878 (vti.Mask true_mask), VLOpFrag), 879 (vti.Mask true_mask), VLOpFrag)), 880 (!cast<Instruction>(instruction_name#"_VX_" # vti.LMul.MX) 881 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 882 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 883 } 884} 885 886multiclass VPatNarrowShiftSplat_WX_WI<SDNode op, string instruction_name> { 887 foreach vtiTowti = AllWidenableIntVectors in { 888 defvar vti = vtiTowti.Vti; 889 defvar wti = vtiTowti.Wti; 890 def : Pat<(vti.Vector (riscv_trunc_vector_vl 891 (wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 892 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 893 (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) 894 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 895 def : Pat<(vti.Vector (riscv_trunc_vector_vl 896 (wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 897 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 898 (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) 899 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 900 } 901} 902 903multiclass VPatWidenFPMulAccVL_VV_VF<string instruction_name> { 904 foreach vtiToWti = AllWidenableFloatVectors in { 905 defvar vti = vtiToWti.Vti; 906 defvar wti = vtiToWti.Wti; 907 def : Pat<(riscv_fma_vl 908 (wti.Vector (riscv_fpextend_vl_oneuse 909 (vti.Vector vti.RegClass:$rs1), 910 (vti.Mask true_mask), VLOpFrag)), 911 (wti.Vector (riscv_fpextend_vl_oneuse 912 (vti.Vector vti.RegClass:$rs2), 913 (vti.Mask true_mask), VLOpFrag)), 914 (wti.Vector wti.RegClass:$rd), (vti.Mask true_mask), 915 VLOpFrag), 916 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 917 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 918 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 919 def : Pat<(riscv_fma_vl 920 (wti.Vector (riscv_fpextend_vl_oneuse 921 (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 922 (vti.Mask true_mask), VLOpFrag)), 923 (wti.Vector (riscv_fpextend_vl_oneuse 924 (vti.Vector vti.RegClass:$rs2), 925 (vti.Mask true_mask), VLOpFrag)), 926 (wti.Vector wti.RegClass:$rd), (vti.Mask true_mask), 927 VLOpFrag), 928 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) 929 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 930 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 931 } 932} 933 934multiclass VPatWidenFPNegMulAccVL_VV_VF<string instruction_name> { 935 foreach vtiToWti = AllWidenableFloatVectors in { 936 defvar vti = vtiToWti.Vti; 937 defvar wti = vtiToWti.Wti; 938 def : Pat<(riscv_fma_vl 939 (riscv_fneg_vl 940 (wti.Vector (riscv_fpextend_vl_oneuse 941 (vti.Vector vti.RegClass:$rs1), 942 (vti.Mask true_mask), VLOpFrag)), 943 (wti.Mask true_mask), VLOpFrag), 944 (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), 945 (vti.Mask true_mask), VLOpFrag), 946 (riscv_fneg_vl wti.RegClass:$rd, (wti.Mask true_mask), 947 VLOpFrag), 948 (vti.Mask true_mask), VLOpFrag), 949 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 950 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 951 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 952 def : Pat<(riscv_fma_vl 953 (riscv_fpextend_vl_oneuse 954 (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 955 (vti.Mask true_mask), VLOpFrag), 956 (riscv_fneg_vl 957 (wti.Vector (riscv_fpextend_vl_oneuse 958 (vti.Vector vti.RegClass:$rs2), 959 (vti.Mask true_mask), VLOpFrag)), 960 (vti.Mask true_mask), VLOpFrag), 961 (riscv_fneg_vl wti.RegClass:$rd, (wti.Mask true_mask), 962 VLOpFrag), 963 (vti.Mask true_mask), VLOpFrag), 964 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) 965 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 966 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 967 def : Pat<(riscv_fma_vl 968 (riscv_fneg_vl 969 (wti.Vector (riscv_fpextend_vl_oneuse 970 (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 971 (vti.Mask true_mask), VLOpFrag)), 972 (vti.Mask true_mask), VLOpFrag), 973 (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), 974 (vti.Mask true_mask), VLOpFrag), 975 (riscv_fneg_vl wti.RegClass:$rd, (wti.Mask true_mask), 976 VLOpFrag), 977 (vti.Mask true_mask), VLOpFrag), 978 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) 979 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 980 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 981 } 982} 983 984multiclass VPatWidenFPMulSacVL_VV_VF<string instruction_name> { 985 foreach vtiToWti = AllWidenableFloatVectors in { 986 defvar vti = vtiToWti.Vti; 987 defvar wti = vtiToWti.Wti; 988 def : Pat<(riscv_fma_vl 989 (wti.Vector (riscv_fpextend_vl_oneuse 990 (vti.Vector vti.RegClass:$rs1), 991 (vti.Mask true_mask), VLOpFrag)), 992 (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), 993 (vti.Mask true_mask), VLOpFrag), 994 (riscv_fneg_vl wti.RegClass:$rd, (vti.Mask true_mask), 995 VLOpFrag), 996 (vti.Mask true_mask), VLOpFrag), 997 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 998 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 999 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1000 def : Pat<(riscv_fma_vl 1001 (wti.Vector (riscv_fpextend_vl_oneuse 1002 (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 1003 (vti.Mask true_mask), VLOpFrag)), 1004 (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), 1005 (vti.Mask true_mask), VLOpFrag), 1006 (riscv_fneg_vl wti.RegClass:$rd, (vti.Mask true_mask), 1007 VLOpFrag), 1008 (vti.Mask true_mask), VLOpFrag), 1009 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1010 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1011 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1012 } 1013} 1014 1015multiclass VPatWidenFPNegMulSacVL_VV_VF<string instruction_name> { 1016 foreach vtiToWti = AllWidenableFloatVectors in { 1017 defvar vti = vtiToWti.Vti; 1018 defvar wti = vtiToWti.Wti; 1019 def : Pat<(riscv_fma_vl 1020 (riscv_fneg_vl 1021 (wti.Vector (riscv_fpextend_vl_oneuse 1022 (vti.Vector vti.RegClass:$rs1), 1023 (vti.Mask true_mask), VLOpFrag)), 1024 (vti.Mask true_mask), VLOpFrag), 1025 (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), 1026 (vti.Mask true_mask), VLOpFrag), 1027 wti.RegClass:$rd, (wti.Mask true_mask), VLOpFrag), 1028 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 1029 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1030 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1031 def : Pat<(riscv_fma_vl 1032 (wti.Vector (riscv_fpextend_vl_oneuse 1033 (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 1034 (vti.Mask true_mask), VLOpFrag)), 1035 (riscv_fneg_vl 1036 (wti.Vector (riscv_fpextend_vl_oneuse 1037 (vti.Vector vti.RegClass:$rs2), 1038 (vti.Mask true_mask), VLOpFrag)), 1039 (wti.Mask true_mask), VLOpFrag), 1040 wti.RegClass:$rd, (wti.Mask true_mask), VLOpFrag), 1041 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1042 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1043 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1044 def : Pat<(riscv_fma_vl 1045 (riscv_fneg_vl 1046 (wti.Vector (riscv_fpextend_vl_oneuse 1047 (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), 1048 (vti.Mask true_mask), VLOpFrag)), 1049 (vti.Mask true_mask), VLOpFrag), 1050 (riscv_fpextend_vl_oneuse (vti.Vector vti.RegClass:$rs2), 1051 (vti.Mask true_mask), VLOpFrag), 1052 wti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag), 1053 (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1054 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1055 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1056 } 1057} 1058 1059//===----------------------------------------------------------------------===// 1060// Patterns. 1061//===----------------------------------------------------------------------===// 1062 1063let Predicates = [HasVInstructions] in { 1064 1065// 12.1. Vector Single-Width Integer Add and Subtract 1066defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 1067defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 1068// Handle VRSUB specially since it's the only integer binary op with reversed 1069// pattern operands 1070foreach vti = AllIntegerVectors in { 1071 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 1072 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 1073 VLOpFrag), 1074 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 1075 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 1076 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1077 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 1078 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 1079 VLOpFrag), 1080 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 1081 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 1082 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1083} 1084 1085// 12.2. Vector Widening Integer Add/Subtract 1086defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwadd_vl, riscv_vwadd_w_vl, "PseudoVWADD">; 1087defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWADDU">; 1088defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">; 1089defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">; 1090 1091// 12.3. Vector Integer Extension 1092defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 1093 AllFractionableVF2IntVectors>; 1094defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 1095 AllFractionableVF2IntVectors>; 1096defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 1097 AllFractionableVF4IntVectors>; 1098defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 1099 AllFractionableVF4IntVectors>; 1100defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 1101 AllFractionableVF8IntVectors>; 1102defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 1103 AllFractionableVF8IntVectors>; 1104 1105// 12.5. Vector Bitwise Logical Instructions 1106defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 1107defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 1108defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 1109 1110// 12.6. Vector Single-Width Bit Shift Instructions 1111defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 1112defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 1113defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 1114 1115foreach vti = AllIntegerVectors in { 1116 // Emit shift by 1 as an add since it might be faster. 1117 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 1118 (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)), 1119 (vti.Mask true_mask), 1120 VLOpFrag), 1121 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 1122 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1123} 1124 1125// 12.7. Vector Narrowing Integer Right Shift Instructions 1126defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">; 1127defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">; 1128 1129defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">; 1130defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">; 1131defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">; 1132defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">; 1133defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">; 1134defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">; 1135 1136foreach vtiTowti = AllWidenableIntVectors in { 1137 defvar vti = vtiTowti.Vti; 1138 defvar wti = vtiTowti.Wti; 1139 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 1140 (vti.Mask V0), 1141 VLOpFrag)), 1142 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX#"_MASK") 1143 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, X0, 1144 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1145} 1146 1147// 12.8. Vector Integer Comparison Instructions 1148foreach vti = AllIntegerVectors in { 1149 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 1150 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 1151 1152 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 1153 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 1154 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1155 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1156 1157 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 1158 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 1159 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 1160 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 1161 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1162 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1163 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 1164 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 1165 // There is no VMSGE(U)_VX instruction 1166 1167 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 1168 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 1169 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 1170 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 1171 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 1172 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 1173 1174 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT, 1175 SplatPat_simm5_plus1_nonzero>; 1176 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT, 1177 SplatPat_simm5_plus1_nonzero>; 1178 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE, 1179 SplatPat_simm5_plus1>; 1180 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE, 1181 SplatPat_simm5_plus1_nonzero>; 1182} // foreach vti = AllIntegerVectors 1183 1184// 12.9. Vector Integer Min/Max Instructions 1185defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 1186defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 1187defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 1188defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 1189 1190// 12.10. Vector Single-Width Integer Multiply Instructions 1191defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 1192defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 1193defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 1194 1195// 12.11. Vector Integer Divide Instructions 1196defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 1197defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 1198defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 1199defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 1200 1201// 12.12. Vector Widening Integer Multiply Instructions 1202defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 1203defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 1204defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; 1205 1206// 12.13 Vector Single-Width Integer Multiply-Add Instructions 1207defm : VPatMultiplyAddVL_VV_VX<riscv_add_vl, "PseudoVMADD">; 1208defm : VPatMultiplyAddVL_VV_VX<riscv_sub_vl, "PseudoVNMSUB">; 1209 1210// 12.14. Vector Widening Integer Multiply-Add Instructions 1211defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmul_vl_oneuse, "PseudoVWMACC">; 1212defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulu_vl_oneuse, "PseudoVWMACCU">; 1213defm : VPatWidenMultiplyAddVL_VV_VX<riscv_vwmulsu_vl_oneuse, "PseudoVWMACCSU">; 1214foreach vtiTowti = AllWidenableIntVectors in { 1215 defvar vti = vtiTowti.Vti; 1216 defvar wti = vtiTowti.Wti; 1217 def : Pat<(wti.Vector 1218 (riscv_add_vl wti.RegClass:$rd, 1219 (riscv_vwmulsu_vl_oneuse (vti.Vector vti.RegClass:$rs1), 1220 (SplatPat XLenVT:$rs2), 1221 (vti.Mask true_mask), VLOpFrag), 1222 (vti.Mask true_mask), VLOpFrag)), 1223 (!cast<Instruction>("PseudoVWMACCUS_VX_" # vti.LMul.MX) 1224 wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1, 1225 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1226} 1227 1228// 12.15. Vector Integer Merge Instructions 1229foreach vti = AllIntegerVectors in { 1230 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1231 vti.RegClass:$rs1, 1232 vti.RegClass:$rs2, 1233 VLOpFrag)), 1234 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 1235 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 1236 GPR:$vl, vti.Log2SEW)>; 1237 1238 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1239 (SplatPat XLenVT:$rs1), 1240 vti.RegClass:$rs2, 1241 VLOpFrag)), 1242 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 1243 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1244 1245 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1246 (SplatPat_simm5 simm5:$rs1), 1247 vti.RegClass:$rs2, 1248 VLOpFrag)), 1249 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 1250 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1251 1252 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1253 vti.RegClass:$rs1, 1254 vti.RegClass:$rs2, 1255 VLOpFrag)), 1256 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX#"_TU") 1257 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1, 1258 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1259 1260 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1261 (SplatPat XLenVT:$rs1), 1262 vti.RegClass:$rs2, 1263 VLOpFrag)), 1264 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX#"_TU") 1265 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1, 1266 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1267 1268 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1269 (SplatPat_simm5 simm5:$rs1), 1270 vti.RegClass:$rs2, 1271 VLOpFrag)), 1272 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU") 1273 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, 1274 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1275} 1276 1277// 12.16. Vector Integer Move Instructions 1278foreach vti = AllIntegerVectors in { 1279 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)), 1280 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 1281 $rs2, GPR:$vl, vti.Log2SEW)>; 1282 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, GPR:$rs2, VLOpFrag)), 1283 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX#"_TU") 1284 $passthru, $rs2, GPR:$vl, vti.Log2SEW)>; 1285 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 1286 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat XLenVT:$imm5), 1287 VLOpFrag)), 1288 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 1289 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1290 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, (ImmPat XLenVT:$imm5), 1291 VLOpFrag)), 1292 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX#"_TU") 1293 $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1294} 1295 1296// 12.1. Vector Single-Width Saturating Add and Subtract 1297defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 1298defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 1299defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 1300defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 1301 1302} // Predicates = [HasVInstructions] 1303 1304// 15.1. Vector Single-Width Integer Reduction Instructions 1305let Predicates = [HasVInstructions] in { 1306defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 1307defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 1308defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 1309defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 1310defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 1311defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 1312defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 1313defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 1314 1315// 15.2. Vector Widening Integer Reduction Instructions 1316defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1317defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1318defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1319defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1320defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1321} // Predicates = [HasVInstructions] 1322 1323// 15.3. Vector Single-Width Floating-Point Reduction Instructions 1324let Predicates = [HasVInstructionsAnyF] in { 1325defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 1326defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>; 1327defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 1328defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 1329 1330// 15.4. Vector Widening Floating-Point Reduction Instructions 1331defm : VPatWidenReductionVL<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1332defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_SEQ_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1333defm : VPatWidenReductionVL<rvv_vecreduce_FADD_vl, fpext_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1334defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1335} // Predicates = [HasVInstructionsAnyF] 1336 1337let Predicates = [HasVInstructionsAnyF] in { 1338 1339// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 1340defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 1341defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 1342defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 1343 1344// 14.3. Vector Widening Floating-Point Add/Subtract Instructions 1345defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fadd_vl, "PseudoVFWADD">; 1346defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fsub_vl, "PseudoVFWSUB">; 1347 1348// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 1349defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 1350defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 1351defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 1352 1353// 14.5. Vector Widening Floating-Point Multiply Instructions 1354defm : VPatWidenBinaryFPVL_VV_VF<riscv_fmul_vl, riscv_fpextend_vl_oneuse, "PseudoVFWMUL">; 1355 1356// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 1357foreach vti = AllFloatVectors in { 1358 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 1359 // works best with how TwoAddressInstructionPass tries commuting. 1360 defvar suffix = vti.LMul.MX; 1361 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1362 vti.RegClass:$rs2, (vti.Mask true_mask), 1363 VLOpFrag)), 1364 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 1365 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1366 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1367 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1368 vti.RegClass:$rs2, (vti.Mask V0), 1369 VLOpFrag)), 1370 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix #"_MASK") 1371 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1372 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 1373 1374 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1375 (riscv_fneg_vl vti.RegClass:$rs2, 1376 (vti.Mask true_mask), 1377 VLOpFrag), 1378 (vti.Mask true_mask), 1379 VLOpFrag)), 1380 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 1381 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1382 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1383 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1384 (riscv_fneg_vl vti.RegClass:$rs2, 1385 (vti.Mask srcvalue), 1386 VLOpFrag), 1387 (vti.Mask V0), 1388 VLOpFrag)), 1389 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix #"_MASK") 1390 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1391 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1392 1393 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1394 (vti.Mask srcvalue), 1395 VLOpFrag), 1396 vti.RegClass:$rd, 1397 (riscv_fneg_vl vti.RegClass:$rs2, 1398 (vti.Mask srcvalue), 1399 VLOpFrag), 1400 (vti.Mask true_mask), 1401 VLOpFrag)), 1402 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 1403 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1404 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1405 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1406 (vti.Mask srcvalue), 1407 VLOpFrag), 1408 vti.RegClass:$rd, 1409 (riscv_fneg_vl vti.RegClass:$rs2, 1410 (vti.Mask srcvalue), 1411 VLOpFrag), 1412 (vti.Mask V0), 1413 VLOpFrag)), 1414 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix #"_MASK") 1415 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1416 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1417 1418 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1419 (vti.Mask srcvalue), 1420 VLOpFrag), 1421 vti.RegClass:$rd, vti.RegClass:$rs2, 1422 (vti.Mask true_mask), 1423 VLOpFrag)), 1424 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 1425 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1426 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1427 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1428 (vti.Mask srcvalue), 1429 VLOpFrag), 1430 vti.RegClass:$rd, vti.RegClass:$rs2, 1431 (vti.Mask V0), 1432 VLOpFrag)), 1433 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix #"_MASK") 1434 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1435 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1436 1437 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 1438 // commutable. 1439 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1440 vti.RegClass:$rd, vti.RegClass:$rs2, 1441 (vti.Mask true_mask), 1442 VLOpFrag)), 1443 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1444 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1445 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1446 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1447 vti.RegClass:$rd, vti.RegClass:$rs2, 1448 (vti.Mask V0), 1449 VLOpFrag)), 1450 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1451 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1452 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 1453 1454 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1455 vti.RegClass:$rd, 1456 (riscv_fneg_vl vti.RegClass:$rs2, 1457 (vti.Mask srcvalue), 1458 VLOpFrag), 1459 (vti.Mask true_mask), 1460 VLOpFrag)), 1461 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1462 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1463 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1464 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1465 vti.RegClass:$rd, 1466 (riscv_fneg_vl vti.RegClass:$rs2, 1467 (vti.Mask srcvalue), 1468 VLOpFrag), 1469 (vti.Mask V0), 1470 VLOpFrag)), 1471 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1472 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1473 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1474 1475 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1476 (riscv_fneg_vl vti.RegClass:$rd, 1477 (vti.Mask srcvalue), 1478 VLOpFrag), 1479 (riscv_fneg_vl vti.RegClass:$rs2, 1480 (vti.Mask srcvalue), 1481 VLOpFrag), 1482 (vti.Mask true_mask), 1483 VLOpFrag)), 1484 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1485 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1486 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1487 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1488 (riscv_fneg_vl vti.RegClass:$rd, 1489 (vti.Mask srcvalue), 1490 VLOpFrag), 1491 (riscv_fneg_vl vti.RegClass:$rs2, 1492 (vti.Mask srcvalue), 1493 VLOpFrag), 1494 (vti.Mask V0), 1495 VLOpFrag)), 1496 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1497 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1498 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1499 1500 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1501 (riscv_fneg_vl vti.RegClass:$rd, 1502 (vti.Mask srcvalue), 1503 VLOpFrag), 1504 vti.RegClass:$rs2, 1505 (vti.Mask true_mask), 1506 VLOpFrag)), 1507 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1508 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1509 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1510 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1511 (riscv_fneg_vl vti.RegClass:$rd, 1512 (vti.Mask srcvalue), 1513 VLOpFrag), 1514 vti.RegClass:$rs2, 1515 (vti.Mask V0), 1516 VLOpFrag)), 1517 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1518 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1519 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1520 1521 // The splat might be negated. 1522 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1523 (vti.Mask srcvalue), 1524 VLOpFrag), 1525 vti.RegClass:$rd, 1526 (riscv_fneg_vl vti.RegClass:$rs2, 1527 (vti.Mask srcvalue), 1528 VLOpFrag), 1529 (vti.Mask true_mask), 1530 VLOpFrag)), 1531 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1532 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1533 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1534 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1535 (vti.Mask srcvalue), 1536 VLOpFrag), 1537 vti.RegClass:$rd, 1538 (riscv_fneg_vl vti.RegClass:$rs2, 1539 (vti.Mask srcvalue), 1540 VLOpFrag), 1541 (vti.Mask V0), 1542 VLOpFrag)), 1543 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1544 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1545 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1546 1547 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1548 (vti.Mask srcvalue), 1549 VLOpFrag), 1550 vti.RegClass:$rd, vti.RegClass:$rs2, 1551 (vti.Mask true_mask), 1552 VLOpFrag)), 1553 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1554 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1555 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1556 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1557 (vti.Mask srcvalue), 1558 VLOpFrag), 1559 vti.RegClass:$rd, vti.RegClass:$rs2, 1560 (vti.Mask V0), 1561 VLOpFrag)), 1562 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1563 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1564 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1565} 1566 1567// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions 1568defm : VPatWidenFPMulAccVL_VV_VF<"PseudoVFWMACC">; 1569defm : VPatWidenFPNegMulAccVL_VV_VF<"PseudoVFWNMACC">; 1570defm : VPatWidenFPMulSacVL_VV_VF<"PseudoVFWMSAC">; 1571defm : VPatWidenFPNegMulSacVL_VV_VF<"PseudoVFWNMSAC">; 1572 1573// 14.11. Vector Floating-Point MIN/MAX Instructions 1574defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1575defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1576 1577// 14.13. Vector Floating-Point Compare Instructions 1578defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1579defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1580 1581defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1582defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1583 1584defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1585defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1586 1587defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1588defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1589 1590foreach vti = AllFloatVectors in { 1591 // 14.8. Vector Floating-Point Square-Root Instruction 1592 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1593 VLOpFrag), 1594 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1595 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1596 1597 // 14.12. Vector Floating-Point Sign-Injection Instructions 1598 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1599 VLOpFrag), 1600 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1601 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1602 // Handle fneg with VFSGNJN using the same input for both operands. 1603 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), 1604 VLOpFrag), 1605 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX #"_MASK") 1606 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs, 1607 vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 1608 TAIL_AGNOSTIC)>; 1609 1610 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1611 (vti.Vector vti.RegClass:$rs2), 1612 (vti.Mask true_mask), 1613 VLOpFrag), 1614 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1615 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1616 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1617 (riscv_fneg_vl vti.RegClass:$rs2, 1618 (vti.Mask true_mask), 1619 VLOpFrag), 1620 (vti.Mask true_mask), 1621 VLOpFrag), 1622 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1623 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1624 1625 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1626 (SplatFPOp vti.ScalarRegClass:$rs2), 1627 (vti.Mask true_mask), 1628 VLOpFrag), 1629 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1630 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1631} 1632 1633foreach fvti = AllFloatVectors in { 1634 // Floating-point vselects: 1635 // 12.15. Vector Integer Merge Instructions 1636 // 14.15. Vector Floating-Point Merge Instruction 1637 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1638 fvti.RegClass:$rs1, 1639 fvti.RegClass:$rs2, 1640 VLOpFrag)), 1641 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1642 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1643 GPR:$vl, fvti.Log2SEW)>; 1644 1645 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1646 (SplatFPOp fvti.ScalarRegClass:$rs1), 1647 fvti.RegClass:$rs2, 1648 VLOpFrag)), 1649 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1650 fvti.RegClass:$rs2, 1651 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1652 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1653 1654 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1655 (SplatFPOp (fvti.Scalar fpimm0)), 1656 fvti.RegClass:$rs2, 1657 VLOpFrag)), 1658 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1659 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1660 1661 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1662 fvti.RegClass:$rs1, 1663 fvti.RegClass:$rs2, 1664 VLOpFrag)), 1665 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX#"_TU") 1666 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1667 GPR:$vl, fvti.Log2SEW)>; 1668 1669 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1670 (SplatFPOp fvti.ScalarRegClass:$rs1), 1671 fvti.RegClass:$rs2, 1672 VLOpFrag)), 1673 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX#"_TU") 1674 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 1675 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1676 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1677 1678 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1679 (SplatFPOp (fvti.Scalar fpimm0)), 1680 fvti.RegClass:$rs2, 1681 VLOpFrag)), 1682 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") 1683 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), 1684 GPR:$vl, fvti.Log2SEW)>; 1685 1686 // 14.16. Vector Floating-Point Move Instruction 1687 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1688 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1689 (fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)), 1690 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1691 0, GPR:$vl, fvti.Log2SEW)>; 1692 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1693 fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)), 1694 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX#"_TU") 1695 $passthru, 0, GPR:$vl, fvti.Log2SEW)>; 1696 1697 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1698 (fvti.Vector undef), (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1699 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1700 fvti.LMul.MX) 1701 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1702 GPR:$vl, fvti.Log2SEW)>; 1703 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1704 fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1705 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1706 fvti.LMul.MX # "_TU") 1707 $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), 1708 GPR:$vl, fvti.Log2SEW)>; 1709 1710 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1711 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1712 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1713 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1714 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1715 1716 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1717 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1718 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1719 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1720 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1721 foreach fvtiToFWti = AllWidenableFloatVectors in { 1722 defvar fvti = fvtiToFWti.Vti; 1723 defvar fwti = fvtiToFWti.Wti; 1724 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1725 (fvti.Mask V0), 1726 VLOpFrag)), 1727 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK") 1728 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1729 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1730 } 1731 1732 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1733 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1734 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1735 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1736 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1737 foreach fvtiToFWti = AllWidenableFloatVectors in { 1738 defvar fvti = fvtiToFWti.Vti; 1739 defvar fwti = fvtiToFWti.Wti; 1740 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1741 (fwti.Mask V0), 1742 VLOpFrag)), 1743 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK") 1744 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1745 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1746 1747 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1748 (fwti.Mask V0), 1749 VLOpFrag)), 1750 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX#"_MASK") 1751 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1752 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1753 } 1754} 1755 1756} // Predicates = [HasVInstructionsAnyF] 1757 1758let Predicates = [HasVInstructions] in { 1759 1760foreach mti = AllMasks in { 1761 // 16.1 Vector Mask-Register Logical Instructions 1762 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1763 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1764 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1765 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1766 1767 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1768 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1769 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1770 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1771 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1772 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1773 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1774 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1775 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1776 1777 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1778 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1779 VLOpFrag)), 1780 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 1781 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1782 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1783 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1784 VLOpFrag)), 1785 (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 1786 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1787 // XOR is associative so we need 2 patterns for VMXNOR. 1788 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1789 VLOpFrag), 1790 VR:$rs2, VLOpFrag)), 1791 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1792 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1793 1794 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1795 VLOpFrag), 1796 VLOpFrag)), 1797 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1798 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1799 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1800 VLOpFrag), 1801 VLOpFrag)), 1802 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1803 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1804 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1805 VLOpFrag), 1806 VLOpFrag)), 1807 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1808 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1809 1810 // Match the not idiom to the vmnot.m pseudo. 1811 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1812 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1813 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1814 1815 // 16.2 Vector count population in mask vcpop.m 1816 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1817 VLOpFrag)), 1818 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 1819 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1820 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 1821 VLOpFrag)), 1822 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 1823 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 1824} 1825 1826} // Predicates = [HasVInstructions] 1827 1828let Predicates = [HasVInstructions] in { 1829// 17.1. Integer Scalar Move Instructions 1830// 17.4. Vector Register Gather Instruction 1831foreach vti = AllIntegerVectors in { 1832 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1833 vti.ScalarRegClass:$rs1, 1834 VLOpFrag)), 1835 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1836 vti.RegClass:$merge, 1837 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1838 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1839 (vti.Vector vti.RegClass:$rs1), 1840 (vti.Mask true_mask), 1841 VLOpFrag)), 1842 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1843 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1844 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1845 (vti.Mask true_mask), 1846 VLOpFrag)), 1847 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1848 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1849 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1850 (vti.Mask true_mask), 1851 VLOpFrag)), 1852 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1853 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1854 1855 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1856 (riscv_vrgather_vv_vl 1857 vti.RegClass:$rs2, 1858 vti.RegClass:$rs1, 1859 (vti.Mask true_mask), 1860 VLOpFrag), 1861 vti.RegClass:$merge, 1862 VLOpFrag)), 1863 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1864 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1865 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1866 1867 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1868 (riscv_vrgather_vx_vl 1869 vti.RegClass:$rs2, 1870 uimm5:$imm, 1871 (vti.Mask true_mask), 1872 VLOpFrag), 1873 vti.RegClass:$merge, 1874 VLOpFrag)), 1875 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1876 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1877 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1878 1879 // emul = lmul * 16 / sew 1880 defvar vlmul = vti.LMul; 1881 defvar octuple_lmul = vlmul.octuple; 1882 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1883 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1884 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1885 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1886 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1887 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1888 (ivti.Vector ivti.RegClass:$rs1), 1889 (vti.Mask true_mask), 1890 VLOpFrag)), 1891 (!cast<Instruction>(inst) 1892 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1893 1894 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1895 (riscv_vrgatherei16_vv_vl 1896 vti.RegClass:$rs2, 1897 (ivti.Vector ivti.RegClass:$rs1), 1898 (vti.Mask true_mask), 1899 VLOpFrag), 1900 vti.RegClass:$merge, 1901 VLOpFrag)), 1902 (!cast<Instruction>(inst#"_MASK") 1903 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1904 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1905 } 1906} 1907 1908} // Predicates = [HasVInstructions] 1909 1910let Predicates = [HasVInstructionsAnyF] in { 1911 1912// 17.2. Floating-Point Scalar Move Instructions 1913foreach vti = AllFloatVectors in { 1914 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1915 (vti.Scalar (fpimm0)), 1916 VLOpFrag)), 1917 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1918 vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>; 1919 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1920 vti.ScalarRegClass:$rs1, 1921 VLOpFrag)), 1922 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1923 vti.RegClass:$merge, 1924 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1925 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1926 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1927 (ivti.Vector vti.RegClass:$rs1), 1928 (vti.Mask true_mask), 1929 VLOpFrag)), 1930 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1931 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1932 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1933 (vti.Mask true_mask), 1934 VLOpFrag)), 1935 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1936 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1937 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1938 (vti.Mask true_mask), 1939 VLOpFrag)), 1940 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1941 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1942 1943 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1944 (riscv_vrgather_vv_vl 1945 vti.RegClass:$rs2, 1946 (ivti.Vector vti.RegClass:$rs1), 1947 (vti.Mask true_mask), 1948 VLOpFrag), 1949 vti.RegClass:$merge, 1950 VLOpFrag)), 1951 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1952 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1953 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1954 1955 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1956 (riscv_vrgather_vx_vl 1957 vti.RegClass:$rs2, 1958 uimm5:$imm, 1959 (vti.Mask true_mask), 1960 VLOpFrag), 1961 vti.RegClass:$merge, 1962 VLOpFrag)), 1963 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1964 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1965 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1966 1967 defvar vlmul = vti.LMul; 1968 defvar octuple_lmul = vlmul.octuple; 1969 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1970 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1971 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1972 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1973 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1974 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1975 (ivti.Vector ivti.RegClass:$rs1), 1976 (vti.Mask true_mask), 1977 VLOpFrag)), 1978 (!cast<Instruction>(inst) 1979 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1980 1981 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1982 (riscv_vrgatherei16_vv_vl 1983 vti.RegClass:$rs2, 1984 (ivti.Vector ivti.RegClass:$rs1), 1985 (vti.Mask true_mask), 1986 VLOpFrag), 1987 vti.RegClass:$merge, 1988 VLOpFrag)), 1989 (!cast<Instruction>(inst#"_MASK") 1990 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1991 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1992 } 1993} 1994 1995} // Predicates = [HasVInstructionsAnyF] 1996 1997//===----------------------------------------------------------------------===// 1998// Miscellaneous RISCVISD SDNodes 1999//===----------------------------------------------------------------------===// 2000 2001def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 2002 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 2003 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 2004 2005def SDTRVVSlide : SDTypeProfile<1, 5, [ 2006 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 2007 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 2008]>; 2009def SDTRVVSlide1 : SDTypeProfile<1, 5, [ 2010 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>, 2011 SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, 2012 SDTCisVT<5, XLenVT> 2013]>; 2014 2015def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 2016def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 2017def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 2018def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 2019 2020let Predicates = [HasVInstructions] in { 2021 2022foreach vti = AllIntegerVectors in { 2023 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 2024 VLOpFrag)), 2025 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 2026 2027 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef), 2028 (vti.Vector vti.RegClass:$rs1), 2029 GPR:$rs2, (vti.Mask true_mask), 2030 VLOpFrag)), 2031 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 2032 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 2033 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rd), 2034 (vti.Vector vti.RegClass:$rs1), 2035 GPR:$rs2, (vti.Mask true_mask), 2036 VLOpFrag)), 2037 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX#"_TU") 2038 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 2039 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector undef), 2040 (vti.Vector vti.RegClass:$rs1), 2041 GPR:$rs2, (vti.Mask true_mask), 2042 VLOpFrag)), 2043 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 2044 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 2045 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rd), 2046 (vti.Vector vti.RegClass:$rs1), 2047 GPR:$rs2, (vti.Mask true_mask), 2048 VLOpFrag)), 2049 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX#"_TU") 2050 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 2051} 2052 2053foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 2054 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 2055 (vti.Vector vti.RegClass:$rs1), 2056 uimm5:$rs2, (vti.Mask true_mask), 2057 VLOpFrag)), 2058 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 2059 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 2060 GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 2061 2062 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 2063 (vti.Vector vti.RegClass:$rs1), 2064 GPR:$rs2, (vti.Mask true_mask), 2065 VLOpFrag)), 2066 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 2067 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 2068 GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED_MASK_UNDISTURBED)>; 2069 2070 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 2071 (vti.Vector vti.RegClass:$rs1), 2072 uimm5:$rs2, (vti.Mask true_mask), 2073 VLOpFrag)), 2074 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 2075 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 2076 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2077 2078 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 2079 (vti.Vector vti.RegClass:$rs1), 2080 GPR:$rs2, (vti.Mask true_mask), 2081 VLOpFrag)), 2082 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 2083 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 2084 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 2085} 2086 2087} // Predicates = [HasVInstructions] 2088