1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// version 1.0. 12/// 13/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 14/// 15/// Note: the patterns for RVV intrinsics are found in 16/// RISCVInstrInfoVPseudos.td. 17/// 18//===----------------------------------------------------------------------===// 19 20//===----------------------------------------------------------------------===// 21// Helpers to define the VL patterns. 22//===----------------------------------------------------------------------===// 23 24def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 25 SDTCisSameAs<0, 2>, 26 SDTCisVec<0>, SDTCisInt<0>, 27 SDTCVecEltisVT<3, i1>, 28 SDTCisSameNumEltsAs<0, 3>, 29 SDTCisVT<4, XLenVT>]>; 30 31def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 32 SDTCisVec<0>, SDTCisFP<0>, 33 SDTCVecEltisVT<2, i1>, 34 SDTCisSameNumEltsAs<0, 2>, 35 SDTCisVT<3, XLenVT>]>; 36def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<3, i1>, 40 SDTCisSameNumEltsAs<0, 3>, 41 SDTCisVT<4, XLenVT>]>; 42 43def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 44 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, 45 SDTCisSameAs<0, 1>, 46 SDTCisVT<2, XLenVT>, 47 SDTCisVT<3, XLenVT>]>>; 48def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 49 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 50 SDTCisSameAs<0, 1>, 51 SDTCisEltOfVec<2, 0>, 52 SDTCisVT<3, XLenVT>]>>; 53def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 54 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 55 SDTCisInt<0>, 56 SDTCisVT<2, XLenVT>, 57 SDTCisVT<3, XLenVT>]>>; 58def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 59 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 60 SDTCisFP<0>, 61 SDTCisEltOfVec<2, 0>, 62 SDTCisVT<3, XLenVT>]>>; 63 64def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 65def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 66def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 67def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 68def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 69def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 70def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 71def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 72def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 73def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 74def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 76def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 77def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 78def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 79def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 80def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 81def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 83 84def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 88 89def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 90def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 91def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 92def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 93def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 94def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 95def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 96def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 97def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 98def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 99 100def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 101 SDTCisSameAs<0, 2>, 102 SDTCisSameAs<0, 3>, 103 SDTCisVec<0>, SDTCisFP<0>, 104 SDTCVecEltisVT<4, i1>, 105 SDTCisSameNumEltsAs<0, 4>, 106 SDTCisVT<5, XLenVT>]>; 107def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 108 109def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 110 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 111 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 112]>; 113def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 114 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 115 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 116]>; 117 118def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 119def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 120def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 121 122def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 127 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 128 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 129]>; 130 131def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 132def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 133def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 134def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 135 136def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 137 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 138 SDTCisVec<1>, 139 SDTCisSameNumEltsAs<0, 1>, 140 SDTCisSameAs<1, 2>, 141 SDTCisVT<3, OtherVT>, 142 SDTCisSameAs<0, 4>, 143 SDTCisVT<5, XLenVT>]>>; 144 145def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 146 SDTypeProfile<1, 4, [SDTCisVec<0>, 147 SDTCisSameAs<0, 1>, 148 SDTCisVT<2, XLenVT>, 149 SDTCVecEltisVT<3, i1>, 150 SDTCisSameNumEltsAs<0, 3>, 151 SDTCisVT<4, XLenVT>]>>; 152def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 153 SDTypeProfile<1, 4, [SDTCisVec<0>, 154 SDTCisSameAs<0, 1>, 155 SDTCisInt<2>, 156 SDTCisSameNumEltsAs<0, 2>, 157 SDTCisSameSizeAs<0, 2>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCVecEltisVT<2, i16>, 166 SDTCisSameNumEltsAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170 171def SDT_RISCVSelect_VL : SDTypeProfile<1, 4, [ 172 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>, 173 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, XLenVT> 174]>; 175 176def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", SDT_RISCVSelect_VL>; 177def riscv_vp_merge_vl : SDNode<"RISCVISD::VP_MERGE_VL", SDT_RISCVSelect_VL>; 178 179def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, 180 SDTCisVT<1, XLenVT>]>; 181def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; 182def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; 183 184def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 185 SDTCisSameAs<0, 2>, 186 SDTCVecEltisVT<0, i1>, 187 SDTCisVT<3, XLenVT>]>; 188def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 189def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 190def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 191 192def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 193 194def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 195 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 196 197def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 198 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 199 SDTCisVec<1>, SDTCisInt<1>, 200 SDTCVecEltisVT<2, i1>, 201 SDTCisSameNumEltsAs<1, 2>, 202 SDTCisVT<3, XLenVT>]>>; 203 204def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 205 SDTCisSameNumEltsAs<0, 1>, 206 SDTCisSameNumEltsAs<1, 2>, 207 SDTCVecEltisVT<2, i1>, 208 SDTCisVT<3, XLenVT>]>; 209def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 210def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 211 212def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 213 SDTypeProfile<1, 3, [SDTCisVec<0>, 214 SDTCisSameNumEltsAs<0, 1>, 215 SDTCisSameNumEltsAs<0, 2>, 216 SDTCVecEltisVT<2, i1>, 217 SDTCisVT<3, XLenVT>]>>; 218 219def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 220 SDTCisSameNumEltsAs<0, 1>, 221 SDTCisSameAs<1, 2>, 222 SDTCisSameNumEltsAs<1, 3>, 223 SDTCVecEltisVT<3, i1>, 224 SDTCisVT<4, XLenVT>]>; 225def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 226def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 227def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>; 228def riscv_vwadd_vl : SDNode<"RISCVISD::VWADD_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 229def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 230def riscv_vwsub_vl : SDNode<"RISCVISD::VWSUB_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 231def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 232 233def SDT_RISCVVWBinOpW_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 234 SDTCisSameAs<0, 1>, 235 SDTCisSameNumEltsAs<1, 2>, 236 SDTCisOpSmallerThanOp<2, 1>, 237 SDTCisSameNumEltsAs<1, 3>, 238 SDTCVecEltisVT<3, i1>, 239 SDTCisVT<4, XLenVT>]>; 240def riscv_vwadd_w_vl : SDNode<"RISCVISD::VWADD_W_VL", SDT_RISCVVWBinOpW_VL>; 241def riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWBinOpW_VL>; 242def riscv_vwsub_w_vl : SDNode<"RISCVISD::VWSUB_W_VL", SDT_RISCVVWBinOpW_VL>; 243def riscv_vwsubu_w_vl : SDNode<"RISCVISD::VWSUBU_W_VL", SDT_RISCVVWBinOpW_VL>; 244 245def SDTRVVVecReduce : SDTypeProfile<1, 5, [ 246 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 247 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT> 248]>; 249 250def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 251 (riscv_mul_vl node:$A, node:$B, node:$C, 252 node:$D), [{ 253 return N->hasOneUse(); 254}]>; 255 256def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 257 (riscv_vwmul_vl node:$A, node:$B, node:$C, 258 node:$D), [{ 259 return N->hasOneUse(); 260}]>; 261 262def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 263 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 264 node:$D), [{ 265 return N->hasOneUse(); 266}]>; 267 268def riscv_vwmulsu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 269 (riscv_vwmulsu_vl node:$A, node:$B, node:$C, 270 node:$D), [{ 271 return N->hasOneUse(); 272}]>; 273 274def riscv_sext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 275 (riscv_sext_vl node:$A, node:$B, node:$C), [{ 276 return N->hasOneUse(); 277}]>; 278 279def riscv_zext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 280 (riscv_zext_vl node:$A, node:$B, node:$C), [{ 281 return N->hasOneUse(); 282}]>; 283 284def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 285 (riscv_fpextend_vl node:$A, node:$B, node:$C), [{ 286 return N->hasOneUse(); 287}]>; 288 289foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 290 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 291 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 292 293// Give explicit Complexity to prefer simm5/uimm5. 294def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; 295def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 2>; 296def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>; 297def SplatPat_simm5_plus1 298 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>; 299def SplatPat_simm5_plus1_nonzero 300 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>; 301 302// Ignore the vl operand. 303def SplatFPOp : PatFrag<(ops node:$op), 304 (riscv_vfmv_v_f_vl undef, node:$op, srcvalue)>; 305 306def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 307def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 308def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 309def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 310 311multiclass VPatBinaryVL_V<SDNode vop, 312 string instruction_name, 313 string suffix, 314 ValueType result_type, 315 ValueType op1_type, 316 ValueType op2_type, 317 ValueType mask_type, 318 int sew, 319 LMULInfo vlmul, 320 VReg op1_reg_class, 321 VReg op2_reg_class> { 322 def : Pat<(result_type (vop 323 (op1_type op1_reg_class:$rs1), 324 (op2_type op2_reg_class:$rs2), 325 (mask_type V0), 326 VLOpFrag)), 327 (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_MASK") 328 (result_type (IMPLICIT_DEF)), 329 op1_reg_class:$rs1, 330 op2_reg_class:$rs2, 331 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 332} 333 334multiclass VPatBinaryVL_XI<SDNode vop, 335 string instruction_name, 336 string suffix, 337 ValueType result_type, 338 ValueType vop1_type, 339 ValueType vop2_type, 340 ValueType mask_type, 341 int sew, 342 LMULInfo vlmul, 343 VReg vop_reg_class, 344 ComplexPattern SplatPatKind, 345 DAGOperand xop_kind> { 346 def : Pat<(result_type (vop 347 (vop1_type vop_reg_class:$rs1), 348 (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))), 349 (mask_type V0), 350 VLOpFrag)), 351 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 352 (result_type (IMPLICIT_DEF)), 353 vop_reg_class:$rs1, 354 xop_kind:$rs2, 355 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 356} 357 358multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 359 foreach vti = AllIntegerVectors in { 360 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 361 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 362 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 363 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 364 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 365 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 366 } 367} 368 369multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 370 Operand ImmType = simm5> 371 : VPatBinaryVL_VV_VX<vop, instruction_name> { 372 foreach vti = AllIntegerVectors in { 373 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 374 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 375 vti.Log2SEW, vti.LMul, vti.RegClass, 376 !cast<ComplexPattern>(SplatPat#_#ImmType), 377 ImmType>; 378 } 379} 380 381multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 382 foreach VtiToWti = AllWidenableIntVectors in { 383 defvar vti = VtiToWti.Vti; 384 defvar wti = VtiToWti.Wti; 385 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 386 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 387 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 388 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 389 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 390 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 391 } 392} 393multiclass VPatBinaryWVL_VV_VX_WV_WX<SDNode vop, SDNode vop_w, 394 string instruction_name> 395 : VPatBinaryWVL_VV_VX<vop, instruction_name> { 396 foreach VtiToWti = AllWidenableIntVectors in { 397 defvar vti = VtiToWti.Vti; 398 defvar wti = VtiToWti.Wti; 399 defm : VPatBinaryVL_V<vop_w, instruction_name, "WV", 400 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 401 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass>; 402 defm : VPatBinaryVL_XI<vop_w, instruction_name, "WX", 403 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 404 vti.Log2SEW, vti.LMul, wti.RegClass, SplatPat, GPR>; 405 } 406} 407 408multiclass VPatBinaryVL_VF<SDNode vop, 409 string instruction_name, 410 ValueType result_type, 411 ValueType vop_type, 412 ValueType mask_type, 413 int sew, 414 LMULInfo vlmul, 415 VReg vop_reg_class, 416 RegisterClass scalar_reg_class> { 417 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 418 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 419 (mask_type V0), 420 VLOpFrag)), 421 (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_MASK") 422 (result_type (IMPLICIT_DEF)), 423 vop_reg_class:$rs1, 424 scalar_reg_class:$rs2, 425 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 426} 427 428multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 429 foreach vti = AllFloatVectors in { 430 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 431 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 432 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 433 defm : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 434 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 435 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 436 } 437} 438 439multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 440 foreach fvti = AllFloatVectors in { 441 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 442 fvti.RegClass:$rs1, 443 (fvti.Mask V0), 444 VLOpFrag)), 445 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 446 (fvti.Vector (IMPLICIT_DEF)), 447 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 448 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 449 } 450} 451 452multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 453 CondCode cc> { 454 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 455 vti.RegClass:$rs2, cc, 456 (vti.Mask V0), 457 VLOpFrag)), 458 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 459 (vti.Mask (IMPLICIT_DEF)), 460 vti.RegClass:$rs1, 461 vti.RegClass:$rs2, 462 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 463} 464 465// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 466multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 467 CondCode cc, CondCode invcc> 468 : VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 469 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 470 vti.RegClass:$rs1, invcc, 471 (vti.Mask V0), 472 VLOpFrag)), 473 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX#"_MASK") 474 (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 475 vti.RegClass:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 476} 477 478multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 479 CondCode cc, CondCode invcc> { 480 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX#"_MASK"); 481 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 482 (SplatPat (XLenVT GPR:$rs2)), cc, 483 (vti.Mask V0), 484 VLOpFrag)), 485 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 486 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 487 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 488 (vti.Vector vti.RegClass:$rs1), invcc, 489 (vti.Mask V0), 490 VLOpFrag)), 491 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 492 GPR:$rs2, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 493} 494 495multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 496 CondCode cc, CondCode invcc> { 497 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 498 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 499 (SplatPat_simm5 simm5:$rs2), cc, 500 (vti.Mask V0), 501 VLOpFrag)), 502 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 503 XLenVT:$rs2, (vti.Mask V0), GPR:$vl, 504 vti.Log2SEW)>; 505 506 // FIXME: Can do some canonicalization to remove these patterns. 507 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 508 (vti.Vector vti.RegClass:$rs1), invcc, 509 (vti.Mask V0), 510 VLOpFrag)), 511 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 512 simm5:$rs2, (vti.Mask V0), GPR:$vl, 513 vti.Log2SEW)>; 514} 515 516multiclass VPatIntegerSetCCVL_VIPlus1_Swappable<VTypeInfo vti, 517 string instruction_name, 518 CondCode cc, CondCode invcc, 519 ComplexPattern splatpat_kind> { 520 defvar instruction_masked = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX#"_MASK"); 521 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 522 (splatpat_kind simm5:$rs2), cc, 523 (vti.Mask V0), 524 VLOpFrag)), 525 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 526 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 527 vti.Log2SEW)>; 528 529 // FIXME: Can do some canonicalization to remove these patterns. 530 def : Pat<(vti.Mask (riscv_setcc_vl (splatpat_kind simm5:$rs2), 531 (vti.Vector vti.RegClass:$rs1), invcc, 532 (vti.Mask V0), 533 VLOpFrag)), 534 (instruction_masked (vti.Mask (IMPLICIT_DEF)), vti.RegClass:$rs1, 535 (DecImm simm5:$rs2), (vti.Mask V0), GPR:$vl, 536 vti.Log2SEW)>; 537} 538 539multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 540 string inst_name, 541 string swapped_op_inst_name> { 542 foreach fvti = AllFloatVectors in { 543 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 544 fvti.RegClass:$rs2, 545 cc, 546 (fvti.Mask true_mask), 547 VLOpFrag)), 548 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX) 549 fvti.RegClass:$rs1, fvti.RegClass:$rs2, GPR:$vl, fvti.Log2SEW)>; 550 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 551 fvti.RegClass:$rs2, 552 cc, 553 (fvti.Mask V0), 554 VLOpFrag)), 555 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX#"_MASK") 556 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 557 fvti.RegClass:$rs2, (fvti.Mask V0), 558 GPR:$vl, fvti.Log2SEW)>; 559 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 560 (SplatFPOp fvti.ScalarRegClass:$rs2), 561 cc, 562 (fvti.Mask true_mask), 563 VLOpFrag)), 564 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 565 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 566 GPR:$vl, fvti.Log2SEW)>; 567 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 568 (SplatFPOp fvti.ScalarRegClass:$rs2), 569 cc, 570 (fvti.Mask V0), 571 VLOpFrag)), 572 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 573 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 574 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 575 GPR:$vl, fvti.Log2SEW)>; 576 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 577 (fvti.Vector fvti.RegClass:$rs1), 578 cc, 579 (fvti.Mask true_mask), 580 VLOpFrag)), 581 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 582 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 583 GPR:$vl, fvti.Log2SEW)>; 584 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 585 (fvti.Vector fvti.RegClass:$rs1), 586 cc, 587 (fvti.Mask V0), 588 VLOpFrag)), 589 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 590 (fvti.Mask (IMPLICIT_DEF)), fvti.RegClass:$rs1, 591 fvti.ScalarRegClass:$rs2, (fvti.Mask V0), 592 GPR:$vl, fvti.Log2SEW)>; 593 } 594} 595 596multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 597 list <VTypeInfoToFraction> fraction_list> { 598 foreach vtiTofti = fraction_list in { 599 defvar vti = vtiTofti.Vti; 600 defvar fti = vtiTofti.Fti; 601 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 602 (fti.Mask V0), VLOpFrag)), 603 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK") 604 (vti.Vector (IMPLICIT_DEF)), 605 fti.RegClass:$rs2, 606 (fti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 607 } 608} 609 610multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 611 foreach fvti = AllFloatVectors in { 612 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 613 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 614 (fvti.Mask V0), 615 VLOpFrag)), 616 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 617 (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 618 (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 619 } 620} 621 622multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 623 foreach fvti = AllFloatVectors in { 624 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 625 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 626 (ivti.Mask V0), 627 VLOpFrag)), 628 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 629 (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 630 (ivti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 631 } 632} 633 634multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 635 foreach fvtiToFWti = AllWidenableFloatVectors in { 636 defvar fvti = fvtiToFWti.Vti; 637 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 638 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 639 (fvti.Mask V0), 640 VLOpFrag)), 641 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 642 (iwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 643 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 644 } 645} 646 647multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 648 foreach vtiToWti = AllWidenableIntToFloatVectors in { 649 defvar ivti = vtiToWti.Vti; 650 defvar fwti = vtiToWti.Wti; 651 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 652 (ivti.Mask V0), 653 VLOpFrag)), 654 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") 655 (fwti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, 656 (ivti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; 657 } 658} 659 660multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 661 foreach vtiToWti = AllWidenableIntToFloatVectors in { 662 defvar vti = vtiToWti.Vti; 663 defvar fwti = vtiToWti.Wti; 664 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 665 (fwti.Mask V0), 666 VLOpFrag)), 667 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX#"_MASK") 668 (vti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 669 (fwti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 670 } 671} 672 673multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 674 foreach fvtiToFWti = AllWidenableFloatVectors in { 675 defvar fvti = fvtiToFWti.Vti; 676 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 677 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 678 (iwti.Mask V0), 679 VLOpFrag)), 680 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") 681 (fvti.Vector (IMPLICIT_DEF)), iwti.RegClass:$rs1, 682 (iwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 683 } 684} 685 686multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 687 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 688 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 689 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 690 (vti.Mask true_mask), 691 VLOpFrag)), 692 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 693 (vti_m1.Vector VR:$merge), 694 (vti.Vector vti.RegClass:$rs1), 695 (vti_m1.Vector VR:$rs2), 696 GPR:$vl, vti.Log2SEW)>; 697 698 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 699 (vti.Mask V0), VLOpFrag)), 700 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 701 (vti_m1.Vector VR:$merge), 702 (vti.Vector vti.RegClass:$rs1), 703 (vti_m1.Vector VR:$rs2), 704 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 705 } 706} 707 708multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> { 709 foreach vti = AllWidenableIntVectors in { 710 def : Pat< 711 (vti.Vti.Vector 712 (riscv_trunc_vector_vl 713 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 714 (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), 715 (riscv_vmset_vl VLOpFrag), 716 VLOpFrag)), 717 (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX) 718 vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1, 719 vti.Vti.AVL, vti.Vti.Log2SEW)>; 720 def : Pat< 721 (vti.Vti.Vector 722 (riscv_trunc_vector_vl 723 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 724 (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))), 725 (riscv_vmset_vl VLOpFrag), 726 VLOpFrag)), 727 (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) 728 vti.Wti.RegClass:$rs2, GPR:$rs1, 729 vti.Vti.AVL, vti.Vti.Log2SEW)>; 730 } 731} 732 733multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> { 734 defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>; 735 defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>; 736 foreach vti = AllWidenableIntVectors in { 737 def : Pat< 738 (vti.Vti.Vector 739 (riscv_trunc_vector_vl 740 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 741 (vti.Wti.Vector (SplatPat_uimm5 uimm5:$rs1))), 742 (riscv_vmset_vl VLOpFrag), 743 VLOpFrag)), 744 (!cast<Instruction>(instruction_name#"_WI_"#vti.Vti.LMul.MX) 745 vti.Wti.RegClass:$rs2, uimm5:$rs1, 746 vti.Vti.AVL, vti.Vti.Log2SEW)>; 747 } 748} 749 750multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 751 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 752 defvar vti = vtiToWti.Vti; 753 defvar wti = vtiToWti.Wti; 754 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 755 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 756 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 757 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 758 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 759 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 760 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 761 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 762 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 763 VR:$rs2, (vti.Mask V0), VLOpFrag)), 764 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 765 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 766 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 767 } 768} 769 770multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 771 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 772 defvar vti = vtiToWti.Vti; 773 defvar wti = vtiToWti.Wti; 774 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 775 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 776 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 777 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 778 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 779 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 780 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 781 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 782 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 783 VR:$rs2, (vti.Mask V0), VLOpFrag)), 784 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 785 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 786 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 787 } 788} 789 790multiclass VPatWidenBinaryFPVL_VV_VF<SDNode op, PatFrags extop, string instruction_name> { 791 foreach fvtiToFWti = AllWidenableFloatVectors in { 792 defvar fvti = fvtiToFWti.Vti; 793 defvar fwti = fvtiToFWti.Wti; 794 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 795 (fvti.Mask true_mask), VLOpFrag)), 796 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 797 (fvti.Mask true_mask), VLOpFrag)), 798 (fwti.Mask true_mask), VLOpFrag)), 799 (!cast<Instruction>(instruction_name#"_VV_"#fvti.LMul.MX) 800 fvti.RegClass:$rs2, fvti.RegClass:$rs1, 801 GPR:$vl, fvti.Log2SEW)>; 802 def : Pat<(fwti.Vector (op (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs2), 803 (fvti.Mask true_mask), VLOpFrag)), 804 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 805 (fvti.Mask true_mask), VLOpFrag)), 806 (fwti.Mask true_mask), VLOpFrag)), 807 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 808 fvti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 809 GPR:$vl, fvti.Log2SEW)>; 810 } 811} 812 813multiclass VPatWidenBinaryFPVL_WV_WF<SDNode op, PatFrags extop, string instruction_name> { 814 foreach fvtiToFWti = AllWidenableFloatVectors in { 815 defvar fvti = fvtiToFWti.Vti; 816 defvar fwti = fvtiToFWti.Wti; 817 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 818 (fwti.Vector (extop (fvti.Vector fvti.RegClass:$rs1), 819 (fvti.Mask true_mask), VLOpFrag)), 820 (fwti.Mask true_mask), VLOpFrag)), 821 (!cast<Instruction>(instruction_name#"_WV_"#fvti.LMul.MX) 822 fwti.RegClass:$rs2, fvti.RegClass:$rs1, 823 GPR:$vl, fvti.Log2SEW)>; 824 def : Pat<(fwti.Vector (op (fwti.Vector fwti.RegClass:$rs2), 825 (fwti.Vector (extop (fvti.Vector (SplatFPOp fvti.ScalarRegClass:$rs1)), 826 (fvti.Mask true_mask), VLOpFrag)), 827 (fwti.Mask true_mask), VLOpFrag)), 828 (!cast<Instruction>(instruction_name#"_W"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 829 fwti.RegClass:$rs2, fvti.ScalarRegClass:$rs1, 830 GPR:$vl, fvti.Log2SEW)>; 831 } 832} 833 834multiclass VPatWidenBinaryFPVL_VV_VF_WV_WF<SDNode op, string instruction_name> { 835 defm : VPatWidenBinaryFPVL_VV_VF<op, riscv_fpextend_vl_oneuse, instruction_name>; 836 defm : VPatWidenBinaryFPVL_WV_WF<op, riscv_fpextend_vl_oneuse, instruction_name>; 837} 838 839multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruction_name> { 840 foreach vti = AllWidenableIntVectors in { 841 def : Pat< 842 (vti.Vti.Vector 843 (riscv_trunc_vector_vl 844 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 845 (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1)), 846 (vti.Vti.Mask true_mask), VLOpFrag)), 847 (vti.Wti.Mask true_mask), VLOpFrag), 848 (vti.Vti.Mask true_mask), VLOpFrag)), 849 (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) 850 vti.Wti.RegClass:$rs2, GPR:$rs1, 851 vti.Vti.AVL, vti.Vti.Log2SEW)>; 852 } 853} 854 855//===----------------------------------------------------------------------===// 856// Patterns. 857//===----------------------------------------------------------------------===// 858 859let Predicates = [HasVInstructions] in { 860 861// 12.1. Vector Single-Width Integer Add and Subtract 862defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 863defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 864// Handle VRSUB specially since it's the only integer binary op with reversed 865// pattern operands 866foreach vti = AllIntegerVectors in { 867 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 868 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 869 VLOpFrag), 870 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 871 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 872 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 873 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 874 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 875 VLOpFrag), 876 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 877 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 878 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 879} 880 881// 12.2. Vector Widening Integer Add/Subtract 882defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwadd_vl, riscv_vwadd_w_vl, "PseudoVWADD">; 883defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWADDU">; 884defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">; 885defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">; 886 887// 12.3. Vector Integer Extension 888defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 889 AllFractionableVF2IntVectors>; 890defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 891 AllFractionableVF2IntVectors>; 892defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 893 AllFractionableVF4IntVectors>; 894defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 895 AllFractionableVF4IntVectors>; 896defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 897 AllFractionableVF8IntVectors>; 898defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 899 AllFractionableVF8IntVectors>; 900 901// 12.5. Vector Bitwise Logical Instructions 902defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 903defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 904defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 905 906// 12.6. Vector Single-Width Bit Shift Instructions 907defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 908defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 909defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 910 911foreach vti = AllIntegerVectors in { 912 // Emit shift by 1 as an add since it might be faster. 913 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 914 (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)), 915 (vti.Mask true_mask), 916 VLOpFrag), 917 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 918 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 919} 920 921// 12.7. Vector Narrowing Integer Right Shift Instructions 922defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">; 923defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">; 924 925foreach vtiTowti = AllWidenableIntVectors in { 926 defvar vti = vtiTowti.Vti; 927 defvar wti = vtiTowti.Wti; 928 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 929 (vti.Mask true_mask), 930 VLOpFrag)), 931 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 932 wti.RegClass:$rs1, X0, GPR:$vl, vti.Log2SEW)>; 933 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 934 (vti.Mask V0), 935 VLOpFrag)), 936 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX#"_MASK") 937 (vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, X0, 938 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 939 940 def : Pat<(vti.Vector 941 (riscv_trunc_vector_vl 942 (wti.Vector 943 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 944 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 945 (!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX) 946 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 947 defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_sext_vl_oneuse, "PseudoVNSRA">; 948 defm : VPatNarrowShiftSplatExt_WX<riscv_sra_vl, riscv_zext_vl_oneuse, "PseudoVNSRA">; 949 def : Pat<(vti.Vector 950 (riscv_trunc_vector_vl 951 (wti.Vector 952 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 953 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 954 (!cast<Instruction>("PseudoVNSRA_WI_"#vti.LMul.MX) 955 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 956 def : Pat<(vti.Vector 957 (riscv_trunc_vector_vl 958 (wti.Vector 959 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 960 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 961 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 962 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 963 defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_sext_vl_oneuse, "PseudoVNSRL">; 964 defm : VPatNarrowShiftSplatExt_WX<riscv_srl_vl, riscv_zext_vl_oneuse, "PseudoVNSRL">; 965 def : Pat<(vti.Vector 966 (riscv_trunc_vector_vl 967 (wti.Vector 968 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 969 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 970 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) 971 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 972} 973 974// 12.8. Vector Integer Comparison Instructions 975foreach vti = AllIntegerVectors in { 976 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 977 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 978 979 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 980 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 981 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 982 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 983 984 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 985 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 986 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 987 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 988 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 989 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 990 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 991 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 992 // There is no VMSGE(U)_VX instruction 993 994 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 995 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 996 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 997 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 998 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 999 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 1000 1001 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLE", SETLT, SETGT, 1002 SplatPat_simm5_plus1_nonzero>; 1003 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT, 1004 SplatPat_simm5_plus1_nonzero>; 1005 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGT", SETGE, SETLE, 1006 SplatPat_simm5_plus1>; 1007 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSGTU", SETUGE, SETULE, 1008 SplatPat_simm5_plus1_nonzero>; 1009} // foreach vti = AllIntegerVectors 1010 1011// 12.9. Vector Integer Min/Max Instructions 1012defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 1013defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 1014defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 1015defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 1016 1017// 12.10. Vector Single-Width Integer Multiply Instructions 1018defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 1019defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 1020defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 1021 1022// 12.11. Vector Integer Divide Instructions 1023defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 1024defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 1025defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 1026defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 1027 1028// 12.12. Vector Widening Integer Multiply Instructions 1029defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 1030defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 1031defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; 1032 1033// 12.13 Vector Single-Width Integer Multiply-Add Instructions 1034foreach vti = AllIntegerVectors in { 1035 // NOTE: We choose VMADD because it has the most commuting freedom. So it 1036 // works best with how TwoAddressInstructionPass tries commuting. 1037 defvar suffix = vti.LMul.MX; 1038 def : Pat<(vti.Vector 1039 (riscv_add_vl vti.RegClass:$rs2, 1040 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 1041 vti.RegClass:$rd, 1042 (vti.Mask true_mask), VLOpFrag), 1043 (vti.Mask true_mask), VLOpFrag)), 1044 (!cast<Instruction>("PseudoVMADD_VV_"# suffix) 1045 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1046 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1047 def : Pat<(vti.Vector 1048 (riscv_sub_vl vti.RegClass:$rs2, 1049 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 1050 vti.RegClass:$rd, 1051 (vti.Mask true_mask), VLOpFrag), 1052 (vti.Mask true_mask), VLOpFrag)), 1053 (!cast<Instruction>("PseudoVNMSUB_VV_"# suffix) 1054 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1055 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1056 1057 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 1058 // commutable. 1059 def : Pat<(vti.Vector 1060 (riscv_add_vl vti.RegClass:$rs2, 1061 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 1062 vti.RegClass:$rd, 1063 (vti.Mask true_mask), VLOpFrag), 1064 (vti.Mask true_mask), VLOpFrag)), 1065 (!cast<Instruction>("PseudoVMADD_VX_" # suffix) 1066 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1067 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1068 def : Pat<(vti.Vector 1069 (riscv_sub_vl vti.RegClass:$rs2, 1070 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 1071 vti.RegClass:$rd, 1072 (vti.Mask true_mask), 1073 VLOpFrag), 1074 (vti.Mask true_mask), VLOpFrag)), 1075 (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix) 1076 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1077 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1078} 1079 1080// 12.14. Vector Widening Integer Multiply-Add Instructions 1081foreach vtiTowti = AllWidenableIntVectors in { 1082 defvar vti = vtiTowti.Vti; 1083 defvar wti = vtiTowti.Wti; 1084 def : Pat<(wti.Vector 1085 (riscv_add_vl wti.RegClass:$rd, 1086 (riscv_vwmul_vl_oneuse vti.RegClass:$rs1, 1087 (vti.Vector vti.RegClass:$rs2), 1088 (vti.Mask true_mask), VLOpFrag), 1089 (vti.Mask true_mask), VLOpFrag)), 1090 (!cast<Instruction>("PseudoVWMACC_VV_" # vti.LMul.MX) 1091 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1092 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1093 def : Pat<(wti.Vector 1094 (riscv_add_vl wti.RegClass:$rd, 1095 (riscv_vwmulu_vl_oneuse vti.RegClass:$rs1, 1096 (vti.Vector vti.RegClass:$rs2), 1097 (vti.Mask true_mask), VLOpFrag), 1098 (vti.Mask true_mask), VLOpFrag)), 1099 (!cast<Instruction>("PseudoVWMACCU_VV_" # vti.LMul.MX) 1100 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1101 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1102 def : Pat<(wti.Vector 1103 (riscv_add_vl wti.RegClass:$rd, 1104 (riscv_vwmulsu_vl_oneuse vti.RegClass:$rs1, 1105 (vti.Vector vti.RegClass:$rs2), 1106 (vti.Mask true_mask), VLOpFrag), 1107 (vti.Mask true_mask), VLOpFrag)), 1108 (!cast<Instruction>("PseudoVWMACCSU_VV_" # vti.LMul.MX) 1109 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1110 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1111 1112 def : Pat<(wti.Vector 1113 (riscv_add_vl wti.RegClass:$rd, 1114 (riscv_vwmul_vl_oneuse (SplatPat XLenVT:$rs1), 1115 (vti.Vector vti.RegClass:$rs2), 1116 (vti.Mask true_mask), VLOpFrag), 1117 (vti.Mask true_mask), VLOpFrag)), 1118 (!cast<Instruction>("PseudoVWMACC_VX_" # vti.LMul.MX) 1119 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1120 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1121 def : Pat<(wti.Vector 1122 (riscv_add_vl wti.RegClass:$rd, 1123 (riscv_vwmulu_vl_oneuse (SplatPat XLenVT:$rs1), 1124 (vti.Vector vti.RegClass:$rs2), 1125 (vti.Mask true_mask), VLOpFrag), 1126 (vti.Mask true_mask), VLOpFrag)), 1127 (!cast<Instruction>("PseudoVWMACCU_VX_" # vti.LMul.MX) 1128 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1129 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1130 def : Pat<(wti.Vector 1131 (riscv_add_vl wti.RegClass:$rd, 1132 (riscv_vwmulsu_vl_oneuse (SplatPat XLenVT:$rs1), 1133 (vti.Vector vti.RegClass:$rs2), 1134 (vti.Mask true_mask), VLOpFrag), 1135 (vti.Mask true_mask), VLOpFrag)), 1136 (!cast<Instruction>("PseudoVWMACCSU_VX_" # vti.LMul.MX) 1137 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1138 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1139 def : Pat<(wti.Vector 1140 (riscv_add_vl wti.RegClass:$rd, 1141 (riscv_vwmulsu_vl_oneuse (vti.Vector vti.RegClass:$rs1), 1142 (SplatPat XLenVT:$rs2), 1143 (vti.Mask true_mask), VLOpFrag), 1144 (vti.Mask true_mask), VLOpFrag)), 1145 (!cast<Instruction>("PseudoVWMACCUS_VX_" # vti.LMul.MX) 1146 wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1, 1147 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1148} 1149 1150// 12.15. Vector Integer Merge Instructions 1151foreach vti = AllIntegerVectors in { 1152 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1153 vti.RegClass:$rs1, 1154 vti.RegClass:$rs2, 1155 VLOpFrag)), 1156 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 1157 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 1158 GPR:$vl, vti.Log2SEW)>; 1159 1160 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1161 (SplatPat XLenVT:$rs1), 1162 vti.RegClass:$rs2, 1163 VLOpFrag)), 1164 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 1165 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1166 1167 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1168 (SplatPat_simm5 simm5:$rs1), 1169 vti.RegClass:$rs2, 1170 VLOpFrag)), 1171 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 1172 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1173 1174 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1175 vti.RegClass:$rs1, 1176 vti.RegClass:$rs2, 1177 VLOpFrag)), 1178 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX#"_TU") 1179 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1, 1180 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1181 1182 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1183 (SplatPat XLenVT:$rs1), 1184 vti.RegClass:$rs2, 1185 VLOpFrag)), 1186 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX#"_TU") 1187 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1, 1188 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1189 1190 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1191 (SplatPat_simm5 simm5:$rs1), 1192 vti.RegClass:$rs2, 1193 VLOpFrag)), 1194 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU") 1195 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, 1196 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1197} 1198 1199// 12.16. Vector Integer Move Instructions 1200foreach vti = AllIntegerVectors in { 1201 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)), 1202 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 1203 $rs2, GPR:$vl, vti.Log2SEW)>; 1204 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, GPR:$rs2, VLOpFrag)), 1205 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX#"_TU") 1206 $passthru, $rs2, GPR:$vl, vti.Log2SEW)>; 1207 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 1208 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat XLenVT:$imm5), 1209 VLOpFrag)), 1210 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 1211 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1212 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, (ImmPat XLenVT:$imm5), 1213 VLOpFrag)), 1214 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX#"_TU") 1215 $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1216} 1217 1218// 12.1. Vector Single-Width Saturating Add and Subtract 1219defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 1220defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 1221defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 1222defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 1223 1224} // Predicates = [HasVInstructions] 1225 1226// 15.1. Vector Single-Width Integer Reduction Instructions 1227let Predicates = [HasVInstructions] in { 1228defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 1229defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 1230defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 1231defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 1232defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 1233defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 1234defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 1235defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 1236 1237// 15.2. Vector Widening Integer Reduction Instructions 1238defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1239defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1240defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1241defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1242defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1243} // Predicates = [HasVInstructions] 1244 1245// 15.3. Vector Single-Width Floating-Point Reduction Instructions 1246let Predicates = [HasVInstructionsAnyF] in { 1247defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 1248defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>; 1249defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 1250defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 1251 1252// 15.4. Vector Widening Floating-Point Reduction Instructions 1253defm : VPatWidenReductionVL<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1254defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_SEQ_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1255defm : VPatWidenReductionVL<rvv_vecreduce_FADD_vl, fpext_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1256defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1257} // Predicates = [HasVInstructionsAnyF] 1258 1259let Predicates = [HasVInstructionsAnyF] in { 1260 1261// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 1262defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 1263defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 1264defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 1265 1266// 14.3. Vector Widening Floating-Point Add/Subtract Instructions 1267defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fadd_vl, "PseudoVFWADD">; 1268defm : VPatWidenBinaryFPVL_VV_VF_WV_WF<riscv_fsub_vl, "PseudoVFWSUB">; 1269 1270// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 1271defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 1272defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 1273defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 1274 1275// 14.5. Vector Widening Floating-Point Multiply Instructions 1276defm : VPatWidenBinaryFPVL_VV_VF<riscv_fmul_vl, riscv_fpextend_vl_oneuse, "PseudoVFWMUL">; 1277 1278// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 1279foreach vti = AllFloatVectors in { 1280 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 1281 // works best with how TwoAddressInstructionPass tries commuting. 1282 defvar suffix = vti.LMul.MX; 1283 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1284 vti.RegClass:$rs2, (vti.Mask true_mask), 1285 VLOpFrag)), 1286 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 1287 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1288 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1289 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1290 vti.RegClass:$rs2, (vti.Mask V0), 1291 VLOpFrag)), 1292 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix #"_MASK") 1293 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1294 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>; 1295 1296 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1297 (riscv_fneg_vl vti.RegClass:$rs2, 1298 (vti.Mask true_mask), 1299 VLOpFrag), 1300 (vti.Mask true_mask), 1301 VLOpFrag)), 1302 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 1303 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1304 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1305 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1306 (riscv_fneg_vl vti.RegClass:$rs2, 1307 (vti.Mask srcvalue), 1308 VLOpFrag), 1309 (vti.Mask V0), 1310 VLOpFrag)), 1311 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix #"_MASK") 1312 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1313 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1314 1315 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1316 (vti.Mask srcvalue), 1317 VLOpFrag), 1318 vti.RegClass:$rd, 1319 (riscv_fneg_vl vti.RegClass:$rs2, 1320 (vti.Mask srcvalue), 1321 VLOpFrag), 1322 (vti.Mask true_mask), 1323 VLOpFrag)), 1324 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 1325 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1326 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1327 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1328 (vti.Mask srcvalue), 1329 VLOpFrag), 1330 vti.RegClass:$rd, 1331 (riscv_fneg_vl vti.RegClass:$rs2, 1332 (vti.Mask srcvalue), 1333 VLOpFrag), 1334 (vti.Mask V0), 1335 VLOpFrag)), 1336 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix #"_MASK") 1337 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1338 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1339 1340 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1341 (vti.Mask srcvalue), 1342 VLOpFrag), 1343 vti.RegClass:$rd, vti.RegClass:$rs2, 1344 (vti.Mask true_mask), 1345 VLOpFrag)), 1346 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 1347 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1348 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1349 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1350 (vti.Mask srcvalue), 1351 VLOpFrag), 1352 vti.RegClass:$rd, vti.RegClass:$rs2, 1353 (vti.Mask V0), 1354 VLOpFrag)), 1355 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix #"_MASK") 1356 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1357 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1358 1359 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 1360 // commutable. 1361 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1362 vti.RegClass:$rd, vti.RegClass:$rs2, 1363 (vti.Mask true_mask), 1364 VLOpFrag)), 1365 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1366 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1367 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1368 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1369 vti.RegClass:$rd, vti.RegClass:$rs2, 1370 (vti.Mask V0), 1371 VLOpFrag)), 1372 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1373 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1374 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>; 1375 1376 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1377 vti.RegClass:$rd, 1378 (riscv_fneg_vl vti.RegClass:$rs2, 1379 (vti.Mask srcvalue), 1380 VLOpFrag), 1381 (vti.Mask true_mask), 1382 VLOpFrag)), 1383 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1384 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1385 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1386 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1387 vti.RegClass:$rd, 1388 (riscv_fneg_vl vti.RegClass:$rs2, 1389 (vti.Mask srcvalue), 1390 VLOpFrag), 1391 (vti.Mask V0), 1392 VLOpFrag)), 1393 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1394 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1395 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1396 1397 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1398 (riscv_fneg_vl vti.RegClass:$rd, 1399 (vti.Mask srcvalue), 1400 VLOpFrag), 1401 (riscv_fneg_vl vti.RegClass:$rs2, 1402 (vti.Mask srcvalue), 1403 VLOpFrag), 1404 (vti.Mask true_mask), 1405 VLOpFrag)), 1406 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1407 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1408 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1409 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1410 (riscv_fneg_vl vti.RegClass:$rd, 1411 (vti.Mask srcvalue), 1412 VLOpFrag), 1413 (riscv_fneg_vl vti.RegClass:$rs2, 1414 (vti.Mask srcvalue), 1415 VLOpFrag), 1416 (vti.Mask V0), 1417 VLOpFrag)), 1418 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1419 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1420 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1421 1422 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1423 (riscv_fneg_vl vti.RegClass:$rd, 1424 (vti.Mask srcvalue), 1425 VLOpFrag), 1426 vti.RegClass:$rs2, 1427 (vti.Mask true_mask), 1428 VLOpFrag)), 1429 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1430 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1431 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1432 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1433 (riscv_fneg_vl vti.RegClass:$rd, 1434 (vti.Mask srcvalue), 1435 VLOpFrag), 1436 vti.RegClass:$rs2, 1437 (vti.Mask V0), 1438 VLOpFrag)), 1439 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1440 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1441 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1442 1443 // The splat might be negated. 1444 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1445 (vti.Mask srcvalue), 1446 VLOpFrag), 1447 vti.RegClass:$rd, 1448 (riscv_fneg_vl vti.RegClass:$rs2, 1449 (vti.Mask srcvalue), 1450 VLOpFrag), 1451 (vti.Mask true_mask), 1452 VLOpFrag)), 1453 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1454 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1455 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1456 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1457 (vti.Mask srcvalue), 1458 VLOpFrag), 1459 vti.RegClass:$rd, 1460 (riscv_fneg_vl vti.RegClass:$rs2, 1461 (vti.Mask srcvalue), 1462 VLOpFrag), 1463 (vti.Mask V0), 1464 VLOpFrag)), 1465 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1466 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1467 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1468 1469 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1470 (vti.Mask srcvalue), 1471 VLOpFrag), 1472 vti.RegClass:$rd, vti.RegClass:$rs2, 1473 (vti.Mask true_mask), 1474 VLOpFrag)), 1475 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1476 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1477 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1478 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1479 (vti.Mask srcvalue), 1480 VLOpFrag), 1481 vti.RegClass:$rd, vti.RegClass:$rs2, 1482 (vti.Mask V0), 1483 VLOpFrag)), 1484 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1485 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1486 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1487} 1488 1489// 14.11. Vector Floating-Point MIN/MAX Instructions 1490defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1491defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1492 1493// 14.13. Vector Floating-Point Compare Instructions 1494defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1495defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1496 1497defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1498defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1499 1500defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1501defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1502 1503defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1504defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1505 1506foreach vti = AllFloatVectors in { 1507 // 14.8. Vector Floating-Point Square-Root Instruction 1508 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1509 VLOpFrag), 1510 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1511 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1512 1513 // 14.12. Vector Floating-Point Sign-Injection Instructions 1514 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1515 VLOpFrag), 1516 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1517 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1518 // Handle fneg with VFSGNJN using the same input for both operands. 1519 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), 1520 VLOpFrag), 1521 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX #"_MASK") 1522 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs, 1523 vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 1524 TAIL_AGNOSTIC)>; 1525 1526 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1527 (vti.Vector vti.RegClass:$rs2), 1528 (vti.Mask true_mask), 1529 VLOpFrag), 1530 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1531 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1532 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1533 (riscv_fneg_vl vti.RegClass:$rs2, 1534 (vti.Mask true_mask), 1535 VLOpFrag), 1536 (vti.Mask true_mask), 1537 VLOpFrag), 1538 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1539 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1540 1541 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1542 (SplatFPOp vti.ScalarRegClass:$rs2), 1543 (vti.Mask true_mask), 1544 VLOpFrag), 1545 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1546 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1547} 1548 1549foreach fvti = AllFloatVectors in { 1550 // Floating-point vselects: 1551 // 12.15. Vector Integer Merge Instructions 1552 // 14.15. Vector Floating-Point Merge Instruction 1553 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1554 fvti.RegClass:$rs1, 1555 fvti.RegClass:$rs2, 1556 VLOpFrag)), 1557 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1558 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1559 GPR:$vl, fvti.Log2SEW)>; 1560 1561 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1562 (SplatFPOp fvti.ScalarRegClass:$rs1), 1563 fvti.RegClass:$rs2, 1564 VLOpFrag)), 1565 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1566 fvti.RegClass:$rs2, 1567 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1568 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1569 1570 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1571 (SplatFPOp (fvti.Scalar fpimm0)), 1572 fvti.RegClass:$rs2, 1573 VLOpFrag)), 1574 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1575 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1576 1577 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1578 fvti.RegClass:$rs1, 1579 fvti.RegClass:$rs2, 1580 VLOpFrag)), 1581 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX#"_TU") 1582 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1583 GPR:$vl, fvti.Log2SEW)>; 1584 1585 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1586 (SplatFPOp fvti.ScalarRegClass:$rs1), 1587 fvti.RegClass:$rs2, 1588 VLOpFrag)), 1589 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX#"_TU") 1590 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 1591 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1592 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1593 1594 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1595 (SplatFPOp (fvti.Scalar fpimm0)), 1596 fvti.RegClass:$rs2, 1597 VLOpFrag)), 1598 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") 1599 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), 1600 GPR:$vl, fvti.Log2SEW)>; 1601 1602 // 14.16. Vector Floating-Point Move Instruction 1603 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1604 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1605 (fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)), 1606 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1607 0, GPR:$vl, fvti.Log2SEW)>; 1608 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1609 fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)), 1610 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX#"_TU") 1611 $passthru, 0, GPR:$vl, fvti.Log2SEW)>; 1612 1613 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1614 (fvti.Vector undef), (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1615 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1616 fvti.LMul.MX) 1617 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1618 GPR:$vl, fvti.Log2SEW)>; 1619 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1620 fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1621 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1622 fvti.LMul.MX # "_TU") 1623 $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), 1624 GPR:$vl, fvti.Log2SEW)>; 1625 1626 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1627 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1628 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1629 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1630 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1631 1632 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1633 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1634 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1635 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1636 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1637 foreach fvtiToFWti = AllWidenableFloatVectors in { 1638 defvar fvti = fvtiToFWti.Vti; 1639 defvar fwti = fvtiToFWti.Wti; 1640 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1641 (fvti.Mask V0), 1642 VLOpFrag)), 1643 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX#"_MASK") 1644 (fwti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, 1645 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1646 } 1647 1648 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1649 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1650 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1651 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1652 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1653 foreach fvtiToFWti = AllWidenableFloatVectors in { 1654 defvar fvti = fvtiToFWti.Vti; 1655 defvar fwti = fvtiToFWti.Wti; 1656 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1657 (fwti.Mask V0), 1658 VLOpFrag)), 1659 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_MASK") 1660 (fvti.Vector (IMPLICIT_DEF)), fwti.RegClass:$rs1, 1661 (fwti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 1662 1663 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1664 (fwti.Mask true_mask), 1665 VLOpFrag)), 1666 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX) 1667 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1668 } 1669} 1670 1671} // Predicates = [HasVInstructionsAnyF] 1672 1673let Predicates = [HasVInstructions] in { 1674 1675foreach mti = AllMasks in { 1676 // 16.1 Vector Mask-Register Logical Instructions 1677 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1678 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1679 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1680 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1681 1682 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1683 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1684 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1685 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1686 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1687 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1688 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1689 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1690 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1691 1692 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1693 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1694 VLOpFrag)), 1695 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 1696 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1697 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1698 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1699 VLOpFrag)), 1700 (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 1701 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1702 // XOR is associative so we need 2 patterns for VMXNOR. 1703 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1704 VLOpFrag), 1705 VR:$rs2, VLOpFrag)), 1706 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1707 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1708 1709 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1710 VLOpFrag), 1711 VLOpFrag)), 1712 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1713 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1714 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1715 VLOpFrag), 1716 VLOpFrag)), 1717 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1718 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1719 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1720 VLOpFrag), 1721 VLOpFrag)), 1722 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1723 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1724 1725 // Match the not idiom to the vmnot.m pseudo. 1726 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1727 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1728 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1729 1730 // 16.2 Vector count population in mask vcpop.m 1731 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1732 VLOpFrag)), 1733 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 1734 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1735 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 1736 VLOpFrag)), 1737 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 1738 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 1739} 1740 1741} // Predicates = [HasVInstructions] 1742 1743let Predicates = [HasVInstructions] in { 1744// 17.1. Integer Scalar Move Instructions 1745// 17.4. Vector Register Gather Instruction 1746foreach vti = AllIntegerVectors in { 1747 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1748 vti.ScalarRegClass:$rs1, 1749 VLOpFrag)), 1750 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1751 vti.RegClass:$merge, 1752 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1753 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1754 (vti.Vector vti.RegClass:$rs1), 1755 (vti.Mask true_mask), 1756 VLOpFrag)), 1757 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1758 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1759 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1760 (vti.Mask true_mask), 1761 VLOpFrag)), 1762 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1763 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1764 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1765 (vti.Mask true_mask), 1766 VLOpFrag)), 1767 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1768 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1769 1770 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1771 (riscv_vrgather_vv_vl 1772 vti.RegClass:$rs2, 1773 vti.RegClass:$rs1, 1774 (vti.Mask true_mask), 1775 VLOpFrag), 1776 vti.RegClass:$merge, 1777 VLOpFrag)), 1778 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1779 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1780 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1781 1782 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1783 (riscv_vrgather_vx_vl 1784 vti.RegClass:$rs2, 1785 uimm5:$imm, 1786 (vti.Mask true_mask), 1787 VLOpFrag), 1788 vti.RegClass:$merge, 1789 VLOpFrag)), 1790 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1791 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1792 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1793 1794 // emul = lmul * 16 / sew 1795 defvar vlmul = vti.LMul; 1796 defvar octuple_lmul = vlmul.octuple; 1797 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1798 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1799 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1800 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1801 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1802 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1803 (ivti.Vector ivti.RegClass:$rs1), 1804 (vti.Mask true_mask), 1805 VLOpFrag)), 1806 (!cast<Instruction>(inst) 1807 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1808 1809 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1810 (riscv_vrgatherei16_vv_vl 1811 vti.RegClass:$rs2, 1812 (ivti.Vector ivti.RegClass:$rs1), 1813 (vti.Mask true_mask), 1814 VLOpFrag), 1815 vti.RegClass:$merge, 1816 VLOpFrag)), 1817 (!cast<Instruction>(inst#"_MASK") 1818 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1819 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1820 } 1821} 1822 1823} // Predicates = [HasVInstructions] 1824 1825let Predicates = [HasVInstructionsAnyF] in { 1826 1827// 17.2. Floating-Point Scalar Move Instructions 1828foreach vti = AllFloatVectors in { 1829 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1830 (vti.Scalar (fpimm0)), 1831 VLOpFrag)), 1832 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1833 vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>; 1834 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1835 vti.ScalarRegClass:$rs1, 1836 VLOpFrag)), 1837 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1838 vti.RegClass:$merge, 1839 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1840 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1841 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1842 (ivti.Vector vti.RegClass:$rs1), 1843 (vti.Mask true_mask), 1844 VLOpFrag)), 1845 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1846 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1847 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1848 (vti.Mask true_mask), 1849 VLOpFrag)), 1850 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1851 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1852 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1853 (vti.Mask true_mask), 1854 VLOpFrag)), 1855 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1856 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1857 1858 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1859 (riscv_vrgather_vv_vl 1860 vti.RegClass:$rs2, 1861 (ivti.Vector vti.RegClass:$rs1), 1862 (vti.Mask true_mask), 1863 VLOpFrag), 1864 vti.RegClass:$merge, 1865 VLOpFrag)), 1866 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1867 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1868 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1869 1870 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1871 (riscv_vrgather_vx_vl 1872 vti.RegClass:$rs2, 1873 uimm5:$imm, 1874 (vti.Mask true_mask), 1875 VLOpFrag), 1876 vti.RegClass:$merge, 1877 VLOpFrag)), 1878 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1879 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1880 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1881 1882 defvar vlmul = vti.LMul; 1883 defvar octuple_lmul = vlmul.octuple; 1884 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1885 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1886 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1887 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1888 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1889 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1890 (ivti.Vector ivti.RegClass:$rs1), 1891 (vti.Mask true_mask), 1892 VLOpFrag)), 1893 (!cast<Instruction>(inst) 1894 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1895 1896 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1897 (riscv_vrgatherei16_vv_vl 1898 vti.RegClass:$rs2, 1899 (ivti.Vector ivti.RegClass:$rs1), 1900 (vti.Mask true_mask), 1901 VLOpFrag), 1902 vti.RegClass:$merge, 1903 VLOpFrag)), 1904 (!cast<Instruction>(inst#"_MASK") 1905 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1906 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1907 } 1908} 1909 1910} // Predicates = [HasVInstructionsAnyF] 1911 1912//===----------------------------------------------------------------------===// 1913// Miscellaneous RISCVISD SDNodes 1914//===----------------------------------------------------------------------===// 1915 1916def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1917 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1918 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1919 1920def SDTRVVSlide : SDTypeProfile<1, 5, [ 1921 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1922 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1923]>; 1924def SDTRVVSlide1 : SDTypeProfile<1, 5, [ 1925 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>, 1926 SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, 1927 SDTCisVT<5, XLenVT> 1928]>; 1929 1930def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1931def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1932def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1933def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 1934 1935let Predicates = [HasVInstructions] in { 1936 1937foreach vti = AllIntegerVectors in { 1938 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1939 VLOpFrag)), 1940 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 1941 1942 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef), 1943 (vti.Vector vti.RegClass:$rs1), 1944 GPR:$rs2, (vti.Mask true_mask), 1945 VLOpFrag)), 1946 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1947 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1948 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rd), 1949 (vti.Vector vti.RegClass:$rs1), 1950 GPR:$rs2, (vti.Mask true_mask), 1951 VLOpFrag)), 1952 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX#"_TU") 1953 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1954 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector undef), 1955 (vti.Vector vti.RegClass:$rs1), 1956 GPR:$rs2, (vti.Mask true_mask), 1957 VLOpFrag)), 1958 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 1959 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1960 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rd), 1961 (vti.Vector vti.RegClass:$rs1), 1962 GPR:$rs2, (vti.Mask true_mask), 1963 VLOpFrag)), 1964 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX#"_TU") 1965 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1966} 1967 1968foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1969 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1970 (vti.Vector vti.RegClass:$rs1), 1971 uimm5:$rs2, (vti.Mask true_mask), 1972 VLOpFrag)), 1973 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1974 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1975 GPR:$vl, vti.Log2SEW)>; 1976 1977 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1978 (vti.Vector vti.RegClass:$rs1), 1979 GPR:$rs2, (vti.Mask true_mask), 1980 VLOpFrag)), 1981 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1982 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1983 GPR:$vl, vti.Log2SEW)>; 1984 1985 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1986 (vti.Vector vti.RegClass:$rs1), 1987 uimm5:$rs2, (vti.Mask true_mask), 1988 VLOpFrag)), 1989 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1990 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1991 GPR:$vl, vti.Log2SEW)>; 1992 1993 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1994 (vti.Vector vti.RegClass:$rs1), 1995 GPR:$rs2, (vti.Mask true_mask), 1996 VLOpFrag)), 1997 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1998 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1999 GPR:$vl, vti.Log2SEW)>; 2000} 2001 2002} // Predicates = [HasVInstructions] 2003