1//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// This file contains the required infrastructure and VL patterns to 10/// support code generation for the standard 'V' (Vector) extension, version 11/// version 1.0. 12/// 13/// This file is included from and depends upon RISCVInstrInfoVPseudos.td 14/// 15/// Note: the patterns for RVV intrinsics are found in 16/// RISCVInstrInfoVPseudos.td. 17/// 18//===----------------------------------------------------------------------===// 19 20//===----------------------------------------------------------------------===// 21// Helpers to define the VL patterns. 22//===----------------------------------------------------------------------===// 23 24def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 25 SDTCisSameAs<0, 2>, 26 SDTCisVec<0>, SDTCisInt<0>, 27 SDTCVecEltisVT<3, i1>, 28 SDTCisSameNumEltsAs<0, 3>, 29 SDTCisVT<4, XLenVT>]>; 30 31def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 32 SDTCisVec<0>, SDTCisFP<0>, 33 SDTCVecEltisVT<2, i1>, 34 SDTCisSameNumEltsAs<0, 2>, 35 SDTCisVT<3, XLenVT>]>; 36def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 37 SDTCisSameAs<0, 2>, 38 SDTCisVec<0>, SDTCisFP<0>, 39 SDTCVecEltisVT<3, i1>, 40 SDTCisSameNumEltsAs<0, 3>, 41 SDTCisVT<4, XLenVT>]>; 42 43def riscv_vmv_v_x_vl : SDNode<"RISCVISD::VMV_V_X_VL", 44 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisInt<0>, 45 SDTCisSameAs<0, 1>, 46 SDTCisVT<2, XLenVT>, 47 SDTCisVT<3, XLenVT>]>>; 48def riscv_vfmv_v_f_vl : SDNode<"RISCVISD::VFMV_V_F_VL", 49 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>, 50 SDTCisSameAs<0, 1>, 51 SDTCisEltOfVec<2, 0>, 52 SDTCisVT<3, XLenVT>]>>; 53def riscv_vmv_s_x_vl : SDNode<"RISCVISD::VMV_S_X_VL", 54 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 55 SDTCisInt<0>, 56 SDTCisVT<2, XLenVT>, 57 SDTCisVT<3, XLenVT>]>>; 58def riscv_vfmv_s_f_vl : SDNode<"RISCVISD::VFMV_S_F_VL", 59 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 60 SDTCisFP<0>, 61 SDTCisEltOfVec<2, 0>, 62 SDTCisVT<3, XLenVT>]>>; 63 64def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 65def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>; 66def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 67def riscv_mulhs_vl : SDNode<"RISCVISD::MULHS_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 68def riscv_mulhu_vl : SDNode<"RISCVISD::MULHU_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 69def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 70def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 71def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>; 72def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>; 73def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>; 74def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>; 75def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>; 76def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>; 77def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>; 78def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>; 79def riscv_smin_vl : SDNode<"RISCVISD::SMIN_VL", SDT_RISCVIntBinOp_VL>; 80def riscv_smax_vl : SDNode<"RISCVISD::SMAX_VL", SDT_RISCVIntBinOp_VL>; 81def riscv_umin_vl : SDNode<"RISCVISD::UMIN_VL", SDT_RISCVIntBinOp_VL>; 82def riscv_umax_vl : SDNode<"RISCVISD::UMAX_VL", SDT_RISCVIntBinOp_VL>; 83 84def riscv_saddsat_vl : SDNode<"RISCVISD::SADDSAT_VL", SDT_RISCVIntBinOp_VL>; 85def riscv_uaddsat_vl : SDNode<"RISCVISD::UADDSAT_VL", SDT_RISCVIntBinOp_VL>; 86def riscv_ssubsat_vl : SDNode<"RISCVISD::SSUBSAT_VL", SDT_RISCVIntBinOp_VL>; 87def riscv_usubsat_vl : SDNode<"RISCVISD::USUBSAT_VL", SDT_RISCVIntBinOp_VL>; 88 89def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 90def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>; 91def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>; 92def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>; 93def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>; 94def riscv_fabs_vl : SDNode<"RISCVISD::FABS_VL", SDT_RISCVFPUnOp_VL>; 95def riscv_fsqrt_vl : SDNode<"RISCVISD::FSQRT_VL", SDT_RISCVFPUnOp_VL>; 96def riscv_fcopysign_vl : SDNode<"RISCVISD::FCOPYSIGN_VL", SDT_RISCVFPBinOp_VL>; 97def riscv_fminnum_vl : SDNode<"RISCVISD::FMINNUM_VL", SDT_RISCVFPBinOp_VL>; 98def riscv_fmaxnum_vl : SDNode<"RISCVISD::FMAXNUM_VL", SDT_RISCVFPBinOp_VL>; 99 100def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>, 101 SDTCisSameAs<0, 2>, 102 SDTCisSameAs<0, 3>, 103 SDTCisVec<0>, SDTCisFP<0>, 104 SDTCVecEltisVT<4, i1>, 105 SDTCisSameNumEltsAs<0, 4>, 106 SDTCisVT<5, XLenVT>]>; 107def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL, [SDNPCommutative]>; 108 109def SDT_RISCVFPRoundOp_VL : SDTypeProfile<1, 3, [ 110 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>, SDTCisSameNumEltsAs<0, 1>, 111 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 112]>; 113def SDT_RISCVFPExtendOp_VL : SDTypeProfile<1, 3, [ 114 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>, SDTCisSameNumEltsAs<0, 1>, 115 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 116]>; 117 118def riscv_fpround_vl : SDNode<"RISCVISD::FP_ROUND_VL", SDT_RISCVFPRoundOp_VL>; 119def riscv_fpextend_vl : SDNode<"RISCVISD::FP_EXTEND_VL", SDT_RISCVFPExtendOp_VL>; 120def riscv_fncvt_rod_vl : SDNode<"RISCVISD::VFNCVT_ROD_VL", SDT_RISCVFPRoundOp_VL>; 121 122def SDT_RISCVFP2IOp_VL : SDTypeProfile<1, 3, [ 123 SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>, 124 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 125]>; 126def SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [ 127 SDTCisFP<0>, SDTCisInt<1>, SDTCisSameNumEltsAs<0, 1>, 128 SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> 129]>; 130 131def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; 132def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; 133def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 134def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; 135 136def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", 137 SDTypeProfile<1, 5, [SDTCVecEltisVT<0, i1>, 138 SDTCisVec<1>, 139 SDTCisSameNumEltsAs<0, 1>, 140 SDTCisSameAs<1, 2>, 141 SDTCisVT<3, OtherVT>, 142 SDTCisSameAs<0, 4>, 143 SDTCisVT<5, XLenVT>]>>; 144 145def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL", 146 SDTypeProfile<1, 4, [SDTCisVec<0>, 147 SDTCisSameAs<0, 1>, 148 SDTCisVT<2, XLenVT>, 149 SDTCVecEltisVT<3, i1>, 150 SDTCisSameNumEltsAs<0, 3>, 151 SDTCisVT<4, XLenVT>]>>; 152def riscv_vrgather_vv_vl : SDNode<"RISCVISD::VRGATHER_VV_VL", 153 SDTypeProfile<1, 4, [SDTCisVec<0>, 154 SDTCisSameAs<0, 1>, 155 SDTCisInt<2>, 156 SDTCisSameNumEltsAs<0, 2>, 157 SDTCisSameSizeAs<0, 2>, 158 SDTCVecEltisVT<3, i1>, 159 SDTCisSameNumEltsAs<0, 3>, 160 SDTCisVT<4, XLenVT>]>>; 161def riscv_vrgatherei16_vv_vl : SDNode<"RISCVISD::VRGATHEREI16_VV_VL", 162 SDTypeProfile<1, 4, [SDTCisVec<0>, 163 SDTCisSameAs<0, 1>, 164 SDTCisInt<2>, 165 SDTCVecEltisVT<2, i16>, 166 SDTCisSameNumEltsAs<0, 2>, 167 SDTCVecEltisVT<3, i1>, 168 SDTCisSameNumEltsAs<0, 3>, 169 SDTCisVT<4, XLenVT>]>>; 170 171def SDT_RISCVSelect_VL : SDTypeProfile<1, 4, [ 172 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameNumEltsAs<0, 1>, SDTCVecEltisVT<1, i1>, 173 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisVT<4, XLenVT> 174]>; 175 176def riscv_vselect_vl : SDNode<"RISCVISD::VSELECT_VL", SDT_RISCVSelect_VL>; 177def riscv_vp_merge_vl : SDNode<"RISCVISD::VP_MERGE_VL", SDT_RISCVSelect_VL>; 178 179def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, 180 SDTCisVT<1, XLenVT>]>; 181def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; 182def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; 183 184def SDT_RISCVMaskBinOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, 185 SDTCisSameAs<0, 2>, 186 SDTCVecEltisVT<0, i1>, 187 SDTCisVT<3, XLenVT>]>; 188def riscv_vmand_vl : SDNode<"RISCVISD::VMAND_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 189def riscv_vmor_vl : SDNode<"RISCVISD::VMOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 190def riscv_vmxor_vl : SDNode<"RISCVISD::VMXOR_VL", SDT_RISCVMaskBinOp_VL, [SDNPCommutative]>; 191 192def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; 193 194def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl), 195 (riscv_vmxor_vl node:$rs, true_mask, node:$vl)>; 196 197def riscv_vcpop_vl : SDNode<"RISCVISD::VCPOP_VL", 198 SDTypeProfile<1, 3, [SDTCisVT<0, XLenVT>, 199 SDTCisVec<1>, SDTCisInt<1>, 200 SDTCVecEltisVT<2, i1>, 201 SDTCisSameNumEltsAs<1, 2>, 202 SDTCisVT<3, XLenVT>]>>; 203 204def SDT_RISCVVEXTEND_VL : SDTypeProfile<1, 3, [SDTCisVec<0>, 205 SDTCisSameNumEltsAs<0, 1>, 206 SDTCisSameNumEltsAs<1, 2>, 207 SDTCVecEltisVT<2, i1>, 208 SDTCisVT<3, XLenVT>]>; 209def riscv_sext_vl : SDNode<"RISCVISD::VSEXT_VL", SDT_RISCVVEXTEND_VL>; 210def riscv_zext_vl : SDNode<"RISCVISD::VZEXT_VL", SDT_RISCVVEXTEND_VL>; 211 212def riscv_trunc_vector_vl : SDNode<"RISCVISD::TRUNCATE_VECTOR_VL", 213 SDTypeProfile<1, 3, [SDTCisVec<0>, 214 SDTCisSameNumEltsAs<0, 1>, 215 SDTCisSameNumEltsAs<0, 2>, 216 SDTCVecEltisVT<2, i1>, 217 SDTCisVT<3, XLenVT>]>>; 218 219def SDT_RISCVVWBinOp_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 220 SDTCisSameNumEltsAs<0, 1>, 221 SDTCisSameAs<1, 2>, 222 SDTCisSameNumEltsAs<1, 3>, 223 SDTCVecEltisVT<3, i1>, 224 SDTCisVT<4, XLenVT>]>; 225def riscv_vwmul_vl : SDNode<"RISCVISD::VWMUL_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 226def riscv_vwmulu_vl : SDNode<"RISCVISD::VWMULU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 227def riscv_vwmulsu_vl : SDNode<"RISCVISD::VWMULSU_VL", SDT_RISCVVWBinOp_VL>; 228def riscv_vwadd_vl : SDNode<"RISCVISD::VWADD_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 229def riscv_vwaddu_vl : SDNode<"RISCVISD::VWADDU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 230def riscv_vwsub_vl : SDNode<"RISCVISD::VWSUB_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 231def riscv_vwsubu_vl : SDNode<"RISCVISD::VWSUBU_VL", SDT_RISCVVWBinOp_VL, [SDNPCommutative]>; 232 233def SDT_RISCVVWBinOpW_VL : SDTypeProfile<1, 4, [SDTCisVec<0>, 234 SDTCisSameAs<0, 1>, 235 SDTCisSameNumEltsAs<1, 2>, 236 SDTCisOpSmallerThanOp<2, 1>, 237 SDTCisSameNumEltsAs<1, 3>, 238 SDTCVecEltisVT<3, i1>, 239 SDTCisVT<4, XLenVT>]>; 240def riscv_vwadd_w_vl : SDNode<"RISCVISD::VWADD_W_VL", SDT_RISCVVWBinOpW_VL>; 241def riscv_vwaddu_w_vl : SDNode<"RISCVISD::VWADDU_W_VL", SDT_RISCVVWBinOpW_VL>; 242def riscv_vwsub_w_vl : SDNode<"RISCVISD::VWSUB_W_VL", SDT_RISCVVWBinOpW_VL>; 243def riscv_vwsubu_w_vl : SDNode<"RISCVISD::VWSUBU_W_VL", SDT_RISCVVWBinOpW_VL>; 244 245def SDTRVVVecReduce : SDTypeProfile<1, 5, [ 246 SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>, 247 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<2, 4>, SDTCisVT<5, XLenVT> 248]>; 249 250def riscv_mul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 251 (riscv_mul_vl node:$A, node:$B, node:$C, 252 node:$D), [{ 253 return N->hasOneUse(); 254}]>; 255 256def riscv_vwmul_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 257 (riscv_vwmul_vl node:$A, node:$B, node:$C, 258 node:$D), [{ 259 return N->hasOneUse(); 260}]>; 261 262def riscv_vwmulu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 263 (riscv_vwmulu_vl node:$A, node:$B, node:$C, 264 node:$D), [{ 265 return N->hasOneUse(); 266}]>; 267 268def riscv_vwmulsu_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C, node:$D), 269 (riscv_vwmulsu_vl node:$A, node:$B, node:$C, 270 node:$D), [{ 271 return N->hasOneUse(); 272}]>; 273 274def riscv_sext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 275 (riscv_sext_vl node:$A, node:$B, node:$C), [{ 276 return N->hasOneUse(); 277}]>; 278 279def riscv_zext_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 280 (riscv_zext_vl node:$A, node:$B, node:$C), [{ 281 return N->hasOneUse(); 282}]>; 283 284def riscv_fpextend_vl_oneuse : PatFrag<(ops node:$A, node:$B, node:$C), 285 (riscv_fpextend_vl node:$A, node:$B, node:$C), [{ 286 return N->hasOneUse(); 287}]>; 288 289foreach kind = ["ADD", "UMAX", "SMAX", "UMIN", "SMIN", "AND", "OR", "XOR", 290 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in 291 def rvv_vecreduce_#kind#_vl : SDNode<"RISCVISD::VECREDUCE_"#kind#"_VL", SDTRVVVecReduce>; 292 293// Give explicit Complexity to prefer simm5/uimm5. 294def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>; 295def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [], [], 2>; 296def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [], [], 2>; 297def SplatPat_simm5_plus1 298 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [], [], 2>; 299def SplatPat_simm5_plus1_nonzero 300 : ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1NonZero", [], [], 2>; 301 302// Ignore the vl operand. 303def SplatFPOp : PatFrag<(ops node:$op), 304 (riscv_vfmv_v_f_vl undef, node:$op, srcvalue)>; 305 306def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; 307def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; 308def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; 309def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; 310 311multiclass VPatBinaryVL_V<SDNode vop, 312 string instruction_name, 313 string suffix, 314 ValueType result_type, 315 ValueType op1_type, 316 ValueType op2_type, 317 ValueType mask_type, 318 int sew, 319 LMULInfo vlmul, 320 VReg op1_reg_class, 321 VReg op2_reg_class> { 322 def : Pat<(result_type (vop 323 (op1_type op1_reg_class:$rs1), 324 (op2_type op2_reg_class:$rs2), 325 (mask_type V0), 326 VLOpFrag)), 327 (!cast<Instruction>(instruction_name#"_"#suffix#"_"# vlmul.MX#"_MASK") 328 (result_type (IMPLICIT_DEF)), 329 op1_reg_class:$rs1, 330 op2_reg_class:$rs2, 331 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 332} 333 334multiclass VPatBinaryVL_XI<SDNode vop, 335 string instruction_name, 336 string suffix, 337 ValueType result_type, 338 ValueType vop1_type, 339 ValueType vop2_type, 340 ValueType mask_type, 341 int sew, 342 LMULInfo vlmul, 343 VReg vop_reg_class, 344 ComplexPattern SplatPatKind, 345 DAGOperand xop_kind> { 346 def : Pat<(result_type (vop 347 (vop1_type vop_reg_class:$rs1), 348 (vop2_type (SplatPatKind (XLenVT xop_kind:$rs2))), 349 (mask_type V0), 350 VLOpFrag)), 351 (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK") 352 (result_type (IMPLICIT_DEF)), 353 vop_reg_class:$rs1, 354 xop_kind:$rs2, 355 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 356} 357 358multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> { 359 foreach vti = AllIntegerVectors in { 360 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 361 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 362 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 363 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 364 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 365 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 366 } 367} 368 369multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name, 370 Operand ImmType = simm5> 371 : VPatBinaryVL_VV_VX<vop, instruction_name> { 372 foreach vti = AllIntegerVectors in { 373 defm : VPatBinaryVL_XI<vop, instruction_name, "VI", 374 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 375 vti.Log2SEW, vti.LMul, vti.RegClass, 376 !cast<ComplexPattern>(SplatPat#_#ImmType), 377 ImmType>; 378 } 379} 380 381multiclass VPatBinaryWVL_VV_VX<SDNode vop, string instruction_name> { 382 foreach VtiToWti = AllWidenableIntVectors in { 383 defvar vti = VtiToWti.Vti; 384 defvar wti = VtiToWti.Wti; 385 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 386 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 387 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 388 defm : VPatBinaryVL_XI<vop, instruction_name, "VX", 389 wti.Vector, vti.Vector, vti.Vector, vti.Mask, 390 vti.Log2SEW, vti.LMul, vti.RegClass, SplatPat, GPR>; 391 } 392} 393multiclass VPatBinaryWVL_VV_VX_WV_WX<SDNode vop, SDNode vop_w, 394 string instruction_name> 395 : VPatBinaryWVL_VV_VX<vop, instruction_name> { 396 foreach VtiToWti = AllWidenableIntVectors in { 397 defvar vti = VtiToWti.Vti; 398 defvar wti = VtiToWti.Wti; 399 defm : VPatBinaryVL_V<vop_w, instruction_name, "WV", 400 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 401 vti.Log2SEW, vti.LMul, wti.RegClass, vti.RegClass>; 402 defm : VPatBinaryVL_XI<vop_w, instruction_name, "WX", 403 wti.Vector, wti.Vector, vti.Vector, vti.Mask, 404 vti.Log2SEW, vti.LMul, wti.RegClass, SplatPat, GPR>; 405 } 406} 407 408multiclass VPatBinaryVL_VF<SDNode vop, 409 string instruction_name, 410 ValueType result_type, 411 ValueType vop_type, 412 ValueType mask_type, 413 int sew, 414 LMULInfo vlmul, 415 VReg vop_reg_class, 416 RegisterClass scalar_reg_class> { 417 def : Pat<(result_type (vop (vop_type vop_reg_class:$rs1), 418 (vop_type (SplatFPOp scalar_reg_class:$rs2)), 419 (mask_type V0), 420 VLOpFrag)), 421 (!cast<Instruction>(instruction_name#"_"#vlmul.MX#"_MASK") 422 (result_type (IMPLICIT_DEF)), 423 vop_reg_class:$rs1, 424 scalar_reg_class:$rs2, 425 (mask_type V0), GPR:$vl, sew, TAIL_AGNOSTIC)>; 426} 427 428multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> { 429 foreach vti = AllFloatVectors in { 430 defm : VPatBinaryVL_V<vop, instruction_name, "VV", 431 vti.Vector, vti.Vector, vti.Vector, vti.Mask, 432 vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>; 433 defm : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix, 434 vti.Vector, vti.Vector, vti.Mask, vti.Log2SEW, 435 vti.LMul, vti.RegClass, vti.ScalarRegClass>; 436 } 437} 438 439multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> { 440 foreach fvti = AllFloatVectors in { 441 def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2), 442 fvti.RegClass:$rs1, 443 (fvti.Mask V0), 444 VLOpFrag)), 445 (!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_MASK") 446 (fvti.Vector (IMPLICIT_DEF)), 447 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 448 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW, TAIL_AGNOSTIC)>; 449 } 450} 451 452multiclass VPatIntegerSetCCVL_VV<VTypeInfo vti, string instruction_name, 453 CondCode cc> { 454 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 455 vti.RegClass:$rs2, cc, 456 (vti.Mask true_mask), 457 VLOpFrag)), 458 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 459 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 460 vti.Log2SEW)>; 461} 462 463// Inherits from VPatIntegerSetCCVL_VV and adds a pattern with operands swapped. 464multiclass VPatIntegerSetCCVL_VV_Swappable<VTypeInfo vti, string instruction_name, 465 CondCode cc, CondCode invcc> : 466 VPatIntegerSetCCVL_VV<vti, instruction_name, cc> { 467 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs2), 468 vti.RegClass:$rs1, invcc, 469 (vti.Mask true_mask), 470 VLOpFrag)), 471 (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) 472 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, 473 vti.Log2SEW)>; 474} 475 476multiclass VPatIntegerSetCCVL_VX_Swappable<VTypeInfo vti, string instruction_name, 477 CondCode cc, CondCode invcc> { 478 defvar instruction = !cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX); 479 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 480 (SplatPat (XLenVT GPR:$rs2)), cc, 481 (vti.Mask true_mask), 482 VLOpFrag)), 483 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 484 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat (XLenVT GPR:$rs2)), 485 (vti.Vector vti.RegClass:$rs1), invcc, 486 (vti.Mask true_mask), 487 VLOpFrag)), 488 (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 489} 490 491multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, 492 CondCode cc, CondCode invcc> { 493 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 494 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 495 (SplatPat_simm5 simm5:$rs2), cc, 496 (vti.Mask true_mask), 497 VLOpFrag)), 498 (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.Log2SEW)>; 499 def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), 500 (vti.Vector vti.RegClass:$rs1), invcc, 501 (vti.Mask true_mask), 502 VLOpFrag)), 503 (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.Log2SEW)>; 504} 505 506multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name, 507 CondCode cc, ComplexPattern splatpat_kind> { 508 defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); 509 def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), 510 (splatpat_kind simm5:$rs2), cc, 511 (vti.Mask true_mask), 512 VLOpFrag)), 513 (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2), 514 GPR:$vl, vti.Log2SEW)>; 515} 516 517multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, 518 string inst_name, 519 string swapped_op_inst_name> { 520 foreach fvti = AllFloatVectors in { 521 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 522 fvti.RegClass:$rs2, 523 cc, 524 (fvti.Mask true_mask), 525 VLOpFrag)), 526 (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX) 527 fvti.RegClass:$rs1, fvti.RegClass:$rs2, GPR:$vl, fvti.Log2SEW)>; 528 def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), 529 (SplatFPOp fvti.ScalarRegClass:$rs2), 530 cc, 531 (fvti.Mask true_mask), 532 VLOpFrag)), 533 (!cast<Instruction>(inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 534 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 535 GPR:$vl, fvti.Log2SEW)>; 536 def : Pat<(fvti.Mask (riscv_setcc_vl (SplatFPOp fvti.ScalarRegClass:$rs2), 537 (fvti.Vector fvti.RegClass:$rs1), 538 cc, 539 (fvti.Mask true_mask), 540 VLOpFrag)), 541 (!cast<Instruction>(swapped_op_inst_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX) 542 fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2, 543 GPR:$vl, fvti.Log2SEW)>; 544 } 545} 546 547multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix, 548 list <VTypeInfoToFraction> fraction_list> { 549 foreach vtiTofti = fraction_list in { 550 defvar vti = vtiTofti.Vti; 551 defvar fti = vtiTofti.Fti; 552 def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2), 553 true_mask, VLOpFrag)), 554 (!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX) 555 fti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 556 } 557} 558 559multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 560 foreach fvti = AllFloatVectors in { 561 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 562 def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 563 (fvti.Mask true_mask), 564 VLOpFrag)), 565 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 566 fvti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 567 } 568} 569 570multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 571 foreach fvti = AllFloatVectors in { 572 defvar ivti = GetIntVTypeInfo<fvti>.Vti; 573 def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 574 (ivti.Mask true_mask), 575 VLOpFrag)), 576 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 577 ivti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 578 } 579} 580 581multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 582 foreach fvtiToFWti = AllWidenableFloatVectors in { 583 defvar fvti = fvtiToFWti.Vti; 584 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 585 def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), 586 (fvti.Mask true_mask), 587 VLOpFrag)), 588 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 589 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 590 } 591} 592 593multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 594 foreach vtiToWti = AllWidenableIntToFloatVectors in { 595 defvar ivti = vtiToWti.Vti; 596 defvar fwti = vtiToWti.Wti; 597 def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), 598 (ivti.Mask true_mask), 599 VLOpFrag)), 600 (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX) 601 ivti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>; 602 } 603} 604 605multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> { 606 foreach vtiToWti = AllWidenableIntToFloatVectors in { 607 defvar vti = vtiToWti.Vti; 608 defvar fwti = vtiToWti.Wti; 609 def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1), 610 (fwti.Mask true_mask), 611 VLOpFrag)), 612 (!cast<Instruction>(instruction_name#"_"#vti.LMul.MX) 613 fwti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 614 } 615} 616 617multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> { 618 foreach fvtiToFWti = AllWidenableFloatVectors in { 619 defvar fvti = fvtiToFWti.Vti; 620 defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti; 621 def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), 622 (iwti.Mask true_mask), 623 VLOpFrag)), 624 (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX) 625 iwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 626 } 627} 628 629multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> { 630 foreach vti = !if(is_float, AllFloatVectors, AllIntegerVectors) in { 631 defvar vti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # vti.SEW # "M1"); 632 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 633 (vti.Mask true_mask), 634 VLOpFrag)), 635 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 636 (vti_m1.Vector VR:$merge), 637 (vti.Vector vti.RegClass:$rs1), 638 (vti_m1.Vector VR:$rs2), 639 GPR:$vl, vti.Log2SEW)>; 640 641 def: Pat<(vti_m1.Vector (vop (vti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), VR:$rs2, 642 (vti.Mask V0), VLOpFrag)), 643 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 644 (vti_m1.Vector VR:$merge), 645 (vti.Vector vti.RegClass:$rs1), 646 (vti_m1.Vector VR:$rs2), 647 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 648 } 649} 650 651multiclass VPatBinarySDNodeExt_V_WV_WX<SDNode op, PatFrags extop, string instruction_name> { 652 foreach vti = AllWidenableIntVectors in { 653 def : Pat< 654 (vti.Vti.Vector 655 (riscv_trunc_vector_vl 656 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 657 (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))), 658 (riscv_vmset_vl VLOpFrag), 659 VLOpFrag)), 660 (!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX) 661 vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1, 662 vti.Vti.AVL, vti.Vti.Log2SEW)>; 663 def : Pat< 664 (vti.Vti.Vector 665 (riscv_trunc_vector_vl 666 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 667 (vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))), 668 (riscv_vmset_vl VLOpFrag), 669 VLOpFrag)), 670 (!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX) 671 vti.Wti.RegClass:$rs2, GPR:$rs1, 672 vti.Vti.AVL, vti.Vti.Log2SEW)>; 673 } 674} 675 676multiclass VPatBinarySDNode_V_WV_WX_WI<SDNode op, string instruction_name> { 677 defm : VPatBinarySDNodeExt_V_WV_WX<op, sext_oneuse, instruction_name>; 678 defm : VPatBinarySDNodeExt_V_WV_WX<op, zext_oneuse, instruction_name>; 679 foreach vti = AllWidenableIntVectors in { 680 def : Pat< 681 (vti.Vti.Vector 682 (riscv_trunc_vector_vl 683 (op (vti.Wti.Vector vti.Wti.RegClass:$rs2), 684 (vti.Wti.Vector (SplatPat_uimm5 uimm5:$rs1))), 685 (riscv_vmset_vl VLOpFrag), 686 VLOpFrag)), 687 (!cast<Instruction>(instruction_name#"_WI_"#vti.Vti.LMul.MX) 688 vti.Wti.RegClass:$rs2, uimm5:$rs1, 689 vti.Vti.AVL, vti.Vti.Log2SEW)>; 690 } 691} 692 693multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 694 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 695 defvar vti = vtiToWti.Vti; 696 defvar wti = vtiToWti.Wti; 697 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 698 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 699 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 700 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 701 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 702 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 703 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 704 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 705 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1))), 706 VR:$rs2, (vti.Mask V0), VLOpFrag)), 707 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 708 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 709 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 710 } 711} 712 713multiclass VPatWidenReductionVL_Ext_VL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { 714 foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { 715 defvar vti = vtiToWti.Vti; 716 defvar wti = vtiToWti.Wti; 717 defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); 718 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 719 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 720 VR:$rs2, (vti.Mask true_mask), VLOpFrag)), 721 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX) 722 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 723 (wti_m1.Vector VR:$rs2), GPR:$vl, vti.Log2SEW)>; 724 def: Pat<(wti_m1.Vector (vop (wti_m1.Vector VR:$merge), 725 (wti.Vector (extop (vti.Vector vti.RegClass:$rs1), (vti.Mask true_mask), VLOpFrag)), 726 VR:$rs2, (vti.Mask V0), VLOpFrag)), 727 (!cast<Instruction>(instruction_name#"_VS_"#vti.LMul.MX#"_MASK") 728 (wti_m1.Vector VR:$merge), (vti.Vector vti.RegClass:$rs1), 729 (wti_m1.Vector VR:$rs2), (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 730 } 731} 732 733//===----------------------------------------------------------------------===// 734// Patterns. 735//===----------------------------------------------------------------------===// 736 737let Predicates = [HasVInstructions] in { 738 739// 12.1. Vector Single-Width Integer Add and Subtract 740defm : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">; 741defm : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">; 742// Handle VRSUB specially since it's the only integer binary op with reversed 743// pattern operands 744foreach vti = AllIntegerVectors in { 745 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat (XLenVT GPR:$rs2))), 746 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 747 VLOpFrag), 748 (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX#"_MASK") 749 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2, 750 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 751 def : Pat<(riscv_sub_vl (vti.Vector (SplatPat_simm5 simm5:$rs2)), 752 (vti.Vector vti.RegClass:$rs1), (vti.Mask V0), 753 VLOpFrag), 754 (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX#"_MASK") 755 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, simm5:$rs2, 756 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 757} 758 759// 12.2. Vector Widening Integer Add/Subtract 760defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwadd_vl, riscv_vwadd_w_vl, "PseudoVWADD">; 761defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwaddu_vl, riscv_vwaddu_w_vl, "PseudoVWADDU">; 762defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsub_vl, riscv_vwsub_w_vl, "PseudoVWSUB">; 763defm : VPatBinaryWVL_VV_VX_WV_WX<riscv_vwsubu_vl, riscv_vwsubu_w_vl, "PseudoVWSUBU">; 764 765// 12.3. Vector Integer Extension 766defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF2", 767 AllFractionableVF2IntVectors>; 768defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF2", 769 AllFractionableVF2IntVectors>; 770defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF4", 771 AllFractionableVF4IntVectors>; 772defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF4", 773 AllFractionableVF4IntVectors>; 774defm : VPatExtendSDNode_V_VL<riscv_zext_vl, "PseudoVZEXT", "VF8", 775 AllFractionableVF8IntVectors>; 776defm : VPatExtendSDNode_V_VL<riscv_sext_vl, "PseudoVSEXT", "VF8", 777 AllFractionableVF8IntVectors>; 778 779// 12.5. Vector Bitwise Logical Instructions 780defm : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">; 781defm : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">; 782defm : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">; 783 784// 12.6. Vector Single-Width Bit Shift Instructions 785defm : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>; 786defm : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>; 787defm : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>; 788 789foreach vti = AllIntegerVectors in { 790 // Emit shift by 1 as an add since it might be faster. 791 def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), 792 (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)), 793 (vti.Mask true_mask), 794 VLOpFrag), 795 (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) 796 vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 797} 798 799// 12.7. Vector Narrowing Integer Right Shift Instructions 800defm : VPatBinarySDNode_V_WV_WX_WI<srl, "PseudoVNSRL">; 801defm : VPatBinarySDNode_V_WV_WX_WI<sra, "PseudoVNSRA">; 802 803foreach vtiTowti = AllWidenableIntVectors in { 804 defvar vti = vtiTowti.Vti; 805 defvar wti = vtiTowti.Wti; 806 def : Pat<(vti.Vector (riscv_trunc_vector_vl (wti.Vector wti.RegClass:$rs1), 807 (vti.Mask true_mask), 808 VLOpFrag)), 809 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 810 wti.RegClass:$rs1, X0, GPR:$vl, vti.Log2SEW)>; 811 812 def : Pat<(vti.Vector 813 (riscv_trunc_vector_vl 814 (wti.Vector 815 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 816 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 817 (!cast<Instruction>("PseudoVNSRA_WX_"#vti.LMul.MX) 818 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 819 def : Pat<(vti.Vector 820 (riscv_trunc_vector_vl 821 (wti.Vector 822 (riscv_sra_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 823 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 824 (!cast<Instruction>("PseudoVNSRA_WI_"#vti.LMul.MX) 825 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 826 827 def : Pat<(vti.Vector 828 (riscv_trunc_vector_vl 829 (wti.Vector 830 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), 831 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 832 (!cast<Instruction>("PseudoVNSRL_WX_"#vti.LMul.MX) 833 wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 834 def : Pat<(vti.Vector 835 (riscv_trunc_vector_vl 836 (wti.Vector 837 (riscv_srl_vl wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), 838 true_mask, VLOpFrag)), true_mask, VLOpFrag)), 839 (!cast<Instruction>("PseudoVNSRL_WI_"#vti.LMul.MX) 840 wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; 841} 842 843// 12.8. Vector Integer Comparison Instructions 844foreach vti = AllIntegerVectors in { 845 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSEQ", SETEQ>; 846 defm : VPatIntegerSetCCVL_VV<vti, "PseudoVMSNE", SETNE>; 847 848 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 849 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 850 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 851 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 852 853 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 854 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 855 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; 856 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; 857 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 858 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 859 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 860 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 861 // There is no VMSGE(U)_VX instruction 862 863 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; 864 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; 865 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; 866 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; 867 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; 868 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; 869 870 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT, 871 SplatPat_simm5_plus1_nonzero>; 872 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT, 873 SplatPat_simm5_plus1_nonzero>; 874 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE, 875 SplatPat_simm5_plus1>; 876 defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGTU", SETUGE, 877 SplatPat_simm5_plus1_nonzero>; 878} // foreach vti = AllIntegerVectors 879 880// 12.9. Vector Integer Min/Max Instructions 881defm : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; 882defm : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; 883defm : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; 884defm : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; 885 886// 12.10. Vector Single-Width Integer Multiply Instructions 887defm : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">; 888defm : VPatBinaryVL_VV_VX<riscv_mulhs_vl, "PseudoVMULH">; 889defm : VPatBinaryVL_VV_VX<riscv_mulhu_vl, "PseudoVMULHU">; 890 891// 12.11. Vector Integer Divide Instructions 892defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">; 893defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">; 894defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; 895defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; 896 897// 12.12. Vector Widening Integer Multiply Instructions 898defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">; 899defm : VPatBinaryWVL_VV_VX<riscv_vwmulu_vl, "PseudoVWMULU">; 900defm : VPatBinaryWVL_VV_VX<riscv_vwmulsu_vl, "PseudoVWMULSU">; 901 902// 12.13 Vector Single-Width Integer Multiply-Add Instructions 903foreach vti = AllIntegerVectors in { 904 // NOTE: We choose VMADD because it has the most commuting freedom. So it 905 // works best with how TwoAddressInstructionPass tries commuting. 906 defvar suffix = vti.LMul.MX; 907 def : Pat<(vti.Vector 908 (riscv_add_vl vti.RegClass:$rs2, 909 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 910 vti.RegClass:$rd, 911 (vti.Mask true_mask), VLOpFrag), 912 (vti.Mask true_mask), VLOpFrag)), 913 (!cast<Instruction>("PseudoVMADD_VV_"# suffix) 914 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 915 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 916 def : Pat<(vti.Vector 917 (riscv_sub_vl vti.RegClass:$rs2, 918 (riscv_mul_vl_oneuse vti.RegClass:$rs1, 919 vti.RegClass:$rd, 920 (vti.Mask true_mask), VLOpFrag), 921 (vti.Mask true_mask), VLOpFrag)), 922 (!cast<Instruction>("PseudoVNMSUB_VV_"# suffix) 923 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 924 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 925 926 // The choice of VMADD here is arbitrary, vmadd.vx and vmacc.vx are equally 927 // commutable. 928 def : Pat<(vti.Vector 929 (riscv_add_vl vti.RegClass:$rs2, 930 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 931 vti.RegClass:$rd, 932 (vti.Mask true_mask), VLOpFrag), 933 (vti.Mask true_mask), VLOpFrag)), 934 (!cast<Instruction>("PseudoVMADD_VX_" # suffix) 935 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 936 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 937 def : Pat<(vti.Vector 938 (riscv_sub_vl vti.RegClass:$rs2, 939 (riscv_mul_vl_oneuse (SplatPat XLenVT:$rs1), 940 vti.RegClass:$rd, 941 (vti.Mask true_mask), 942 VLOpFrag), 943 (vti.Mask true_mask), VLOpFrag)), 944 (!cast<Instruction>("PseudoVNMSUB_VX_" # suffix) 945 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 946 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 947} 948 949// 12.14. Vector Widening Integer Multiply-Add Instructions 950foreach vtiTowti = AllWidenableIntVectors in { 951 defvar vti = vtiTowti.Vti; 952 defvar wti = vtiTowti.Wti; 953 def : Pat<(wti.Vector 954 (riscv_add_vl wti.RegClass:$rd, 955 (riscv_vwmul_vl_oneuse vti.RegClass:$rs1, 956 (vti.Vector vti.RegClass:$rs2), 957 (vti.Mask true_mask), VLOpFrag), 958 (vti.Mask true_mask), VLOpFrag)), 959 (!cast<Instruction>("PseudoVWMACC_VV_" # vti.LMul.MX) 960 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 961 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 962 def : Pat<(wti.Vector 963 (riscv_add_vl wti.RegClass:$rd, 964 (riscv_vwmulu_vl_oneuse vti.RegClass:$rs1, 965 (vti.Vector vti.RegClass:$rs2), 966 (vti.Mask true_mask), VLOpFrag), 967 (vti.Mask true_mask), VLOpFrag)), 968 (!cast<Instruction>("PseudoVWMACCU_VV_" # vti.LMul.MX) 969 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 970 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 971 def : Pat<(wti.Vector 972 (riscv_add_vl wti.RegClass:$rd, 973 (riscv_vwmulsu_vl_oneuse vti.RegClass:$rs1, 974 (vti.Vector vti.RegClass:$rs2), 975 (vti.Mask true_mask), VLOpFrag), 976 (vti.Mask true_mask), VLOpFrag)), 977 (!cast<Instruction>("PseudoVWMACCSU_VV_" # vti.LMul.MX) 978 wti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 979 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 980 981 def : Pat<(wti.Vector 982 (riscv_add_vl wti.RegClass:$rd, 983 (riscv_vwmul_vl_oneuse (SplatPat XLenVT:$rs1), 984 (vti.Vector vti.RegClass:$rs2), 985 (vti.Mask true_mask), VLOpFrag), 986 (vti.Mask true_mask), VLOpFrag)), 987 (!cast<Instruction>("PseudoVWMACC_VX_" # vti.LMul.MX) 988 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 989 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 990 def : Pat<(wti.Vector 991 (riscv_add_vl wti.RegClass:$rd, 992 (riscv_vwmulu_vl_oneuse (SplatPat XLenVT:$rs1), 993 (vti.Vector vti.RegClass:$rs2), 994 (vti.Mask true_mask), VLOpFrag), 995 (vti.Mask true_mask), VLOpFrag)), 996 (!cast<Instruction>("PseudoVWMACCU_VX_" # vti.LMul.MX) 997 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 998 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 999 def : Pat<(wti.Vector 1000 (riscv_add_vl wti.RegClass:$rd, 1001 (riscv_vwmulsu_vl_oneuse (SplatPat XLenVT:$rs1), 1002 (vti.Vector vti.RegClass:$rs2), 1003 (vti.Mask true_mask), VLOpFrag), 1004 (vti.Mask true_mask), VLOpFrag)), 1005 (!cast<Instruction>("PseudoVWMACCSU_VX_" # vti.LMul.MX) 1006 wti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1007 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1008 def : Pat<(wti.Vector 1009 (riscv_add_vl wti.RegClass:$rd, 1010 (riscv_vwmulsu_vl_oneuse (vti.Vector vti.RegClass:$rs1), 1011 (SplatPat XLenVT:$rs2), 1012 (vti.Mask true_mask), VLOpFrag), 1013 (vti.Mask true_mask), VLOpFrag)), 1014 (!cast<Instruction>("PseudoVWMACCUS_VX_" # vti.LMul.MX) 1015 wti.RegClass:$rd, vti.ScalarRegClass:$rs2, vti.RegClass:$rs1, 1016 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1017} 1018 1019// 12.15. Vector Integer Merge Instructions 1020foreach vti = AllIntegerVectors in { 1021 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1022 vti.RegClass:$rs1, 1023 vti.RegClass:$rs2, 1024 VLOpFrag)), 1025 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX) 1026 vti.RegClass:$rs2, vti.RegClass:$rs1, (vti.Mask V0), 1027 GPR:$vl, vti.Log2SEW)>; 1028 1029 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1030 (SplatPat XLenVT:$rs1), 1031 vti.RegClass:$rs2, 1032 VLOpFrag)), 1033 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX) 1034 vti.RegClass:$rs2, GPR:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1035 1036 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1037 (SplatPat_simm5 simm5:$rs1), 1038 vti.RegClass:$rs2, 1039 VLOpFrag)), 1040 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX) 1041 vti.RegClass:$rs2, simm5:$rs1, (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1042 1043 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1044 vti.RegClass:$rs1, 1045 vti.RegClass:$rs2, 1046 VLOpFrag)), 1047 (!cast<Instruction>("PseudoVMERGE_VVM_"#vti.LMul.MX#"_TU") 1048 vti.RegClass:$rs2, vti.RegClass:$rs2, vti.RegClass:$rs1, 1049 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1050 1051 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1052 (SplatPat XLenVT:$rs1), 1053 vti.RegClass:$rs2, 1054 VLOpFrag)), 1055 (!cast<Instruction>("PseudoVMERGE_VXM_"#vti.LMul.MX#"_TU") 1056 vti.RegClass:$rs2, vti.RegClass:$rs2, GPR:$rs1, 1057 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1058 1059 def : Pat<(vti.Vector (riscv_vp_merge_vl (vti.Mask V0), 1060 (SplatPat_simm5 simm5:$rs1), 1061 vti.RegClass:$rs2, 1062 VLOpFrag)), 1063 (!cast<Instruction>("PseudoVMERGE_VIM_"#vti.LMul.MX#"_TU") 1064 vti.RegClass:$rs2, vti.RegClass:$rs2, simm5:$rs1, 1065 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>; 1066} 1067 1068// 12.16. Vector Integer Move Instructions 1069foreach vti = AllIntegerVectors in { 1070 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), GPR:$rs2, VLOpFrag)), 1071 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) 1072 $rs2, GPR:$vl, vti.Log2SEW)>; 1073 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, GPR:$rs2, VLOpFrag)), 1074 (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX#"_TU") 1075 $passthru, $rs2, GPR:$vl, vti.Log2SEW)>; 1076 defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5"); 1077 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), (ImmPat XLenVT:$imm5), 1078 VLOpFrag)), 1079 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX) 1080 XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1081 def : Pat<(vti.Vector (riscv_vmv_v_x_vl vti.Vector:$passthru, (ImmPat XLenVT:$imm5), 1082 VLOpFrag)), 1083 (!cast<Instruction>("PseudoVMV_V_I_"#vti.LMul.MX#"_TU") 1084 $passthru, XLenVT:$imm5, GPR:$vl, vti.Log2SEW)>; 1085} 1086 1087// 12.1. Vector Single-Width Saturating Add and Subtract 1088defm : VPatBinaryVL_VV_VX_VI<riscv_saddsat_vl, "PseudoVSADD">; 1089defm : VPatBinaryVL_VV_VX_VI<riscv_uaddsat_vl, "PseudoVSADDU">; 1090defm : VPatBinaryVL_VV_VX<riscv_ssubsat_vl, "PseudoVSSUB">; 1091defm : VPatBinaryVL_VV_VX<riscv_usubsat_vl, "PseudoVSSUBU">; 1092 1093} // Predicates = [HasVInstructions] 1094 1095// 15.1. Vector Single-Width Integer Reduction Instructions 1096let Predicates = [HasVInstructions] in { 1097defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>; 1098defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>; 1099defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>; 1100defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>; 1101defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>; 1102defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>; 1103defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>; 1104defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>; 1105 1106// 15.2. Vector Widening Integer Reduction Instructions 1107defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1108defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1109defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", /*is_float*/0>; 1110defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1111defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", /*is_float*/0>; 1112} // Predicates = [HasVInstructions] 1113 1114// 15.3. Vector Single-Width Floating-Point Reduction Instructions 1115let Predicates = [HasVInstructionsAnyF] in { 1116defm : VPatReductionVL<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>; 1117defm : VPatReductionVL<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>; 1118defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>; 1119defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>; 1120 1121// 15.4. Vector Widening Floating-Point Reduction Instructions 1122defm : VPatWidenReductionVL<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1123defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_SEQ_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDOSUM", /*is_float*/1>; 1124defm : VPatWidenReductionVL<rvv_vecreduce_FADD_vl, fpext_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1125defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_FADD_vl, riscv_fpextend_vl_oneuse, "PseudoVFWREDUSUM", /*is_float*/1>; 1126} // Predicates = [HasVInstructionsAnyF] 1127 1128let Predicates = [HasVInstructionsAnyF] in { 1129 1130// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions 1131defm : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">; 1132defm : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">; 1133defm : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">; 1134 1135// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions 1136defm : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">; 1137defm : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">; 1138defm : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">; 1139 1140// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. 1141foreach vti = AllFloatVectors in { 1142 // NOTE: We choose VFMADD because it has the most commuting freedom. So it 1143 // works best with how TwoAddressInstructionPass tries commuting. 1144 defvar suffix = vti.LMul.MX; 1145 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1146 vti.RegClass:$rs2, (vti.Mask true_mask), 1147 VLOpFrag)), 1148 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix) 1149 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1150 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1151 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1152 vti.RegClass:$rs2, (vti.Mask V0), 1153 VLOpFrag)), 1154 (!cast<Instruction>("PseudoVFMADD_VV_"# suffix #"_MASK") 1155 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1156 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>; 1157 1158 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1159 (riscv_fneg_vl vti.RegClass:$rs2, 1160 (vti.Mask true_mask), 1161 VLOpFrag), 1162 (vti.Mask true_mask), 1163 VLOpFrag)), 1164 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) 1165 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1166 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1167 def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rs1, vti.RegClass:$rd, 1168 (riscv_fneg_vl vti.RegClass:$rs2, 1169 (vti.Mask srcvalue), 1170 VLOpFrag), 1171 (vti.Mask V0), 1172 VLOpFrag)), 1173 (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix #"_MASK") 1174 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1175 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1176 1177 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1178 (vti.Mask srcvalue), 1179 VLOpFrag), 1180 vti.RegClass:$rd, 1181 (riscv_fneg_vl vti.RegClass:$rs2, 1182 (vti.Mask srcvalue), 1183 VLOpFrag), 1184 (vti.Mask true_mask), 1185 VLOpFrag)), 1186 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) 1187 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1188 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1189 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1190 (vti.Mask srcvalue), 1191 VLOpFrag), 1192 vti.RegClass:$rd, 1193 (riscv_fneg_vl vti.RegClass:$rs2, 1194 (vti.Mask srcvalue), 1195 VLOpFrag), 1196 (vti.Mask V0), 1197 VLOpFrag)), 1198 (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix #"_MASK") 1199 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1200 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1201 1202 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1203 (vti.Mask srcvalue), 1204 VLOpFrag), 1205 vti.RegClass:$rd, vti.RegClass:$rs2, 1206 (vti.Mask true_mask), 1207 VLOpFrag)), 1208 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) 1209 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1210 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1211 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl vti.RegClass:$rs1, 1212 (vti.Mask srcvalue), 1213 VLOpFrag), 1214 vti.RegClass:$rd, vti.RegClass:$rs2, 1215 (vti.Mask V0), 1216 VLOpFrag)), 1217 (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix #"_MASK") 1218 vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2, 1219 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1220 1221 // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally 1222 // commutable. 1223 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1224 vti.RegClass:$rd, vti.RegClass:$rs2, 1225 (vti.Mask true_mask), 1226 VLOpFrag)), 1227 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix) 1228 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1229 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1230 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1231 vti.RegClass:$rd, vti.RegClass:$rs2, 1232 (vti.Mask V0), 1233 VLOpFrag)), 1234 (!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1235 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1236 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_UNDISTURBED)>; 1237 1238 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1239 vti.RegClass:$rd, 1240 (riscv_fneg_vl vti.RegClass:$rs2, 1241 (vti.Mask srcvalue), 1242 VLOpFrag), 1243 (vti.Mask true_mask), 1244 VLOpFrag)), 1245 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1246 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1247 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1248 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1249 vti.RegClass:$rd, 1250 (riscv_fneg_vl vti.RegClass:$rs2, 1251 (vti.Mask srcvalue), 1252 VLOpFrag), 1253 (vti.Mask V0), 1254 VLOpFrag)), 1255 (!cast<Instruction>("PseudoVFMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1256 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1257 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1258 1259 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1260 (riscv_fneg_vl vti.RegClass:$rd, 1261 (vti.Mask srcvalue), 1262 VLOpFrag), 1263 (riscv_fneg_vl vti.RegClass:$rs2, 1264 (vti.Mask srcvalue), 1265 VLOpFrag), 1266 (vti.Mask true_mask), 1267 VLOpFrag)), 1268 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1269 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1270 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1271 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1272 (riscv_fneg_vl vti.RegClass:$rd, 1273 (vti.Mask srcvalue), 1274 VLOpFrag), 1275 (riscv_fneg_vl vti.RegClass:$rs2, 1276 (vti.Mask srcvalue), 1277 VLOpFrag), 1278 (vti.Mask V0), 1279 VLOpFrag)), 1280 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1281 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1282 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1283 1284 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1285 (riscv_fneg_vl vti.RegClass:$rd, 1286 (vti.Mask srcvalue), 1287 VLOpFrag), 1288 vti.RegClass:$rs2, 1289 (vti.Mask true_mask), 1290 VLOpFrag)), 1291 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1292 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1293 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1294 def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1295 (riscv_fneg_vl vti.RegClass:$rd, 1296 (vti.Mask srcvalue), 1297 VLOpFrag), 1298 vti.RegClass:$rs2, 1299 (vti.Mask V0), 1300 VLOpFrag)), 1301 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1302 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1303 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1304 1305 // The splat might be negated. 1306 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1307 (vti.Mask srcvalue), 1308 VLOpFrag), 1309 vti.RegClass:$rd, 1310 (riscv_fneg_vl vti.RegClass:$rs2, 1311 (vti.Mask srcvalue), 1312 VLOpFrag), 1313 (vti.Mask true_mask), 1314 VLOpFrag)), 1315 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix) 1316 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1317 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1318 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1319 (vti.Mask srcvalue), 1320 VLOpFrag), 1321 vti.RegClass:$rd, 1322 (riscv_fneg_vl vti.RegClass:$rs2, 1323 (vti.Mask srcvalue), 1324 VLOpFrag), 1325 (vti.Mask V0), 1326 VLOpFrag)), 1327 (!cast<Instruction>("PseudoVFNMADD_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1328 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1329 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1330 1331 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1332 (vti.Mask srcvalue), 1333 VLOpFrag), 1334 vti.RegClass:$rd, vti.RegClass:$rs2, 1335 (vti.Mask true_mask), 1336 VLOpFrag)), 1337 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix) 1338 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1339 GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1340 def : Pat<(vti.Vector (riscv_fma_vl (riscv_fneg_vl (SplatFPOp vti.ScalarRegClass:$rs1), 1341 (vti.Mask srcvalue), 1342 VLOpFrag), 1343 vti.RegClass:$rd, vti.RegClass:$rs2, 1344 (vti.Mask V0), 1345 VLOpFrag)), 1346 (!cast<Instruction>("PseudoVFNMSUB_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") 1347 vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, 1348 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1349} 1350 1351// 14.11. Vector Floating-Point MIN/MAX Instructions 1352defm : VPatBinaryFPVL_VV_VF<riscv_fminnum_vl, "PseudoVFMIN">; 1353defm : VPatBinaryFPVL_VV_VF<riscv_fmaxnum_vl, "PseudoVFMAX">; 1354 1355// 14.13. Vector Floating-Point Compare Instructions 1356defm : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1357defm : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; 1358 1359defm : VPatFPSetCCVL_VV_VF_FV<SETNE, "PseudoVMFNE", "PseudoVMFNE">; 1360defm : VPatFPSetCCVL_VV_VF_FV<SETUNE, "PseudoVMFNE", "PseudoVMFNE">; 1361 1362defm : VPatFPSetCCVL_VV_VF_FV<SETLT, "PseudoVMFLT", "PseudoVMFGT">; 1363defm : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">; 1364 1365defm : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; 1366defm : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; 1367 1368foreach vti = AllFloatVectors in { 1369 // 14.8. Vector Floating-Point Square-Root Instruction 1370 def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), 1371 VLOpFrag), 1372 (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX) 1373 vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1374 1375 // 14.12. Vector Floating-Point Sign-Injection Instructions 1376 def : Pat<(riscv_fabs_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask), 1377 VLOpFrag), 1378 (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) 1379 vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.Log2SEW)>; 1380 // Handle fneg with VFSGNJN using the same input for both operands. 1381 def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask V0), 1382 VLOpFrag), 1383 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX #"_MASK") 1384 (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs, 1385 vti.RegClass:$rs, (vti.Mask V0), GPR:$vl, vti.Log2SEW, 1386 TAIL_AGNOSTIC)>; 1387 1388 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1389 (vti.Vector vti.RegClass:$rs2), 1390 (vti.Mask true_mask), 1391 VLOpFrag), 1392 (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) 1393 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1394 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1395 (riscv_fneg_vl vti.RegClass:$rs2, 1396 (vti.Mask true_mask), 1397 VLOpFrag), 1398 (vti.Mask true_mask), 1399 VLOpFrag), 1400 (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) 1401 vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1402 1403 def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), 1404 (SplatFPOp vti.ScalarRegClass:$rs2), 1405 (vti.Mask true_mask), 1406 VLOpFrag), 1407 (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX) 1408 vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>; 1409} 1410 1411foreach fvti = AllFloatVectors in { 1412 // Floating-point vselects: 1413 // 12.15. Vector Integer Merge Instructions 1414 // 14.15. Vector Floating-Point Merge Instruction 1415 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1416 fvti.RegClass:$rs1, 1417 fvti.RegClass:$rs2, 1418 VLOpFrag)), 1419 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX) 1420 fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1421 GPR:$vl, fvti.Log2SEW)>; 1422 1423 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1424 (SplatFPOp fvti.ScalarRegClass:$rs1), 1425 fvti.RegClass:$rs2, 1426 VLOpFrag)), 1427 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX) 1428 fvti.RegClass:$rs2, 1429 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1430 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1431 1432 def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask V0), 1433 (SplatFPOp (fvti.Scalar fpimm0)), 1434 fvti.RegClass:$rs2, 1435 VLOpFrag)), 1436 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX) 1437 fvti.RegClass:$rs2, 0, (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1438 1439 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1440 fvti.RegClass:$rs1, 1441 fvti.RegClass:$rs2, 1442 VLOpFrag)), 1443 (!cast<Instruction>("PseudoVMERGE_VVM_"#fvti.LMul.MX#"_TU") 1444 fvti.RegClass:$rs2, fvti.RegClass:$rs2, fvti.RegClass:$rs1, (fvti.Mask V0), 1445 GPR:$vl, fvti.Log2SEW)>; 1446 1447 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1448 (SplatFPOp fvti.ScalarRegClass:$rs1), 1449 fvti.RegClass:$rs2, 1450 VLOpFrag)), 1451 (!cast<Instruction>("PseudoVFMERGE_V"#fvti.ScalarSuffix#"M_"#fvti.LMul.MX#"_TU") 1452 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 1453 (fvti.Scalar fvti.ScalarRegClass:$rs1), 1454 (fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>; 1455 1456 def : Pat<(fvti.Vector (riscv_vp_merge_vl (fvti.Mask V0), 1457 (SplatFPOp (fvti.Scalar fpimm0)), 1458 fvti.RegClass:$rs2, 1459 VLOpFrag)), 1460 (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX#"_TU") 1461 fvti.RegClass:$rs2, fvti.RegClass:$rs2, 0, (fvti.Mask V0), 1462 GPR:$vl, fvti.Log2SEW)>; 1463 1464 // 14.16. Vector Floating-Point Move Instruction 1465 // If we're splatting fpimm0, use vmv.v.x vd, x0. 1466 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1467 (fvti.Vector undef), (fvti.Scalar (fpimm0)), VLOpFrag)), 1468 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX) 1469 0, GPR:$vl, fvti.Log2SEW)>; 1470 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1471 fvti.Vector:$passthru, (fvti.Scalar (fpimm0)), VLOpFrag)), 1472 (!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX#"_TU") 1473 $passthru, 0, GPR:$vl, fvti.Log2SEW)>; 1474 1475 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1476 (fvti.Vector undef), (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1477 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1478 fvti.LMul.MX) 1479 (fvti.Scalar fvti.ScalarRegClass:$rs2), 1480 GPR:$vl, fvti.Log2SEW)>; 1481 def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl 1482 fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), 1483 (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # 1484 fvti.LMul.MX # "_TU") 1485 $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), 1486 GPR:$vl, fvti.Log2SEW)>; 1487 1488 // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions 1489 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; 1490 defm : VPatConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; 1491 defm : VPatConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; 1492 defm : VPatConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; 1493 1494 // 14.18. Widening Floating-Point/Integer Type-Convert Instructions 1495 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; 1496 defm : VPatWConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; 1497 defm : VPatWConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">; 1498 defm : VPatWConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFWCVT_F_XU_V">; 1499 foreach fvtiToFWti = AllWidenableFloatVectors in { 1500 defvar fvti = fvtiToFWti.Vti; 1501 defvar fwti = fvtiToFWti.Wti; 1502 def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1), 1503 (fvti.Mask true_mask), 1504 VLOpFrag)), 1505 (!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX) 1506 fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1507 } 1508 1509 // 14.19 Narrowing Floating-Point/Integer Type-Convert Instructions 1510 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_sint_vl, "PseudoVFNCVT_RTZ_X_F_W">; 1511 defm : VPatNConvertFP2ISDNode_V_VL<riscv_fp_to_uint_vl, "PseudoVFNCVT_RTZ_XU_F_W">; 1512 defm : VPatNConvertI2FPSDNode_V_VL<riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">; 1513 defm : VPatNConvertI2FPSDNode_V_VL<riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">; 1514 foreach fvtiToFWti = AllWidenableFloatVectors in { 1515 defvar fvti = fvtiToFWti.Vti; 1516 defvar fwti = fvtiToFWti.Wti; 1517 def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1), 1518 (fwti.Mask true_mask), 1519 VLOpFrag)), 1520 (!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX) 1521 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1522 1523 def : Pat<(fvti.Vector (riscv_fncvt_rod_vl (fwti.Vector fwti.RegClass:$rs1), 1524 (fwti.Mask true_mask), 1525 VLOpFrag)), 1526 (!cast<Instruction>("PseudoVFNCVT_ROD_F_F_W_"#fvti.LMul.MX) 1527 fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>; 1528 } 1529} 1530 1531} // Predicates = [HasVInstructionsAnyF] 1532 1533let Predicates = [HasVInstructions] in { 1534 1535foreach mti = AllMasks in { 1536 // 16.1 Vector Mask-Register Logical Instructions 1537 def : Pat<(mti.Mask (riscv_vmset_vl VLOpFrag)), 1538 (!cast<Instruction>("PseudoVMSET_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1539 def : Pat<(mti.Mask (riscv_vmclr_vl VLOpFrag)), 1540 (!cast<Instruction>("PseudoVMCLR_M_" # mti.BX) GPR:$vl, mti.Log2SEW)>; 1541 1542 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1543 (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) 1544 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1545 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1546 (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) 1547 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1548 def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, VLOpFrag)), 1549 (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) 1550 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1551 1552 def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, 1553 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1554 VLOpFrag)), 1555 (!cast<Instruction>("PseudoVMANDN_MM_" # mti.LMul.MX) 1556 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1557 def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, 1558 (riscv_vmnot_vl VR:$rs2, VLOpFrag), 1559 VLOpFrag)), 1560 (!cast<Instruction>("PseudoVMORN_MM_" # mti.LMul.MX) 1561 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1562 // XOR is associative so we need 2 patterns for VMXNOR. 1563 def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1, 1564 VLOpFrag), 1565 VR:$rs2, VLOpFrag)), 1566 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1567 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1568 1569 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2, 1570 VLOpFrag), 1571 VLOpFrag)), 1572 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1573 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1574 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, 1575 VLOpFrag), 1576 VLOpFrag)), 1577 (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) 1578 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1579 def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2, 1580 VLOpFrag), 1581 VLOpFrag)), 1582 (!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX) 1583 VR:$rs1, VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1584 1585 // Match the not idiom to the vmnot.m pseudo. 1586 def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, VLOpFrag)), 1587 (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) 1588 VR:$rs, VR:$rs, GPR:$vl, mti.Log2SEW)>; 1589 1590 // 16.2 Vector count population in mask vcpop.m 1591 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask true_mask), 1592 VLOpFrag)), 1593 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX) 1594 VR:$rs2, GPR:$vl, mti.Log2SEW)>; 1595 def : Pat<(XLenVT (riscv_vcpop_vl (mti.Mask VR:$rs2), (mti.Mask V0), 1596 VLOpFrag)), 1597 (!cast<Instruction>("PseudoVCPOP_M_" # mti.BX # "_MASK") 1598 VR:$rs2, (mti.Mask V0), GPR:$vl, mti.Log2SEW)>; 1599} 1600 1601} // Predicates = [HasVInstructions] 1602 1603let Predicates = [HasVInstructions] in { 1604// 17.1. Integer Scalar Move Instructions 1605// 17.4. Vector Register Gather Instruction 1606foreach vti = AllIntegerVectors in { 1607 def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge), 1608 vti.ScalarRegClass:$rs1, 1609 VLOpFrag)), 1610 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1611 vti.RegClass:$merge, 1612 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1613 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1614 (vti.Vector vti.RegClass:$rs1), 1615 (vti.Mask true_mask), 1616 VLOpFrag)), 1617 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1618 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1619 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1620 (vti.Mask true_mask), 1621 VLOpFrag)), 1622 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1623 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1624 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1625 (vti.Mask true_mask), 1626 VLOpFrag)), 1627 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1628 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1629 1630 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1631 (riscv_vrgather_vv_vl 1632 vti.RegClass:$rs2, 1633 vti.RegClass:$rs1, 1634 (vti.Mask true_mask), 1635 VLOpFrag), 1636 vti.RegClass:$merge, 1637 VLOpFrag)), 1638 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1639 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1640 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1641 1642 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1643 (riscv_vrgather_vx_vl 1644 vti.RegClass:$rs2, 1645 uimm5:$imm, 1646 (vti.Mask true_mask), 1647 VLOpFrag), 1648 vti.RegClass:$merge, 1649 VLOpFrag)), 1650 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1651 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1652 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1653 1654 // emul = lmul * 16 / sew 1655 defvar vlmul = vti.LMul; 1656 defvar octuple_lmul = vlmul.octuple; 1657 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1658 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1659 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1660 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1661 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1662 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1663 (ivti.Vector ivti.RegClass:$rs1), 1664 (vti.Mask true_mask), 1665 VLOpFrag)), 1666 (!cast<Instruction>(inst) 1667 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1668 1669 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1670 (riscv_vrgatherei16_vv_vl 1671 vti.RegClass:$rs2, 1672 (ivti.Vector ivti.RegClass:$rs1), 1673 (vti.Mask true_mask), 1674 VLOpFrag), 1675 vti.RegClass:$merge, 1676 VLOpFrag)), 1677 (!cast<Instruction>(inst#"_MASK") 1678 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1679 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1680 } 1681} 1682 1683} // Predicates = [HasVInstructions] 1684 1685let Predicates = [HasVInstructionsAnyF] in { 1686 1687// 17.2. Floating-Point Scalar Move Instructions 1688foreach vti = AllFloatVectors in { 1689 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1690 (vti.Scalar (fpimm0)), 1691 VLOpFrag)), 1692 (!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX) 1693 vti.RegClass:$merge, X0, GPR:$vl, vti.Log2SEW)>; 1694 def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge), 1695 vti.ScalarRegClass:$rs1, 1696 VLOpFrag)), 1697 (!cast<Instruction>("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) 1698 vti.RegClass:$merge, 1699 (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; 1700 defvar ivti = GetIntVTypeInfo<vti>.Vti; 1701 def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, 1702 (ivti.Vector vti.RegClass:$rs1), 1703 (vti.Mask true_mask), 1704 VLOpFrag)), 1705 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX) 1706 vti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1707 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1, 1708 (vti.Mask true_mask), 1709 VLOpFrag)), 1710 (!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX) 1711 vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; 1712 def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm, 1713 (vti.Mask true_mask), 1714 VLOpFrag)), 1715 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX) 1716 vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.Log2SEW)>; 1717 1718 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1719 (riscv_vrgather_vv_vl 1720 vti.RegClass:$rs2, 1721 (ivti.Vector vti.RegClass:$rs1), 1722 (vti.Mask true_mask), 1723 VLOpFrag), 1724 vti.RegClass:$merge, 1725 VLOpFrag)), 1726 (!cast<Instruction>("PseudoVRGATHER_VV_"# vti.LMul.MX#"_MASK") 1727 vti.RegClass:$merge, vti.RegClass:$rs2, vti.RegClass:$rs1, 1728 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1729 1730 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1731 (riscv_vrgather_vx_vl 1732 vti.RegClass:$rs2, 1733 uimm5:$imm, 1734 (vti.Mask true_mask), 1735 VLOpFrag), 1736 vti.RegClass:$merge, 1737 VLOpFrag)), 1738 (!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX#"_MASK") 1739 vti.RegClass:$merge, vti.RegClass:$rs2, uimm5:$imm, 1740 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1741 1742 defvar vlmul = vti.LMul; 1743 defvar octuple_lmul = vlmul.octuple; 1744 defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); 1745 if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { 1746 defvar emul_str = octuple_to_str<octuple_emul>.ret; 1747 defvar ivti = !cast<VTypeInfo>("VI16" # emul_str); 1748 defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_" # emul_str; 1749 def : Pat<(vti.Vector (riscv_vrgatherei16_vv_vl vti.RegClass:$rs2, 1750 (ivti.Vector ivti.RegClass:$rs1), 1751 (vti.Mask true_mask), 1752 VLOpFrag)), 1753 (!cast<Instruction>(inst) 1754 vti.RegClass:$rs2, ivti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; 1755 1756 def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask V0), 1757 (riscv_vrgatherei16_vv_vl 1758 vti.RegClass:$rs2, 1759 (ivti.Vector ivti.RegClass:$rs1), 1760 (vti.Mask true_mask), 1761 VLOpFrag), 1762 vti.RegClass:$merge, 1763 VLOpFrag)), 1764 (!cast<Instruction>(inst#"_MASK") 1765 vti.RegClass:$merge, vti.RegClass:$rs2, ivti.RegClass:$rs1, 1766 (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; 1767 } 1768} 1769 1770} // Predicates = [HasVInstructionsAnyF] 1771 1772//===----------------------------------------------------------------------===// 1773// Miscellaneous RISCVISD SDNodes 1774//===----------------------------------------------------------------------===// 1775 1776def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2, 1777 [SDTCisVec<0>, SDTCVecEltisVT<1, i1>, 1778 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>; 1779 1780def SDTRVVSlide : SDTypeProfile<1, 5, [ 1781 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisVT<3, XLenVT>, 1782 SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, SDTCisVT<5, XLenVT> 1783]>; 1784def SDTRVVSlide1 : SDTypeProfile<1, 5, [ 1785 SDTCisVec<0>, SDTCisSameAs<1, 0>, SDTCisSameAs<2, 0>, SDTCisInt<0>, 1786 SDTCisVT<3, XLenVT>, SDTCVecEltisVT<4, i1>, SDTCisSameNumEltsAs<0, 4>, 1787 SDTCisVT<5, XLenVT> 1788]>; 1789 1790def riscv_slideup_vl : SDNode<"RISCVISD::VSLIDEUP_VL", SDTRVVSlide, []>; 1791def riscv_slide1up_vl : SDNode<"RISCVISD::VSLIDE1UP_VL", SDTRVVSlide1, []>; 1792def riscv_slidedown_vl : SDNode<"RISCVISD::VSLIDEDOWN_VL", SDTRVVSlide, []>; 1793def riscv_slide1down_vl : SDNode<"RISCVISD::VSLIDE1DOWN_VL", SDTRVVSlide1, []>; 1794 1795let Predicates = [HasVInstructions] in { 1796 1797foreach vti = AllIntegerVectors in { 1798 def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask), 1799 VLOpFrag)), 1800 (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.Log2SEW)>; 1801 1802 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef), 1803 (vti.Vector vti.RegClass:$rs1), 1804 GPR:$rs2, (vti.Mask true_mask), 1805 VLOpFrag)), 1806 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX) 1807 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1808 def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rd), 1809 (vti.Vector vti.RegClass:$rs1), 1810 GPR:$rs2, (vti.Mask true_mask), 1811 VLOpFrag)), 1812 (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX#"_TU") 1813 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1814 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector undef), 1815 (vti.Vector vti.RegClass:$rs1), 1816 GPR:$rs2, (vti.Mask true_mask), 1817 VLOpFrag)), 1818 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX) 1819 vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1820 def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rd), 1821 (vti.Vector vti.RegClass:$rs1), 1822 GPR:$rs2, (vti.Mask true_mask), 1823 VLOpFrag)), 1824 (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX#"_TU") 1825 vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; 1826} 1827 1828foreach vti = !listconcat(AllIntegerVectors, AllFloatVectors) in { 1829 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1830 (vti.Vector vti.RegClass:$rs1), 1831 uimm5:$rs2, (vti.Mask true_mask), 1832 VLOpFrag)), 1833 (!cast<Instruction>("PseudoVSLIDEUP_VI_"#vti.LMul.MX) 1834 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1835 GPR:$vl, vti.Log2SEW)>; 1836 1837 def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), 1838 (vti.Vector vti.RegClass:$rs1), 1839 GPR:$rs2, (vti.Mask true_mask), 1840 VLOpFrag)), 1841 (!cast<Instruction>("PseudoVSLIDEUP_VX_"#vti.LMul.MX) 1842 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1843 GPR:$vl, vti.Log2SEW)>; 1844 1845 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1846 (vti.Vector vti.RegClass:$rs1), 1847 uimm5:$rs2, (vti.Mask true_mask), 1848 VLOpFrag)), 1849 (!cast<Instruction>("PseudoVSLIDEDOWN_VI_"#vti.LMul.MX) 1850 vti.RegClass:$rs3, vti.RegClass:$rs1, uimm5:$rs2, 1851 GPR:$vl, vti.Log2SEW)>; 1852 1853 def : Pat<(vti.Vector (riscv_slidedown_vl (vti.Vector vti.RegClass:$rs3), 1854 (vti.Vector vti.RegClass:$rs1), 1855 GPR:$rs2, (vti.Mask true_mask), 1856 VLOpFrag)), 1857 (!cast<Instruction>("PseudoVSLIDEDOWN_VX_"#vti.LMul.MX) 1858 vti.RegClass:$rs3, vti.RegClass:$rs1, GPR:$rs2, 1859 GPR:$vl, vti.Log2SEW)>; 1860} 1861 1862} // Predicates = [HasVInstructions] 1863