1//===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the RISC-V instructions in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
14include "RISCVInstrFormats.td"
15
16def simm12 : Operand<i32>;
17
18// As noted in RISCVRegisterInfo.td, the hope is that support for
19// variable-sized register classes will mean that instruction definitions do
20// not need to be duplicated for 32-bit and 64-bit register classes. For now
21// we use 'GPR', which is 32-bit. When codegen for both RV32 and RV64 is
22// added, we will need to duplicate instruction definitions unless a proposal
23// like <http://lists.llvm.org/pipermail/llvm-dev/2016-September/105027.html>
24// is adopted.
25
26class ALU_ri<bits<3> funct3, string OpcodeStr> :
27      FI<funct3, 0b0010011, (outs GPR:$rd), (ins GPR:$rs1, simm12:$imm12),
28         OpcodeStr#"\t$rd, $rs1, $imm12", []>
29{
30}
31
32def ADDI  : ALU_ri<0b000, "addi">;
33def SLTI  : ALU_ri<0b010, "slti">;
34def SLTIU : ALU_ri<0b011, "sltiu">;
35def XORI  : ALU_ri<0b100, "xori">;
36def ORI   : ALU_ri<0b110, "ori">;
37def ANDI  : ALU_ri<0b111, "andi">;
38
39class ALU_rr<bits<7> funct7, bits<3> funct3, string OpcodeStr> :
40      FR<funct7, funct3, 0b0110011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
41         OpcodeStr#"\t$rd, $rs1, $rs2", []>
42{
43}
44
45def ADD  : ALU_rr<0b0000000, 0b000, "add">;
46def SUB  : ALU_rr<0b0100000, 0b000, "sub">;
47def SLL  : ALU_rr<0b0000000, 0b001, "sll">;
48def SLT  : ALU_rr<0b0000000, 0b010, "slt">;
49def SLTU : ALU_rr<0b0000000, 0b011, "sltu">;
50def XOR  : ALU_rr<0b0000000, 0b100, "xor">;
51def SRL  : ALU_rr<0b0000000, 0b101, "srl">;
52def SRA  : ALU_rr<0b0100000, 0b101, "sra">;
53def OR   : ALU_rr<0b0000000, 0b110, "or">;
54def AND  : ALU_rr<0b0000000, 0b111, "and">;
55
56